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Adjust the comments about translating clock divisor bits to match recent

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code changes.
This commit is contained in:
Ian Lepore 2014-04-04 15:03:03 +00:00
parent 7de2785827
commit 922e7b19a7
1 changed files with 8 additions and 8 deletions
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16
sys/arm/ti/ti_sdhci.c
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@ -167,13 +167,12 @@ ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
* but doesn't split them into low:high fields. Instead they're a
* single number in the range 0..1023 and the number is exactly the
* clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI
* driver code expects a v2.0 divisor (value N is power of two in the
* range 0..128 and clock is divided by 2N). The shifting and masking
* driver code expects a v2.0 or v3.0 divisor. The shifting and masking
* here extracts the MMCHS representation from the hardware word, cleans
* those bits out, applies the 2N adjustment, and plugs that into the
* bit positions for the 2.0 divisor in the returned register value. The
* ti_sdhci_write_2() routine performs the opposite transformation when
* the SDHCI driver writes to the register.
* those bits out, applies the 2N adjustment, and plugs the result into
* the bit positions for the 2.0 or 3.0 divisor in the returned register
* value. The ti_sdhci_write_2() routine performs the opposite
* transformation when the SDHCI driver writes to the register.
*/
if (off == SDHCI_CLOCK_CONTROL) {
val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
@ -254,8 +253,9 @@ ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
uint32_t clkdiv, val32;
/*
* Translate between the hardware and SDHCI 2.0 representations of the
* clock divisor. See the comments in ti_sdhci_read_2() for details.
* Translate between the hardware and SDHCI 2.0 or 3.0 representations
* of the clock divisor. See the comments in ti_sdhci_read_2() for
* details.
*/
if (off == SDHCI_CLOCK_CONTROL) {
clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;