Fix the logic for translating between MMCHS and SDHCI clock divisors.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
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3490c30476
commit
927f53548b
@ -111,6 +111,9 @@ static struct ofw_compat_data compat_data[] = {
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#define MMCHS_CON 0x02C
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#define MMCHS_CON_DW8 (1 << 5)
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#define MMCHS_CON_DVAL_8_4MS (3 << 9)
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#define MMCHS_SYSCTL 0x12C
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#define MMCHS_SYSCTL_CLKD_MASK 0x3FF
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#define MMCHS_SYSCTL_CLKD_SHIFT 6
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#define MMCHS_SD_CAPA 0x140
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#define MMCHS_SD_CAPA_VS18 (1 << 26)
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#define MMCHS_SD_CAPA_VS30 (1 << 25)
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@ -174,9 +177,13 @@ ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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*/
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if (off == SDHCI_CLOCK_CONTROL) {
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val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
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clkdiv = (val32 >> SDHCI_DIVIDER_HI_SHIFT) & 0xff;
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val32 &= ~(0xff << SDHCI_DIVIDER_HI_SHIFT);
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val32 |= (clkdiv / 2) << SDHCI_DIVIDER_SHIFT;
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clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) &
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MMCHS_SYSCTL_CLKD_MASK) / 2;
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val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT);
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val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
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if (slot->version >= SDHCI_SPEC_300)
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val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) &
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SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT;
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return (val32 & 0xffff);
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}
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@ -252,10 +259,17 @@ ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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*/
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if (off == SDHCI_CLOCK_CONTROL) {
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clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
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if (slot->version >= SDHCI_SPEC_300)
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clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) &
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SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN;
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clkdiv *= 2;
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if (clkdiv > MMCHS_SYSCTL_CLKD_MASK)
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clkdiv = MMCHS_SYSCTL_CLKD_MASK;
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val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
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val32 &= 0xffff0000;
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val32 |= val & ~(SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT);
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val32 |= (clkdiv * 2) << SDHCI_DIVIDER_HI_SHIFT;
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val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK <<
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MMCHS_SYSCTL_CLKD_SHIFT);
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val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT;
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WR4(sc, SDHCI_CLOCK_CONTROL, val32);
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return;
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}
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