Add necessary bits for Linux KPI to work correctly on powerpc
PowerPC, and possibly other architectures, use different address ranges for PCI space vs physical address space, which is only mapped at resource activation time, when the BAR gets written. The DRM kernel modules do not activate the rman resources, soas not to waste KVA, instead only mapping parts of the PCI memory at a time. This introduces a BUS_TRANSLATE_RESOURCE() method, implemented in the Open Firmware/FDT PCI driver, to perform this necessary translation without activating the resource. In addition to system KPI changes, LinuxKPI is updated to handle a big-endian host, by adding proper endian swaps to the I/O functions. Submitted by: mmacy Reported by: hselasky Differential Revision: https://reviews.freebsd.org/D21096
This commit is contained in:
Justin Hibbits
parent
69a277d98e
commit
937a05ba81
@ -56,6 +56,7 @@
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#define __GFP_IO 0
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#define __GFP_NO_KSWAPD 0
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#define __GFP_KSWAPD_RECLAIM 0
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#define __GFP_WAIT M_WAITOK
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#define __GFP_DMA32 (1U << 24) /* LinuxKPI only */
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#define __GFP_BITS_SHIFT 25
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@ -42,6 +42,32 @@
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* XXX This is all x86 specific. It should be bus space access.
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*/
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/* rmb and wmb are declared in machine/atomic.h, so should be included first. */
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#ifndef __io_br
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#define __io_br() __compiler_membar()
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#endif
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#ifndef __io_ar
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#ifdef rmb
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#define __io_ar() rmb()
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#else
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#define __io_ar() __compiler_membar()
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#endif
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#endif
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#ifndef __io_bw
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#ifdef wmb
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#define __io_bw() wmb()
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#else
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#define __io_bw() __compiler_membar()
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#endif
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#endif
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#ifndef __io_aw
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#define __io_aw() __compiler_membar()
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#endif
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/* Access MMIO registers atomically without barriers and byte swapping. */
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static inline uint8_t
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@ -112,9 +138,9 @@ readb(const volatile void *addr)
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{
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uint8_t v;
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__compiler_membar();
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__io_br();
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v = *(const volatile uint8_t *)addr;
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__compiler_membar();
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__io_ar();
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return (v);
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}
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#define readb(addr) readb(addr)
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@ -123,9 +149,9 @@ readb(const volatile void *addr)
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static inline void
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writeb(uint8_t v, volatile void *addr)
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{
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__compiler_membar();
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__io_bw();
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*(volatile uint8_t *)addr = v;
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__compiler_membar();
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__io_aw();
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}
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#define writeb(v, addr) writeb(v, addr)
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@ -135,9 +161,9 @@ readw(const volatile void *addr)
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{
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uint16_t v;
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__compiler_membar();
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v = *(const volatile uint16_t *)addr;
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__compiler_membar();
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__io_br();
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v = le16toh(__raw_readw(addr));
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__io_ar();
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return (v);
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}
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#define readw(addr) readw(addr)
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@ -146,9 +172,9 @@ readw(const volatile void *addr)
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static inline void
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writew(uint16_t v, volatile void *addr)
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{
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__compiler_membar();
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*(volatile uint16_t *)addr = v;
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__compiler_membar();
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__io_bw();
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__raw_writew(htole16(v), addr);
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__io_aw();
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}
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#define writew(v, addr) writew(v, addr)
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@ -158,9 +184,9 @@ readl(const volatile void *addr)
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{
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uint32_t v;
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__compiler_membar();
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v = *(const volatile uint32_t *)addr;
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__compiler_membar();
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__io_br();
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v = le32toh(__raw_readl(addr));
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__io_ar();
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return (v);
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}
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#define readl(addr) readl(addr)
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@ -169,9 +195,9 @@ readl(const volatile void *addr)
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static inline void
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writel(uint32_t v, volatile void *addr)
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{
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__compiler_membar();
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*(volatile uint32_t *)addr = v;
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__compiler_membar();
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__io_bw();
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__raw_writel(htole32(v), addr);
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__io_aw();
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}
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#define writel(v, addr) writel(v, addr)
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@ -183,9 +209,9 @@ readq(const volatile void *addr)
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{
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uint64_t v;
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__compiler_membar();
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v = *(const volatile uint64_t *)addr;
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__compiler_membar();
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__io_br();
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v = le64toh(__raw_readq(addr));
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__io_ar();
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return (v);
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}
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#define readq(addr) readq(addr)
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@ -193,9 +219,9 @@ readq(const volatile void *addr)
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static inline void
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writeq(uint64_t v, volatile void *addr)
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{
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__compiler_membar();
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*(volatile uint64_t *)addr = v;
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__compiler_membar();
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__io_bw();
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__raw_writeq(htole64(v), addr);
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__io_aw();
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}
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#define writeq(v, addr) writeq(v, addr)
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#endif
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@ -206,7 +232,7 @@ writeq(uint64_t v, volatile void *addr)
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static inline uint8_t
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readb_relaxed(const volatile void *addr)
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{
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return (*(const volatile uint8_t *)addr);
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return (__raw_readb(addr));
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}
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#define readb_relaxed(addr) readb_relaxed(addr)
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@ -214,7 +240,7 @@ readb_relaxed(const volatile void *addr)
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static inline void
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writeb_relaxed(uint8_t v, volatile void *addr)
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{
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*(volatile uint8_t *)addr = v;
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__raw_writeb(v, addr);
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}
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#define writeb_relaxed(v, addr) writeb_relaxed(v, addr)
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@ -222,7 +248,7 @@ writeb_relaxed(uint8_t v, volatile void *addr)
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static inline uint16_t
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readw_relaxed(const volatile void *addr)
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{
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return (*(const volatile uint16_t *)addr);
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return (le16toh(__raw_readw(addr)));
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}
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#define readw_relaxed(addr) readw_relaxed(addr)
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@ -230,7 +256,7 @@ readw_relaxed(const volatile void *addr)
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static inline void
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writew_relaxed(uint16_t v, volatile void *addr)
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{
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*(volatile uint16_t *)addr = v;
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__raw_writew(htole16(v), addr);
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}
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#define writew_relaxed(v, addr) writew_relaxed(v, addr)
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@ -238,7 +264,7 @@ writew_relaxed(uint16_t v, volatile void *addr)
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static inline uint32_t
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readl_relaxed(const volatile void *addr)
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{
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return (*(const volatile uint32_t *)addr);
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return (le32toh(__raw_readl(addr)));
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}
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#define readl_relaxed(addr) readl_relaxed(addr)
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@ -246,7 +272,7 @@ readl_relaxed(const volatile void *addr)
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static inline void
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writel_relaxed(uint32_t v, volatile void *addr)
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{
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*(volatile uint32_t *)addr = v;
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__raw_writel(htole32(v), addr);
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}
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#define writel_relaxed(v, addr) writel_relaxed(v, addr)
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@ -256,14 +282,14 @@ writel_relaxed(uint32_t v, volatile void *addr)
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static inline uint64_t
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readq_relaxed(const volatile void *addr)
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{
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return (*(const volatile uint64_t *)addr);
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return (le64toh(__raw_readq(addr)));
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}
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#define readq_relaxed(addr) readq_relaxed(addr)
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static inline void
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writeq_relaxed(uint64_t v, volatile void *addr)
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{
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*(volatile uint64_t *)addr = v;
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__raw_writeq(htole64(v), addr);
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}
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#define writeq_relaxed(v, addr) writeq_relaxed(v, addr)
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#endif
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@ -290,7 +316,13 @@ ioread16(const volatile void *addr)
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static inline uint16_t
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ioread16be(const volatile void *addr)
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{
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return (bswap16(readw(addr)));
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uint16_t v;
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__io_br();
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v = (be16toh(__raw_readw(addr)));
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__io_ar();
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return (v);
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}
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#define ioread16be(addr) ioread16be(addr)
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@ -306,7 +338,13 @@ ioread32(const volatile void *addr)
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static inline uint32_t
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ioread32be(const volatile void *addr)
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{
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return (bswap32(readl(addr)));
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uint32_t v;
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__io_br();
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v = (be32toh(__raw_readl(addr)));
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__io_ar();
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return (v);
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}
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#define ioread32be(addr) ioread32be(addr)
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@ -338,7 +376,9 @@ iowrite32(uint32_t v, volatile void *addr)
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static inline void
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iowrite32be(uint32_t v, volatile void *addr)
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{
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writel(bswap32(v), addr);
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__io_bw();
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__raw_writel(htobe32(v), addr);
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__io_aw();
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}
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#define iowrite32be(v, addr) iowrite32be(v, addr)
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@ -205,6 +205,7 @@ struct pci_driver {
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struct pci_bus {
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struct pci_dev *self;
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int domain;
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int number;
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};
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@ -270,26 +271,6 @@ linux_pci_find_irq_dev(unsigned int irq)
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return (found);
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}
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static inline unsigned long
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pci_resource_start(struct pci_dev *pdev, int bar)
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{
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struct resource_list_entry *rle;
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if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
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return (0);
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return rle->start;
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}
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static inline unsigned long
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pci_resource_len(struct pci_dev *pdev, int bar)
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{
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struct resource_list_entry *rle;
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if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
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return (0);
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return rle->count;
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}
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static inline int
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pci_resource_type(struct pci_dev *pdev, int bar)
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{
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@ -447,6 +428,9 @@ pci_disable_msix(struct pci_dev *pdev)
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pdev->dev.msix_max = 0;
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}
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unsigned long pci_resource_start(struct pci_dev *pdev, int bar);
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unsigned long pci_resource_len(struct pci_dev *pdev, int bar);
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static inline bus_addr_t
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pci_bus_address(struct pci_dev *pdev, int bar)
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{
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@ -633,7 +617,7 @@ static inline void pci_disable_sriov(struct pci_dev *dev)
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/* XXX This should not be necessary. */
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#define pcix_set_mmrbc(d, v) 0
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#define pcix_get_max_mmrbc(d) 0
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#define pcie_set_readrq(d, v) 0
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#define pcie_set_readrq(d, v) pci_set_max_read_req(&(d)->dev, (v))
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#define PCI_DMA_BIDIRECTIONAL 0
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#define PCI_DMA_TODEVICE 1
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@ -29,12 +29,12 @@ __FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <sys/fcntl.h>
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#include <sys/file.h>
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#include <sys/filio.h>
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@ -209,7 +209,6 @@ linux_pci_attach(device_t dev)
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struct pci_driver *pdrv;
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const struct pci_device_id *id;
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device_t parent;
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devclass_t devclass;
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int error;
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linux_set_current(curthread);
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@ -218,7 +217,6 @@ linux_pci_attach(device_t dev)
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pdev = device_get_softc(dev);
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parent = device_get_parent(dev);
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devclass = device_get_devclass(parent);
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if (pdrv->isdrm) {
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dinfo = device_get_ivars(parent);
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device_set_ivars(dev, dinfo);
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@ -254,6 +252,7 @@ linux_pci_attach(device_t dev)
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pbus = malloc(sizeof(*pbus), M_DEVBUF, M_WAITOK | M_ZERO);
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pbus->self = pdev;
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pbus->number = pci_get_bus(dev);
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pbus->domain = pci_get_domain(dev);
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pdev->bus = pbus;
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spin_lock(&pci_lock);
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@ -388,6 +387,36 @@ linux_pci_register_driver(struct pci_driver *pdrv)
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return (_linux_pci_register_driver(pdrv, dc));
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}
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unsigned long
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pci_resource_start(struct pci_dev *pdev, int bar)
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{
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struct resource_list_entry *rle;
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unsigned long newstart;
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device_t dev;
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if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
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return (0);
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dev = pci_find_dbsf(pdev->bus->domain, pdev->bus->number,
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PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
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MPASS(dev != NULL);
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if (BUS_TRANSLATE_RESOURCE(dev, rle->type, rle->start, &newstart)) {
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device_printf(pdev->dev.bsddev, "translate of %#lx failed\n",
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rle->start);
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return (0);
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}
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return (newstart);
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}
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unsigned long
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pci_resource_len(struct pci_dev *pdev, int bar)
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{
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struct resource_list_entry *rle;
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if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
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return (0);
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return (rle->count);
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}
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int
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linux_pci_register_drm_driver(struct pci_driver *pdrv)
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{
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@ -76,6 +76,8 @@ static int ofw_pci_deactivate_resource(device_t, device_t, int, int,
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struct resource *);
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static int ofw_pci_adjust_resource(device_t, device_t, int,
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struct resource *, rman_res_t, rman_res_t);
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static int ofw_pci_translate_resource(device_t bus, int type,
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rman_res_t start, rman_res_t *newstart);
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#ifdef __powerpc__
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static bus_space_tag_t ofw_pci_bus_get_bus_tag(device_t, device_t);
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@ -116,6 +118,7 @@ static device_method_t ofw_pci_methods[] = {
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DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource),
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DEVMETHOD(bus_deactivate_resource, ofw_pci_deactivate_resource),
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DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource),
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DEVMETHOD(bus_translate_resource, ofw_pci_translate_resource),
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#ifdef __powerpc__
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DEVMETHOD(bus_get_bus_tag, ofw_pci_bus_get_bus_tag),
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#endif
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@ -478,6 +481,45 @@ ofw_pci_release_resource(device_t bus, device_t child, int type, int rid,
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return (rman_release_resource(res));
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}
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static int
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ofw_pci_translate_resource(device_t bus, int type, rman_res_t start,
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rman_res_t *newstart)
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{
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struct ofw_pci_softc *sc;
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struct ofw_pci_range *rp;
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int space;
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sc = device_get_softc(bus);
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/*
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* Map this through the ranges list
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*/
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for (rp = sc->sc_range; rp < sc->sc_range + sc->sc_nrange &&
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rp->pci_hi != 0; rp++) {
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if (start < rp->pci || start >= rp->pci + rp->size)
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continue;
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switch (rp->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) {
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case OFW_PCI_PHYS_HI_SPACE_IO:
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space = SYS_RES_IOPORT;
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break;
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case OFW_PCI_PHYS_HI_SPACE_MEM32:
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case OFW_PCI_PHYS_HI_SPACE_MEM64:
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space = SYS_RES_MEMORY;
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break;
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default:
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space = -1;
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}
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if (type == space) {
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start += (rp->host - rp->pci);
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break;
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}
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}
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*newstart = start;
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return (0);
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}
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static int
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ofw_pci_activate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *res)
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@ -142,11 +142,35 @@ vga_pci_is_boot_display(device_t dev)
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return (1);
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}
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static void
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vga_pci_reset(device_t dev)
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{
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int ps;
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/*
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* FLR is unsupported on GPUs so attempt a power-management reset by cycling
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* the device in/out of D3 state.
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* PCI spec says we can only go into D3 state from D0 state.
|
||||
* Transition from D[12] into D0 before going to D3 state.
|
||||
*/
|
||||
ps = pci_get_powerstate(dev);
|
||||
if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
|
||||
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
|
||||
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
|
||||
pci_set_powerstate(dev, PCI_POWERSTATE_D3);
|
||||
pci_set_powerstate(dev, ps);
|
||||
}
|
||||
|
||||
|
||||
void *
|
||||
vga_pci_map_bios(device_t dev, size_t *size)
|
||||
{
|
||||
int rid;
|
||||
struct vga_resource *vr;
|
||||
struct resource *res;
|
||||
device_t pcib;
|
||||
uint32_t rom_addr;
|
||||
uint16_t config;
|
||||
volatile char *bios;
|
||||
int i, rid, found;
|
||||
|
||||
#if defined(__amd64__) || defined(__i386__)
|
||||
if (vga_pci_is_boot_display(dev)) {
|
||||
@ -164,21 +188,96 @@ vga_pci_map_bios(device_t dev, size_t *size)
|
||||
}
|
||||
#endif
|
||||
|
||||
rid = PCIR_BIOS;
|
||||
pcib = device_get_parent(device_get_parent(dev));
|
||||
if (device_get_devclass(device_get_parent(pcib)) ==
|
||||
devclass_find("pci")) {
|
||||
/*
|
||||
* The parent bridge is a PCI-to-PCI bridge: check the
|
||||
* value of the "VGA Enable" bit.
|
||||
*/
|
||||
config = pci_read_config(pcib, PCIR_BRIDGECTL_1, 2);
|
||||
if ((config & PCIB_BCR_VGA_ENABLE) == 0) {
|
||||
config |= PCIB_BCR_VGA_ENABLE;
|
||||
pci_write_config(pcib, PCIR_BRIDGECTL_1, config, 2);
|
||||
}
|
||||
}
|
||||
|
||||
switch(pci_read_config(dev, PCIR_HDRTYPE, 1)) {
|
||||
case PCIM_HDRTYPE_BRIDGE:
|
||||
rid = PCIR_BIOS_1;
|
||||
break;
|
||||
case PCIM_HDRTYPE_CARDBUS:
|
||||
rid = 0;
|
||||
break;
|
||||
default:
|
||||
rid = PCIR_BIOS;
|
||||
break;
|
||||
}
|
||||
if (rid == 0)
|
||||
return (NULL);
|
||||
res = vga_pci_alloc_resource(dev, NULL, SYS_RES_MEMORY, &rid, 0,
|
||||
~0, 1, RF_ACTIVE);
|
||||
|
||||
if (res == NULL) {
|
||||
device_printf(dev, "vga_pci_alloc_resource failed\n");
|
||||
return (NULL);
|
||||
}
|
||||
bios = rman_get_virtual(res);
|
||||
*size = rman_get_size(res);
|
||||
for (found = i = 0; i < hz; i++) {
|
||||
found = (bios[0] == 0x55 && bios[1] == 0xaa);
|
||||
if (found)
|
||||
break;
|
||||
pause("vgabios", 1);
|
||||
}
|
||||
if (found)
|
||||
return (__DEVOLATILE(void *, bios));
|
||||
if (bootverbose)
|
||||
device_printf(dev, "initial ROM mapping failed -- resetting\n");
|
||||
|
||||
/*
|
||||
* Enable ROM decode
|
||||
*/
|
||||
vga_pci_reset(dev);
|
||||
rom_addr = pci_read_config(dev, rid, 4);
|
||||
rom_addr &= 0x7ff;
|
||||
rom_addr |= rman_get_start(res) | 0x1;
|
||||
pci_write_config(dev, rid, rom_addr, 4);
|
||||
vr = lookup_res(device_get_softc(dev), rid);
|
||||
vga_pci_release_resource(dev, NULL, SYS_RES_MEMORY, rid,
|
||||
vr->vr_res);
|
||||
|
||||
/*
|
||||
* re-allocate
|
||||
*/
|
||||
res = vga_pci_alloc_resource(dev, NULL, SYS_RES_MEMORY, &rid, 0,
|
||||
~0, 1, RF_ACTIVE);
|
||||
if (res == NULL) {
|
||||
device_printf(dev, "vga_pci_alloc_resource failed\n");
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
bios = rman_get_virtual(res);
|
||||
*size = rman_get_size(res);
|
||||
return (rman_get_virtual(res));
|
||||
for (found = i = 0; i < 3*hz; i++) {
|
||||
found = (bios[0] == 0x55 && bios[1] == 0xaa);
|
||||
if (found)
|
||||
break;
|
||||
pause("vgabios", 1);
|
||||
}
|
||||
if (found)
|
||||
return (__DEVOLATILE(void *, bios));
|
||||
device_printf(dev, "ROM mapping failed\n");
|
||||
vr = lookup_res(device_get_softc(dev), rid);
|
||||
vga_pci_release_resource(dev, NULL, SYS_RES_MEMORY, rid,
|
||||
vr->vr_res);
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
void
|
||||
vga_pci_unmap_bios(device_t dev, void *bios)
|
||||
{
|
||||
struct vga_resource *vr;
|
||||
int rid;
|
||||
|
||||
if (bios == NULL) {
|
||||
return;
|
||||
@ -192,16 +291,28 @@ vga_pci_unmap_bios(device_t dev, void *bios)
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
switch(pci_read_config(dev, PCIR_HDRTYPE, 1)) {
|
||||
case PCIM_HDRTYPE_BRIDGE:
|
||||
rid = PCIR_BIOS_1;
|
||||
break;
|
||||
case PCIM_HDRTYPE_CARDBUS:
|
||||
rid = 0;
|
||||
break;
|
||||
default:
|
||||
rid = PCIR_BIOS;
|
||||
break;
|
||||
}
|
||||
if (rid == 0)
|
||||
return;
|
||||
/*
|
||||
* Look up the PCIR_BIOS resource in our softc. It should match
|
||||
* the address we returned previously.
|
||||
*/
|
||||
vr = lookup_res(device_get_softc(dev), PCIR_BIOS);
|
||||
vr = lookup_res(device_get_softc(dev), rid);
|
||||
KASSERT(vr->vr_res != NULL, ("vga_pci_unmap_bios: bios not mapped"));
|
||||
KASSERT(rman_get_virtual(vr->vr_res) == bios,
|
||||
("vga_pci_unmap_bios: mismatch"));
|
||||
vga_pci_release_resource(dev, NULL, SYS_RES_MEMORY, PCIR_BIOS,
|
||||
vga_pci_release_resource(dev, NULL, SYS_RES_MEMORY, rid,
|
||||
vr->vr_res);
|
||||
}
|
||||
|
||||
|
||||
@ -76,6 +76,18 @@ CODE {
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
null_translate_resource(device_t bus, int type, rman_res_t start,
|
||||
rman_res_t *newstart)
|
||||
{
|
||||
if (device_get_parent(bus) != NULL)
|
||||
return (BUS_TRANSLATE_RESOURCE(device_get_parent(bus),
|
||||
type, start, newstart));
|
||||
|
||||
*newstart = start;
|
||||
return (0);
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
@ -406,6 +418,23 @@ METHOD int adjust_resource {
|
||||
rman_res_t _end;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @brief translate a resource value
|
||||
*
|
||||
*
|
||||
* @param _dev the device associated with the resource
|
||||
* @param _type the type of resource
|
||||
* @param _start the starting address of the resource range
|
||||
* @param _newstart the new starting address of the resource range
|
||||
*/
|
||||
METHOD int translate_resource {
|
||||
device_t _dev;
|
||||
int _type;
|
||||
rman_res_t _start;
|
||||
rman_res_t *_newstart;
|
||||
} DEFAULT null_translate_resource;
|
||||
|
||||
/**
|
||||
* @brief Release a resource
|
||||
*
|
||||
|
||||
@ -3971,7 +3971,6 @@ bus_helper_reset_prepare(device_t dev, int flags)
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Helper function for implementing BUS_PRINT_CHILD().
|
||||
*
|
||||
|
||||
@ -434,6 +434,8 @@ struct resource *
|
||||
bus_generic_alloc_resource(device_t bus, device_t child, int type,
|
||||
int *rid, rman_res_t start, rman_res_t end,
|
||||
rman_res_t count, u_int flags);
|
||||
int bus_generic_translate_resource(device_t dev, int type, rman_res_t start,
|
||||
rman_res_t *newstart);
|
||||
int bus_generic_attach(device_t dev);
|
||||
int bus_generic_bind_intr(device_t dev, device_t child,
|
||||
struct resource *irq, int cpu);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user