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Add Firmware Reset Level, MFRL, register accessors in mlx5core.

Browse Source 
Submitted by:	kib@
MFC after:	3 days
Sponsored by:	Mellanox Technologies
This commit is contained in:
Hans Petter Selasky 2019-05-08 11:04:40 +00:00
parent 13a2290c66
commit 939c79a213
5 changed files with 39 additions and 0 deletions
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5
sys/dev/mlx5/device.h
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@ -1218,6 +1218,11 @@ enum {
MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
};
enum {
MLX5_FRL_LEVEL3 = 0x8,
MLX5_FRL_LEVEL6 = 0x40,
};
/* 8 regular priorities + 1 for multicast */
#define MLX5_NUM_BYPASS_FTS 9

1
sys/dev/mlx5/driver.h
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@ -154,6 +154,7 @@ enum {
MLX5_REG_HOST_ENDIANNESS = 0x7004,
MLX5_REG_MTMP = 0x900a,
MLX5_REG_MCIA = 0x9014,
MLX5_REG_MFRL = 0x9028,
MLX5_REG_MPCNT = 0x9051,
MLX5_REG_MCQI = 0x9061,
MLX5_REG_MCC = 0x9062,

2
sys/dev/mlx5/mlx5_core/mlx5_core.h
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@ -82,6 +82,8 @@ int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam,
u8 feature_group, u8 access_reg_group);
int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap,
u8 feature_group, u8 access_reg_group);
int mlx5_query_mfrl_reg(struct mlx5_core_dev *mdev, u8 *reset_level);
int mlx5_set_mfrl_reg(struct mlx5_core_dev *mdev, u8 reset_level);
int mlx5_cmd_init_hca(struct mlx5_core_dev *dev);
int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);

26
sys/dev/mlx5/mlx5_core/mlx5_port.c
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@ -1210,3 +1210,29 @@ int mlx5_query_pddr_range_info(struct mlx5_core_dev *mdev, u8 local_port, u8 *is
return (0);
}
EXPORT_SYMBOL_GPL(mlx5_query_pddr_range_info);
int
mlx5_query_mfrl_reg(struct mlx5_core_dev *mdev, u8 *reset_level)
{
u32 mfrl[MLX5_ST_SZ_DW(mfrl_reg)] = {};
int sz = MLX5_ST_SZ_BYTES(mfrl_reg);
int err;
err = mlx5_core_access_reg(mdev, mfrl, sz, mfrl, sz, MLX5_REG_MFRL,
0, 0);
if (err == 0)
*reset_level = MLX5_GET(mfrl_reg, mfrl, reset_level);
return (err);
}
int
mlx5_set_mfrl_reg(struct mlx5_core_dev *mdev, u8 reset_level)
{
u32 mfrl[MLX5_ST_SZ_DW(mfrl_reg)] = {};
int sz = MLX5_ST_SZ_BYTES(mfrl_reg);
MLX5_SET(mfrl_reg, mfrl, reset_level, reset_level);
return (mlx5_core_access_reg(mdev, mfrl, sz, mfrl, sz, MLX5_REG_MFRL,
0, 1));
}

5
sys/dev/mlx5/mlx5_ifc.h
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@ -10409,4 +10409,9 @@ struct mlx5_ifc_qpts_reg_bits {
u8 trust_state[0x3];
};
struct mlx5_ifc_mfrl_reg_bits {
u8 reserved_at_0[0x38];
u8 reset_level[0x8];
};
#endif /* MLX5_IFC_H */