Add the codes for enabling CPU cores of Rockchip RK3188 SoC.
Enable SMP for Radxa Rock board. Approved by: stas (mentor)
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ganbold
parent
9913c6f0ef
commit
93d0ee130f
@ -121,3 +121,4 @@ options FDT
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options FDT_DTB_STATIC
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makeoptions FDT_DTS_FILE=rk3188-radxa.dts
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options SMP # Enable multiple cores
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@ -19,3 +19,4 @@ arm/rockchip/rk30xx_grf.c standard
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arm/rockchip/rk30xx_wdog.c standard
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arm/rockchip/rk30xx_gpio.c optional gpio
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dev/usb/controller/dwc_otg_fdt.c optional dwcotg
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arm/rockchip/rk30xx_mp.c optional smp
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@ -85,6 +85,7 @@ int
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initarm_devmap_init(void)
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{
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arm_devmap_add_entry(0x10000000, 0x00200000);
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arm_devmap_add_entry(0x20000000, 0x00100000);
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return (0);
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192
sys/arm/rockchip/rk30xx_mp.c
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192
sys/arm/rockchip/rk30xx_mp.c
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@ -0,0 +1,192 @@
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/*-
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* Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#define SCU_PHYSBASE 0x1013c000
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#define SCU_SIZE 0x100
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#define SCU_CONTROL_REG 0x00
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#define SCU_CONTROL_ENABLE (1 << 0)
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#define SCU_STANDBY_EN (1 << 5)
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#define SCU_CONFIG_REG 0x04
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#define SCU_CONFIG_REG_NCPU_MASK 0x03
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#define SCU_CPUPOWER_REG 0x08
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#define SCU_INV_TAGS_REG 0x0c
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#define SCU_FILTER_START_REG 0x10
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#define SCU_FILTER_END_REG 0x14
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#define SCU_SECURE_ACCESS_REG 0x18
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#define SCU_NONSECURE_ACCESS_REG 0x1c
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#define IMEM_PHYSBASE 0x10080000
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#define IMEM_SIZE 0x20
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#define PMU_PHYSBASE 0x20004000
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#define PMU_SIZE 0x100
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#define PMU_PWRDN_CON 0x08
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#define PMU_PWRDN_SCU (1 << 4)
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extern char *mpentry_addr;
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static void rk30xx_boot2(void);
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static void
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rk30xx_boot2(void)
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{
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__asm __volatile(
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"ldr pc, 1f\n"
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".globl mpentry_addr\n"
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"mpentry_addr:\n"
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"1: .space 4\n");
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}
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void
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platform_mp_init_secondary(void)
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{
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gic_init_secondary();
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}
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void
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platform_mp_setmaxid(void)
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{
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bus_space_handle_t scu;
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int ncpu;
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uint32_t val;
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if (mp_ncpus != 0)
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return;
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if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
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panic("Could not map the SCU");
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val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONFIG_REG);
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ncpu = (val & SCU_CONFIG_REG_NCPU_MASK) + 1;
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bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
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mp_ncpus = ncpu;
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mp_maxid = ncpu - 1;
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}
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int
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platform_mp_probe(void)
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{
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if (mp_ncpus == 0)
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platform_mp_setmaxid();
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return (mp_ncpus > 1);
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}
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void
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platform_mp_start_ap(void)
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{
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bus_space_handle_t scu;
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bus_space_handle_t imem;
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bus_space_handle_t pmu;
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uint32_t val;
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int i;
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if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
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panic("Could not map the SCU");
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if (bus_space_map(fdtbus_bs_tag, IMEM_PHYSBASE,
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IMEM_SIZE, 0, &imem) != 0)
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panic("Could not map the IMEM");
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if (bus_space_map(fdtbus_bs_tag, PMU_PHYSBASE, PMU_SIZE, 0, &pmu) != 0)
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panic("Could not map the PMU");
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/*
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* Invalidate SCU cache tags. The 0x0000ffff constant invalidates all
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* ways on all cores 0-3. Per the ARM docs, it's harmless to write to
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* the bits for cores that are not present.
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*/
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bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
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/* Make sure all cores except the first are off */
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val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
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for (i = 1; i < mp_ncpus; i++)
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val |= 1 << i;
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bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
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/* Enable SCU power domain */
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val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
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val &= ~PMU_PWRDN_SCU;
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bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
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/* Enable SCU */
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val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
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bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
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val | SCU_CONTROL_ENABLE);
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/*
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* Cores will execute the code which resides at the start of
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* the on-chip bootram/sram after power-on. This sram region
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* should be reserved and the trampoline code that directs
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* the core to the real startup code in ram should be copied
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* into this sram region.
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*
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* First set boot function for the sram code.
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*/
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mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry);
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/* Copy trampoline to sram, that runs during startup of the core */
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bus_space_write_region_4(fdtbus_bs_tag, imem, 0,
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(uint32_t *)&rk30xx_boot2, 8);
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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/* Start all cores */
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val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
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for (i = 1; i < mp_ncpus; i++)
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val &= ~(1 << i);
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bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
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armv7_sev();
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bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
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bus_space_unmap(fdtbus_bs_tag, imem, IMEM_SIZE);
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bus_space_unmap(fdtbus_bs_tag, pmu, PMU_SIZE);
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}
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void
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platform_ipi_send(cpuset_t cpus, u_int ipi)
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{
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pic_ipi_send(cpus, ipi);
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}
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