Add support for the National Semiconductor DP83815 fast ethernet
controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
This commit is contained in:
Bill Paul
parent
18c8a61a47
commit
95674596b9
@ -526,6 +526,9 @@ NICs including the following:
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Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet NICs
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National Semiconductor DP83815 fast ethernet NICs including the following:
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NetGear FA312-TX
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Sundance Technologies ST201 PCI fast ethernet NICs including
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the following:
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D-Link DFE-550TX
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@ -71,6 +71,8 @@ POSIX.1b Shared Memory Objects are now supported. The implementation
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uses regular files, but automatically enables the MAP_NOSYNC flag
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when they are mmap(2)ed.
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Added support for PCI ethernet adapters based on the National Semiconductor
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DP83815 chipset, including the NetGear FA312-TX.
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1.2. SECURITY FIXES
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-------------------
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@ -289,6 +291,9 @@ NICs including the following:
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Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet NICs
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National Semiconductor DP83815 fast ethernet NICs including the following:
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NetGear FA312-TX
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Sundance Technologies ST201 PCI fast ethernet NICs including
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the following:
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D-Link DFE-550TX
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@ -75,6 +75,9 @@ POSIX.1b Shared Memory Objects are now supported. The implementation
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uses regular files, but automatically enables the MAP_NOSYNC flag
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when they are mmap(2)ed.
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Added support for PCI ethernet adapters based on the National Semiconductor
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DP83815 chipset, including the NetGear FA312-TX.
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1.2. SECURITY FIXES
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-------------------
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@ -308,6 +311,9 @@ NICs including the following:
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Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet NICs
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National Semiconductor DP83815 fast ethernet NICs including the following:
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NetGear FA312-TX
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Sundance Technologies ST201 PCI fast ethernet NICs including
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the following:
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D-Link DFE-550TX
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@ -36,7 +36,7 @@
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.Sh NAME
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.Nm sis
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.Nd
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Silicon Integrated Systems fast ethernet device driver
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SiS 900, SiS 7016 and NS DP83815 fast ethernet device driver
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.Sh SYNOPSIS
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.Cd "device miibus"
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.Cd "device sis"
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@ -45,7 +45,9 @@ The
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.Nm
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driver provides support for PCI ethernet adapters and embedded
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controllers based on the Silicon Integrated Systems SiS 900
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and SiS 7016 fast ethernet controller chips.
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and SiS 7016 fast ethernet controller chips, as well as support
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for adapters based on the National Semiconductor DP83815 (MacPhyter)
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PCI ethernet controller chip, including the Netgear FA312-TX.
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.Pp
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The SiS 900 is a 100Mbps ethernet MAC and MII-compliant transceiver
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in a single package.
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@ -57,6 +59,11 @@ to be attached to its MII interface.
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The SiS 900 and SiS 7016 both have a 128-bit multicast hash filter
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and a single perfect filter entry for the station address.
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.Pp
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The NS DP83815 is also a 100Mbps ethernet MAC with integrated PHY.
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The NatSemi chip and the SiS 900 share many of the same features and
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a fairly similar programming interface, hence both chips are supported
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by the same driver.
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.Pp
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The
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.Nm
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driver supports the following media types:
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@ -147,6 +154,10 @@ the card should be configured correctly.
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.%T SiS 900 and SiS 7016 datasheets
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.%O http://www.sis.com.tw
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.Re
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.Rs
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.%T NatSemi DP83815 datasheet
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.%O http://www.national.com
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.Re
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.Sh HISTORY
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The
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.Nm
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218
sys/pci/if_sis.c
218
sys/pci/if_sis.c
@ -106,6 +106,7 @@ static const char rcsid[] =
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static struct sis_type sis_devs[] = {
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{ SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
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{ SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
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{ NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" },
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{ 0, 0, NULL }
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};
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@ -132,6 +133,7 @@ static void sis_shutdown __P((device_t));
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static int sis_ifmedia_upd __P((struct ifnet *));
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static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
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static u_int16_t sis_reverse __P((u_int16_t));
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static void sis_delay __P((struct sis_softc *));
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static void sis_eeprom_idle __P((struct sis_softc *));
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static void sis_eeprom_putbyte __P((struct sis_softc *, int));
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@ -142,8 +144,9 @@ static int sis_miibus_readreg __P((device_t, int, int));
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static int sis_miibus_writereg __P((device_t, int, int, int));
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static void sis_miibus_statchg __P((device_t));
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static void sis_setmulti __P((struct sis_softc *));
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static u_int32_t sis_calchash __P((caddr_t));
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static void sis_setmulti_sis __P((struct sis_softc *));
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static void sis_setmulti_ns __P((struct sis_softc *));
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static u_int32_t sis_crc __P((struct sis_softc *, caddr_t));
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static void sis_reset __P((struct sis_softc *));
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static int sis_list_rx_init __P((struct sis_softc *));
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static int sis_list_tx_init __P((struct sis_softc *));
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@ -200,6 +203,21 @@ DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
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#define SIO_CLR(x) \
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CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
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/*
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* Routine to reverse the bits in a word. Stolen almost
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* verbatim from /usr/games/fortune.
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*/
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static u_int16_t sis_reverse(n)
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u_int16_t n;
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{
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n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
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n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
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n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
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n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
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return(n);
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}
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static void sis_delay(sc)
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struct sis_softc *sc;
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{
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@ -283,9 +301,9 @@ static void sis_eeprom_getword(sc, addr, dest)
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/* Enter EEPROM access mode. */
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sis_delay(sc);
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SIO_SET(SIS_EECTL_CSEL);
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SIO_CLR(SIS_EECTL_CLK);
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sis_delay(sc);
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SIO_SET(SIS_EECTL_CLK);
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SIO_SET(SIS_EECTL_CSEL);
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sis_delay(sc);
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/*
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@ -344,10 +362,29 @@ static int sis_miibus_readreg(dev, phy, reg)
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int phy, reg;
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{
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struct sis_softc *sc;
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int i, val;
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int i, val = 0;
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sc = device_get_softc(dev);
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if (sc->sis_type == SIS_TYPE_83815) {
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if (phy != 0)
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return(0);
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/*
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* The NatSemi chip can take a while after
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* a reset to come ready, during which the BMSR
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* returns a value of 0. This is *never* supposed
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* to happen: some of the BMSR bits are meant to
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* be hardwired in the on position, and this can
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* confuse the miibus code a bit during the probe
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* and attach phase. So we make an effort to check
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* for this condition and wait for it to clear.
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*/
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if (!CSR_READ_4(sc, NS_BMSR))
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DELAY(1000);
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val = CSR_READ_4(sc, NS_BMCR + (reg * 4));
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return(val);
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}
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if (sc->sis_type == SIS_TYPE_900 && phy != 0)
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return(0);
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@ -381,6 +418,16 @@ static int sis_miibus_writereg(dev, phy, reg, data)
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sc = device_get_softc(dev);
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if (sc->sis_type == SIS_TYPE_83815) {
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if (phy != 0)
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return(0);
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CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
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return(0);
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}
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if (sc->sis_type == SIS_TYPE_900 && phy != 0)
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return(0);
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if (sc->sis_type == SIS_TYPE_900 && phy != 0)
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return(0);
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@ -421,7 +468,8 @@ static void sis_miibus_statchg(dev)
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return;
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}
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static u_int32_t sis_calchash(addr)
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static u_int32_t sis_crc(sc, addr)
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struct sis_softc *sc;
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caddr_t addr;
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{
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u_int32_t crc, carry;
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@ -442,11 +490,68 @@ static u_int32_t sis_calchash(addr)
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}
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}
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/* return the filter bit position */
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/*
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* return the filter bit position
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*
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* The NatSemi chip has a 512-bit filter, which is
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* different than the SiS, so we special-case it.
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*/
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if (sc->sis_type == SIS_TYPE_83815)
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return((crc >> 23) & 0x1FF);
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return((crc >> 25) & 0x0000007F);
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}
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static void sis_setmulti(sc)
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static void sis_setmulti_ns(sc)
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struct sis_softc *sc;
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{
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struct ifnet *ifp;
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struct ifmultiaddr *ifma;
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u_int32_t h = 0, i, filtsave;
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int bit, index;
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ifp = &sc->arpcom.ac_if;
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if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
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SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
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SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
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return;
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}
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/*
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* We have to explicitly enable the multicast hash table
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* on the NatSemi chip if we want to use it, which we do.
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*/
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SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
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SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
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filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
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/* first, zot all the existing hash bits */
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for (i = 0; i < 32; i++) {
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
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CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
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}
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for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
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ifma = ifma->ifma_link.le_next) {
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if (ifma->ifma_addr->sa_family != AF_LINK)
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continue;
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h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
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index = h >> 3;
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bit = h & 0x1F;
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
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if (bit > 0xF)
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bit -= 0x10;
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SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
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}
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
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return;
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}
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static void sis_setmulti_sis(sc)
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struct sis_softc *sc;
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{
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struct ifnet *ifp;
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@ -475,7 +580,7 @@ static void sis_setmulti(sc)
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ifma = ifma->ifma_link.le_next) {
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if (ifma->ifma_addr->sa_family != AF_LINK)
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continue;
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h = sis_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
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h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16);
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SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF)));
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}
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@ -552,6 +657,8 @@ static int sis_attach(dev)
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sc->sis_type = SIS_TYPE_900;
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if (pci_get_device(dev) == SIS_DEVICEID_7016)
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sc->sis_type = SIS_TYPE_7016;
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if (pci_get_vendor(dev) == NS_VENDORID)
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sc->sis_type = SIS_TYPE_83815;
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/*
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* Handle power management nonsense.
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@ -645,7 +752,47 @@ static int sis_attach(dev)
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/*
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* Get station address from the EEPROM.
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*/
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sis_read_eeprom(sc, (caddr_t)&eaddr, SIS_EE_NODEADDR, 3, 0);
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switch (pci_get_vendor(dev)) {
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case NS_VENDORID:
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/*
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* Reading the MAC address out of the EEPROM on
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* the NatSemi chip takes a bit more work than
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* you'd expect. The address spans 4 16-bit words,
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* with the first word containing only a single bit.
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* You have to shift everything over one bit to
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* get it aligned properly. Also, the bits are
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* stored backwards (the LSB is really the MSB,
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* and so on) so you have to reverse them in order
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* to get the MAC address into the form we want.
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* Why? Who the hell knows.
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*/
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{
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u_int16_t tmp[4];
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sis_read_eeprom(sc, (caddr_t)&tmp,
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NS_EE_NODEADDR, 4, 0);
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/* Shift everything over one bit. */
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tmp[3] = tmp[3] >> 1;
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tmp[3] |= tmp[2] >> 15;
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tmp[2] = tmp[2] >> 1;
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tmp[2] |= tmp[1] >> 15;
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tmp[1] = tmp[1] >> 1;
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tmp[1] |= tmp[0] >> 15;
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/* Now reverse all the bits. */
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tmp[3] = sis_reverse(tmp[3]);
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tmp[2] = sis_reverse(tmp[2]);
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tmp[1] = sis_reverse(tmp[1]);
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bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
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}
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break;
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case SIS_VENDORID:
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default:
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sis_read_eeprom(sc, (caddr_t)&eaddr, SIS_EE_NODEADDR, 3, 0);
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break;
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}
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/*
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* A SiS chip was detected. Inform the world.
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@ -1183,15 +1330,27 @@ static void sis_init(xsc)
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mii = device_get_softc(sc->sis_miibus);
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/* Set MAC address */
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
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CSR_WRITE_4(sc, SIS_RXFILT_DATA,
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((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
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CSR_WRITE_4(sc, SIS_RXFILT_DATA,
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((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
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CSR_WRITE_4(sc, SIS_RXFILT_DATA,
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((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
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if (sc->sis_type == SIS_TYPE_83815) {
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
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CSR_WRITE_4(sc, SIS_RXFILT_DATA,
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((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
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CSR_WRITE_4(sc, SIS_RXFILT_DATA,
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((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
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CSR_WRITE_4(sc, SIS_RXFILT_DATA,
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((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
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} else {
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
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CSR_WRITE_4(sc, SIS_RXFILT_DATA,
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((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
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CSR_WRITE_4(sc, SIS_RXFILT_DATA,
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((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
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CSR_WRITE_4(sc, SIS_RXFILT_DATA,
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((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
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}
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/* Init circular RX list. */
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if (sis_list_rx_init(sc) == ENOBUFS) {
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@ -1207,6 +1366,17 @@ static void sis_init(xsc)
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*/
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sis_list_tx_init(sc);
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/*
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* For the NatSemi chip, we have to explicitly enable the
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* reception of ARP frames, as well as turn on the 'perfect
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* match' filter where we store the station address, otherwise
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* we won't receive unicasts meant for this host.
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*/
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if (sc->sis_type == SIS_TYPE_83815) {
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SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
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SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
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}
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/* If we want promiscuous mode, set the allframes bit. */
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if (ifp->if_flags & IFF_PROMISC) {
|
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SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
|
||||
@ -1226,7 +1396,10 @@ static void sis_init(xsc)
|
||||
/*
|
||||
* Load the multicast filter.
|
||||
*/
|
||||
sis_setmulti(sc);
|
||||
if (sc->sis_type == SIS_TYPE_83815)
|
||||
sis_setmulti_ns(sc);
|
||||
else
|
||||
sis_setmulti_sis(sc);
|
||||
|
||||
/* Turn the receive filter on */
|
||||
SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
|
||||
@ -1331,7 +1504,10 @@ static int sis_ioctl(ifp, command, data)
|
||||
break;
|
||||
case SIOCADDMULTI:
|
||||
case SIOCDELMULTI:
|
||||
sis_setmulti(sc);
|
||||
if (sc->sis_type == SIS_TYPE_83815)
|
||||
sis_setmulti_ns(sc);
|
||||
else
|
||||
sis_setmulti_sis(sc);
|
||||
error = 0;
|
||||
break;
|
||||
case SIOCGIFMEDIA:
|
||||
|
||||
@ -74,6 +74,16 @@
|
||||
#define SIS_TIMEUNIT 0xA4
|
||||
#define SIS_GPIO 0xB8
|
||||
|
||||
/* NS DP83815 registers */
|
||||
#define NS_BMCR 0x80
|
||||
#define NS_BMSR 0x84
|
||||
#define NS_PHYIDR1 0x88
|
||||
#define NS_PHYIDR2 0x8C
|
||||
#define NS_ANAR 0x90
|
||||
#define NS_ANLPAR 0x94
|
||||
#define NS_ANER 0x98
|
||||
#define NS_ANNPTR 0x9C
|
||||
|
||||
#define SIS_CSR_TX_ENABLE 0x00000001
|
||||
#define SIS_CSR_TX_DISABLE 0x00000002
|
||||
#define SIS_CSR_RX_ENABLE 0x00000004
|
||||
@ -100,6 +110,7 @@
|
||||
#define SIS_EECMD_ERASE 0x1c0
|
||||
|
||||
#define SIS_EE_NODEADDR 0x8
|
||||
#define NS_EE_NODEADDR 0x6
|
||||
|
||||
#define SIS_PCICTL_SRAMADDR 0x0000001F
|
||||
#define SIS_PCICTL_RAMTSTENB 0x00000020
|
||||
@ -220,6 +231,9 @@
|
||||
(SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES)
|
||||
|
||||
#define SIS_RXFILTCTL_ADDR 0x000F0000
|
||||
#define NS_RXFILTCTL_MCHASH 0x00200000
|
||||
#define NS_RXFILTCTL_ARP 0x00400000
|
||||
#define NS_RXFILTCTL_PERFECT 0x08000000
|
||||
#define SIS_RXFILTCTL_ALLPHYS 0x10000000
|
||||
#define SIS_RXFILTCTL_ALLMULTI 0x20000000
|
||||
#define SIS_RXFILTCTL_BROAD 0x40000000
|
||||
@ -237,6 +251,13 @@
|
||||
#define SIS_FILTADDR_MAR6 0x000A0000
|
||||
#define SIS_FILTADDR_MAR7 0x000B0000
|
||||
|
||||
#define NS_FILTADDR_PAR0 0x00000000
|
||||
#define NS_FILTADDR_PAR1 0x00000002
|
||||
#define NS_FILTADDR_PAR2 0x00000004
|
||||
|
||||
#define NS_FILTADDR_FMEM_LO 0x00000200
|
||||
#define NS_FILTADDR_FMEM_HI 0x000003FE
|
||||
|
||||
/*
|
||||
* DMA descriptor structures. The first part of the descriptor
|
||||
* is the hardware descriptor format, which is just three longwords.
|
||||
@ -322,6 +343,16 @@ struct sis_ring_data {
|
||||
#define SIS_DEVICEID_900 0x0900
|
||||
#define SIS_DEVICEID_7016 0x7016
|
||||
|
||||
/*
|
||||
* NatSemi vendor ID
|
||||
*/
|
||||
#define NS_VENDORID 0x100B
|
||||
|
||||
/*
|
||||
* DP83815 device ID
|
||||
*/
|
||||
#define NS_DEVICEID_DP83815 0x0020
|
||||
|
||||
struct sis_type {
|
||||
u_int16_t sis_vid;
|
||||
u_int16_t sis_did;
|
||||
@ -330,6 +361,7 @@ struct sis_type {
|
||||
|
||||
#define SIS_TYPE_900 1
|
||||
#define SIS_TYPE_7016 2
|
||||
#define SIS_TYPE_83815 3
|
||||
|
||||
struct sis_softc {
|
||||
struct arpcom arpcom; /* interface info */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user