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Do not do a cache invalidate on a PREREAD sync that is also a PREWRITE sync.

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The PREWRITE handling does a writeback of any dirty cachelines, so there's
no danger of an eviction during the DMA corrupting the buffer.  There will
be an invalidate done during POSTREAD, so doing it before the read too is
wasted time.
This commit is contained in:
ian 2014-11-16 20:55:51 +00:00
parent c15cabeb69
commit 958e1dabc1
1 changed files with 1 additions and 1 deletions
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2
sys/arm/arm/busdma_machdep-v6.c
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@ -1345,7 +1345,7 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
dmat->bounce_zone->total_bounced++;
}
if (op & BUS_DMASYNC_PREREAD) {
if ((op & BUS_DMASYNC_PREREAD) && !(op & BUS_DMASYNC_PREWRITE)) {
bpage = STAILQ_FIRST(&map->bpages);
while (bpage != NULL) {
cpu_dcache_inv_range((vm_offset_t)bpage->vaddr,