Fix spelling.
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531e5eb0be
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9595ccdac2
@ -828,7 +828,7 @@ void fw_init(struct firewire_comm *fc)
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((fwb)->end < (addr))?1:0)
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/*
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* To lookup binded process from IEEE1394 address.
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* To lookup bound process from IEEE1394 address.
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*/
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struct fw_bind *
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fw_bindlookup(struct firewire_comm *fc, u_int16_t dest_hi, u_int32_t dest_lo)
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@ -898,7 +898,7 @@ fw_bindremove(struct firewire_comm *fc, struct fw_bind *fwb)
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goto found;
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}
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printf("%s: no such bind\n", __func__);
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printf("%s: no such binding\n", __func__);
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splx(s);
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return (1);
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found:
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@ -1532,7 +1532,7 @@ fw_bus_explore_callback(struct fw_xfer *xfer)
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if(sfp->mode.rreqq.dest_lo == (0xf0000000 | CSRROMOFF)){
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rfp->mode.rresq.data = ntohl(rfp->mode.rresq.data);
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chdr = (struct csrhdr *)(&rfp->mode.rresq.data);
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/* If CSR is minimal confinguration, more investgation is not needed. */
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/* If CSR is minimal confinguration, more investigation is not needed. */
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if(chdr->info_len == 1){
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if (firewire_debug)
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printf("node%d: minimal config\n",
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@ -1702,7 +1702,7 @@ fw_attach_dev(struct firewire_comm *fc)
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}
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/*
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* To allocate uniq transaction label.
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* To allocate unique transaction label.
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*/
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static int
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fw_get_tlabel(struct firewire_comm *fc, struct fw_xfer *xfer)
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@ -1797,7 +1797,7 @@ fw_rcv_copy(struct fw_rcv_buf *rb)
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}
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/*
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* Generic packet receving process.
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* Generic packet receiving process.
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*/
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void
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fw_rcv(struct fw_rcv_buf *rb)
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@ -491,10 +491,10 @@ fwohci_reset(struct fwohci_softc *sc, device_t dev)
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u_int32_t reg, reg2;
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struct fwohcidb_tr *db_tr;
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/* Disable interrupt */
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/* Disable interrupts */
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OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
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/* Now stopping all DMA channel */
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/* Now stopping all DMA channels */
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OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
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OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
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OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
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@ -580,7 +580,7 @@ fwohci_reset(struct fwohci_softc *sc, device_t dev)
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}
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/* Enable interrupt */
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/* Enable interrupts */
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OWRITE(sc, FWOHCI_INTMASK,
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OHCI_INT_ERR | OHCI_INT_PHY_SID
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| OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
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@ -611,7 +611,7 @@ fwohci_init(struct fwohci_softc *sc, device_t dev)
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return (ENXIO);
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}
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/* Available Isochrounous DMA channel probe */
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/* Available Isochronous DMA channel probe */
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OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
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OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
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reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
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@ -621,7 +621,7 @@ fwohci_init(struct fwohci_softc *sc, device_t dev)
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if ((reg & (1 << i)) == 0)
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break;
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sc->fc.nisodma = i;
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device_printf(dev, "No. of Isochronous channel is %d.\n", i);
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device_printf(dev, "No. of Isochronous channels is %d.\n", i);
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if (i == 0)
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return (ENXIO);
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@ -692,7 +692,7 @@ fwohci_init(struct fwohci_softc *sc, device_t dev)
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#endif
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/* SID recieve buffer must allign 2^11 */
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/* SID recieve buffer must align 2^11 */
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#define OHCI_SIDSIZE (1 << 11)
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sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
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&sc->sid_dma, BUS_DMA_WAITOK);
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@ -1739,7 +1739,7 @@ fwohci_resume(struct fwohci_softc *sc, device_t dev)
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struct fw_bulkxfer *chunk;
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fwohci_reset(sc, dev);
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/* XXX resume isochronus receive automatically. (how about TX?) */
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/* XXX resume isochronous receive automatically. (how about TX?) */
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for(i = 0; i < sc->fc.nisodma; i ++) {
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ir = &sc->ir[i].xferq;
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if((ir->flag & FWXFERQ_RUNNING) != 0) {
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@ -94,7 +94,7 @@
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#define CSRKEY_DID 0x20 /* Directory_ID */
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#define CSRKEY_REV 0x21 /* Revision */
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#define CSRKEY_FIRM_VER 0x3c /* Firemware version */
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#define CSRKEY_FIRM_VER 0x3c /* Firmware version */
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#define CSRKEY_UNIT_CH 0x3a /* Unit characteristics */
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#define CSRKEY_COM_SPEC 0x38 /* Command set revision */
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#define CSRKEY_COM_SET 0x39 /* Command set */
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