diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile index 22e115b3c4c3..3d68767c5555 100644 --- a/share/man/man4/Makefile +++ b/share/man/man4/Makefile @@ -16,6 +16,7 @@ MAN= aac.4 \ atkbdc.4 \ aue.4 \ awi.4 \ + bge.4 \ bktr.4 \ blackhole.4 \ bpf.4 \ diff --git a/share/man/man4/bge.4 b/share/man/man4/bge.4 new file mode 100644 index 000000000000..72ac3ab893ea --- /dev/null +++ b/share/man/man4/bge.4 @@ -0,0 +1,204 @@ +.\" Copyright (c) 2001 Wind River Systems +.\" Copyright (c) 1997, 1998, 1999, 2000, 2001 +.\" Bill Paul . All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" 3. All advertising materials mentioning features or use of this software +.\" must display the following acknowledgement: +.\" This product includes software developed by Bill Paul. +.\" 4. Neither the name of the author nor the names of any co-contributors +.\" may be used to endorse or promote products derived from this software +.\" without specific prior written permission. +.\" +.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD +.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +.\" THE POSSIBILITY OF SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd September 27, 2001 +.Dt BGE 4 +.Os +.Sh NAME +.Nm bge +.Nd "Broadcom BCM570x PCI gigabit ethernet adapter driver" +.Sh SYNOPSIS +.Cd "device miibus" +.Cd "device bge" +.Sh DESCRIPTION +The +.Nm +driver provides support for various NICs based on the Broadcom BCM570x +family of gigabit ethernet controller chips, including the +following: +.Pp +.Bl -bullet -compact +.It +3Com 3c996-T (10/100/1000baseTX) +.It +Dell PowerEdge 2550 integrated BCM5700 NIC (10/100/1000baseTX) +.It +SysKonnect SK-9D21 (10/100/1000baseTX) +.It +SysKonnect SK-9D41 (1000baseSX) +.El +.Pp +All of these NICs are capable of 10, 100 and 1000Mbps speeds over CAT5 +copper cable, except for the SysKonnect SK-9D41 which supports only +1000Mbps over multimode fiber. +The BCM570x builds upon the technology of the Alteon Tigon II. It has +two R4000 CPU cores and is PCI v2.2 and PCI-X v1.0 compliant. It +supports IP, TCP +and UDP checksum checksum offload for both receive and transmit, +multiple RX and TX DMA rings for QoS applications, rules-based +receive filtering, and VLAN tag stripping/insertion as well as +a 256-bit multicast hash filter. Additional features may be +provided via value-add firmware updates. +The BCM570x supports TBI (ten bit interface) and GMII +transceivers, which means it can be used with either copper of 1000baseX +fiber applications. Note however the device only supports a single +speed in TBI mode. +.Pp +Most cards also use the Broadcom BCM5401 or BCM5411 10/100/1000 +copper gigabit tranceivers, +which support autonegotiation of 10, 100 and 1000mbps modes in +full or half duplex. +.Pp +The BCM5700 also supports jumbo frames, which can be configured +via the interface MTU setting. +Selecting an MTU larger than 1500 bytes with the +.Xr ifconfig 8 +utility configures the adapter to receive and transmit jumbo frames. +Using jumbo frames can greatly improve performance for certain tasks, +such as file transfers and data streaming. +.Pp +The +.Nm +driver supports the following media types: +.Bl -tag -width 10baseTXUTP +.It Cm autoselect +Enable autoselection of the media type and options. +The user can manually override +the autoselected mode by adding media options to +.Xr rc.conf 5 . +.It Cm 10baseT/UTP +Set 10Mbps operation. +The +.Xr ifconfig 8 +.Ic mediaopt +option can also be used to select either +.Cm full-duplex +or +.Cm half-duplex +modes. +.It Cm 100baseTX +Set 100Mbps (fast ethernet) operation. +The +.Xr ifconfig 8 +.Ic mediaopt +option can also be used to select either +.Cm full-duplex +or +.Cm half-duplex +modes. +.It Cm 1000baseTX +Set 1000baseTX operation over twisted pair. +.Cm full-duplex +and +.Cm half-duplex +modes are supported. +.It Cm 1000baseSX +Set 1000Mbps (gigabit ethernet) operation. +Both +.Cm full-duplex +and +.Cm half-duplex +modes are supported. +.El +.Pp +The +.Nm +driver supports the following media options: +.Bl -tag -width full-duplex +.It Cm full-duplex +Force full duplex operation. +.It Cm half-duplex +Force half duplex operation. +.El +.Pp +The +.Nm +driver also supports one special link option for 1000baseTX cards: +.Bl -tag -width link0 +.It Cm link0 +With 1000baseTX cards, establishing a link between two ports requires +that one port be configured as a master and the other a slave. +With autonegotiation, +the master/slave settings will be chosen automatically. +However when manually selecting the link state, it is necessary to +force one side of the link to be a master and the other a slave. +The +.Nm +driver configures the ports as slaves by default. +Setting the +.Cm link0 +flag with +.Xr ifconfig 8 +will set a port as a master instead. +.El +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +.Sh DIAGNOSTICS +.Bl -diag +.It "bge%d: couldn't map memory" +A fatal initialization error has occurred. +.It "bge%d: couldn't map ports" +A fatal initialization error has occurred. +.It "bge%d: couldn't map interrupt" +A fatal initialization error has occurred. +.It "bge%d: no memory for softc struct!" +The driver failed to allocate memory for per-device instance information +during initialization. +.It "bge%d: failed to enable memory mapping!" +The driver failed to initialize PCI shared memory mapping. +This might +happen if the card is not in a bus-master slot. +.It "bge%d: no memory for jumbo buffers!" +The driver failed to allocate memory for jumbo frames during +initialization. +.It "bge%d: watchdog timeout" +The device has stopped responding to the network, or there is a problem with +the network connection (cable). +.El +.Sh SEE ALSO +.Xr arp 4 , +.Xr netintro 4 , +.Xr ng_ether 4 , +.Xr vlan 4 , +.Xr ifconfig 8 +.Sh HISTORY +The +.Nm +device driver first appeared in +.Fx 5.0 . +.Sh AUTHORS +The +.Nm +driver was written by +.An Bill Paul Aq wpaul@windriver.com . diff --git a/sys/conf/NOTES b/sys/conf/NOTES index 60e29be6795a..ae3e901214d2 100644 --- a/sys/conf/NOTES +++ b/sys/conf/NOTES @@ -1665,6 +1665,10 @@ device miibus # (requires sppp) # awi: Support for IEEE 802.11 PC Card devices using the AMD Am79C930 and # Harris (Intersil) Chipset with PCnetMobile firmware by AMD. +# bge: Support for gigabit ethernet adapters based on the Broadcom +# BCM570x familiy of controllers, including the 3Com 3c996-T, +# the SysKonnect SK-9D21 and SK-9D41, and the embedded gigE NICs +# on Dell PowerEdge 2550 servers. # cnw: Xircom CNW/Netware Airsurfer PC Card adapter # cs: IBM Etherjet and other Crystal Semi CS89x0-based adapters # cx: Cronyx/Sigma multiport sync/async (with Cisco or PPP framing) @@ -1872,9 +1876,11 @@ device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'') # PCI Ethernet NICs. device de # DEC/Intel DC21x4x (``Tulip'') +device txp # 3Com 3cR990 (``Typhoon'') device vx # 3Com 3c590, 3c595 (``Vortex'') # PCI Gigabit & FDDI NICs. +device bge device lge device nge device sk diff --git a/sys/conf/files b/sys/conf/files index 7e3a947d1437..9dbd1fb723c2 100644 --- a/sys/conf/files +++ b/sys/conf/files @@ -270,6 +270,7 @@ dev/awi/awi_wep.c optional awi dev/awi/awi_wicfg.c optional awi dev/awi/if_awi_pccard.c optional awi card dev/awi/if_awi_pccard.c optional awi pccard +dev/bge/if_bge.c optional bge dev/bktr/bktr_audio.c optional bktr pci dev/bktr/bktr_card.c optional bktr pci dev/bktr/bktr_core.c count bktr pci diff --git a/sys/dev/bge/if_bge.c b/sys/dev/bge/if_bge.c new file mode 100644 index 000000000000..05c972cf86c5 --- /dev/null +++ b/sys/dev/bge/if_bge.c @@ -0,0 +1,2696 @@ +/* + * Copyright (c) 2001 Wind River Systems + * Copyright (c) 1997, 1998, 1999, 2001 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. + * + * Written by Bill Paul + * Senior Engineer, Wind River Systems + */ + +/* + * The Broadcom BCM5700 is based on technology originally developed by + * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet + * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has + * two on-board MIPS R4000 CPUs and can have as much as 16MB of external + * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo + * frames, highly configurable RX filtering, and 16 RX and TX queues + * (which, along with RX filter rules, can be used for QOS applications). + * Other features, such as TCP segmentation, may be available as part + * of value-added firmware updates. Unlike the Tigon I and Tigon II, + * firmware images can be stored in hardware and need not be compiled + * into the driver. + * + * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will + * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. + * + * The BCM5701 is a single-chip solution incorporating both the BCM5700 + * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700 + * does not support external SSRAM. + * + * Broadcom also produces a variation of the BCM5700 under the "Altima" + * brand name, which is functionally similar but lacks PCI-X support. + * + * Without external SSRAM, you can only have at most 4 TX rings, + * and the use of the mini RX ring is disabled. This seems to imply + * that these features are simply not available on the BCM5701. As a + * result, this driver does not implement any support for the mini RX + * ring. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#include /* for vtophys */ +#include /* for vtophys */ +#include /* for DELAY */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) + +MODULE_DEPEND(bge, miibus, 1, 1, 1); + +/* "controller miibus0" required. See GENERIC if you get errors here. */ +#include "miibus_if.h" + +#if !defined(lint) +static const char rcsid[] = + "$FreeBSD$"; +#endif + +/* + * Various supported device vendors/types and their names. Note: the + * spec seems to indicate that the hardware still has Alteon's vendor + * ID burned into it, though it will always be overriden by the vendor + * ID in the EEPROM. Just to be safe, we cover all possibilities. + */ + +static struct bge_type bge_devs[] = { + { ALT_VENDORID, ALT_DEVICEID_BCM5700, + "Broadcom BCM5700 Gigabit Ethernet" }, + { ALT_VENDORID, ALT_DEVICEID_BCM5701, + "Broadcom BCM5701 Gigabit Ethernet" }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, + "Broadcom BCM5700 Gigabit Ethernet" }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, + "Broadcom BCM5701 Gigabit Ethernet" }, + { SK_VENDORID, SK_DEVICEID_ALTIMA, + "SysKonnect Gigabit Ethernet" }, + { 0, 0, NULL } +}; + +static int bge_probe __P((device_t)); +static int bge_attach __P((device_t)); +static int bge_detach __P((device_t)); +static void bge_release_resources + __P((struct bge_softc *)); +static void bge_txeof __P((struct bge_softc *)); +static void bge_rxeof __P((struct bge_softc *)); + +static void bge_tick __P((void *)); +static void bge_stats_update __P((struct bge_softc *)); +static int bge_encap __P((struct bge_softc *, struct mbuf *, + u_int32_t *)); + +static void bge_intr __P((void *)); +static void bge_start __P((struct ifnet *)); +static int bge_ioctl __P((struct ifnet *, u_long, caddr_t)); +static void bge_init __P((void *)); +static void bge_stop __P((struct bge_softc *)); +static void bge_watchdog __P((struct ifnet *)); +static void bge_shutdown __P((device_t)); +static int bge_ifmedia_upd __P((struct ifnet *)); +static void bge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); + +static u_int8_t bge_eeprom_getbyte __P((struct bge_softc *, + int, u_int8_t *)); +static int bge_read_eeprom __P((struct bge_softc *, caddr_t, int, int)); + +static u_int32_t bge_crc __P((caddr_t)); +static void bge_setmulti __P((struct bge_softc *)); + +static void bge_handle_events __P((struct bge_softc *)); +static int bge_alloc_jumbo_mem __P((struct bge_softc *)); +static void bge_free_jumbo_mem __P((struct bge_softc *)); +static void *bge_jalloc __P((struct bge_softc *)); +static void bge_jfree __P((caddr_t, void *)); +static int bge_newbuf_std __P((struct bge_softc *, int, struct mbuf *)); +static int bge_newbuf_jumbo __P((struct bge_softc *, int, struct mbuf *)); +static int bge_init_rx_ring_std __P((struct bge_softc *)); +static void bge_free_rx_ring_std __P((struct bge_softc *)); +static int bge_init_rx_ring_jumbo __P((struct bge_softc *)); +static void bge_free_rx_ring_jumbo __P((struct bge_softc *)); +static void bge_free_tx_ring __P((struct bge_softc *)); +static int bge_init_tx_ring __P((struct bge_softc *)); + +static int bge_chipinit __P((struct bge_softc *)); +static int bge_blockinit __P((struct bge_softc *)); + +static u_int8_t bge_vpd_readbyte __P((struct bge_softc *, int)); +static void bge_vpd_read_res __P((struct bge_softc *, + struct vpd_res *, int)); +static void bge_vpd_read __P((struct bge_softc *)); + +static u_int32_t bge_readmem_ind + __P((struct bge_softc *, int)); +static void bge_writemem_ind __P((struct bge_softc *, int, int)); +#ifdef notdef +static u_int32_t bge_readreg_ind + __P((struct bge_softc *, int)); +#endif +static void bge_writereg_ind __P((struct bge_softc *, int, int)); + +static int bge_miibus_readreg __P((device_t, int, int)); +static int bge_miibus_writereg __P((device_t, int, int, int)); +static void bge_miibus_statchg __P((device_t)); + +static void bge_reset __P((struct bge_softc *)); +static void bge_phy_hack __P((struct bge_softc *)); + +static device_method_t bge_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bge_probe), + DEVMETHOD(device_attach, bge_attach), + DEVMETHOD(device_detach, bge_detach), + DEVMETHOD(device_shutdown, bge_shutdown), + + /* bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_driver_added, bus_generic_driver_added), + + /* MII interface */ + DEVMETHOD(miibus_readreg, bge_miibus_readreg), + DEVMETHOD(miibus_writereg, bge_miibus_writereg), + DEVMETHOD(miibus_statchg, bge_miibus_statchg), + + { 0, 0 } +}; + +static driver_t bge_driver = { + "bge", + bge_methods, + sizeof(struct bge_softc) +}; + +static devclass_t bge_devclass; + +DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); +DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); + +static u_int32_t +bge_readmem_ind(sc, off) + struct bge_softc *sc; + int off; +{ + device_t dev; + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); + return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); +} + +static void +bge_writemem_ind(sc, off, val) + struct bge_softc *sc; + int off, val; +{ + device_t dev; + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); + pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); + + return; +} + +#ifdef notdef +static u_int32_t +bge_readreg_ind(sc, off) + struct bge_softc *sc; + int off; +{ + device_t dev; + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); + return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); +} +#endif + +static void +bge_writereg_ind(sc, off, val) + struct bge_softc *sc; + int off, val; +{ + device_t dev; + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); + pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); + + return; +} + +static u_int8_t +bge_vpd_readbyte(sc, addr) + struct bge_softc *sc; + int addr; +{ + int i; + device_t dev; + u_int32_t val; + + dev = sc->bge_dev; + pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); + for (i = 0; i < BGE_TIMEOUT * 10; i++) { + DELAY(10); + if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) + break; + } + + if (i == BGE_TIMEOUT) { + printf("bge%d: VPD read timed out\n", sc->bge_unit); + return(0); + } + + val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); + + return((val >> ((addr % 4) * 8)) & 0xFF); +} + +static void +bge_vpd_read_res(sc, res, addr) + struct bge_softc *sc; + struct vpd_res *res; + int addr; +{ + int i; + u_int8_t *ptr; + + ptr = (u_int8_t *)res; + for (i = 0; i < sizeof(struct vpd_res); i++) + ptr[i] = bge_vpd_readbyte(sc, i + addr); + + return; +} + +static void +bge_vpd_read(sc) + struct bge_softc *sc; +{ + int pos = 0, i; + struct vpd_res res; + + if (sc->bge_vpd_prodname != NULL) + free(sc->bge_vpd_prodname, M_DEVBUF); + if (sc->bge_vpd_readonly != NULL) + free(sc->bge_vpd_readonly, M_DEVBUF); + sc->bge_vpd_prodname = NULL; + sc->bge_vpd_readonly = NULL; + + bge_vpd_read_res(sc, &res, pos); + + if (res.vr_id != VPD_RES_ID) { + printf("bge%d: bad VPD resource id: expected %x got %x\n", + sc->bge_unit, VPD_RES_ID, res.vr_id); + return; + } + + pos += sizeof(res); + sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); + for (i = 0; i < res.vr_len; i++) + sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); + sc->bge_vpd_prodname[i] = '\0'; + pos += i; + + bge_vpd_read_res(sc, &res, pos); + + if (res.vr_id != VPD_RES_READ) { + printf("bge%d: bad VPD resource id: expected %x got %x\n", + sc->bge_unit, VPD_RES_READ, res.vr_id); + return; + } + + pos += sizeof(res); + sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); + for (i = 0; i < res.vr_len + 1; i++) + sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); + + return; +} + +/* + * Read a byte of data stored in the EEPROM at address 'addr.' The + * BCM570x supports both the traditional bitbang interface and an + * auto access interface for reading the EEPROM. We use the auto + * access method. + */ +static u_int8_t +bge_eeprom_getbyte(sc, addr, dest) + struct bge_softc *sc; + int addr; + u_int8_t *dest; +{ + int i; + u_int32_t byte = 0; + + /* + * Enable use of auto EEPROM access so we can avoid + * having to use the bitbang method. + */ + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); + + /* Reset the EEPROM, load the clock period. */ + CSR_WRITE_4(sc, BGE_EE_ADDR, + BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); + DELAY(20); + + /* Issue the read EEPROM command. */ + CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); + + /* Wait for completion */ + for(i = 0; i < BGE_TIMEOUT * 10; i++) { + DELAY(10); + if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) + break; + } + + if (i == BGE_TIMEOUT) { + printf("bge%d: eeprom read timed out\n", sc->bge_unit); + return(0); + } + + /* Get result. */ + byte = CSR_READ_4(sc, BGE_EE_DATA); + + *dest = (byte >> ((addr % 4) * 8)) & 0xFF; + + return(0); +} + +/* + * Read a sequence of bytes from the EEPROM. + */ +static int +bge_read_eeprom(sc, dest, off, cnt) + struct bge_softc *sc; + caddr_t dest; + int off; + int cnt; +{ + int err = 0, i; + u_int8_t byte = 0; + + for (i = 0; i < cnt; i++) { + err = bge_eeprom_getbyte(sc, off + i, &byte); + if (err) + break; + *(dest + i) = byte; + } + + return(err ? 1 : 0); +} + +static int +bge_miibus_readreg(dev, phy, reg) + device_t dev; + int phy, reg; +{ + struct bge_softc *sc; + struct ifnet *ifp; + u_int32_t val; + int i; + + sc = device_get_softc(dev); + ifp = &sc->arpcom.ac_if; + + if (ifp->if_flags & IFF_RUNNING) + BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); + + CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| + BGE_MIPHY(phy)|BGE_MIREG(reg)); + + for (i = 0; i < BGE_TIMEOUT; i++) { + val = CSR_READ_4(sc, BGE_MI_COMM); + if (!(val & BGE_MICOMM_BUSY)) + break; + } + + if (i == BGE_TIMEOUT) { + printf("bge%d: PHY read timed out\n", sc->bge_unit); + return(0); + } + + val = CSR_READ_4(sc, BGE_MI_COMM); + + if (ifp->if_flags & IFF_RUNNING) + BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); + + if (val & BGE_MICOMM_READFAIL) + return(0); + + return(val & 0xFFFF); +} + +static int +bge_miibus_writereg(dev, phy, reg, val) + device_t dev; + int phy, reg, val; +{ + struct bge_softc *sc; + int i; + + sc = device_get_softc(dev); + + CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| + BGE_MIPHY(phy)|BGE_MIREG(reg)|val); + + for (i = 0; i < BGE_TIMEOUT; i++) { + if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) + break; + } + + if (i == BGE_TIMEOUT) { + printf("bge%d: PHY read timed out\n", sc->bge_unit); + return(0); + } + + return(0); +} + +static void +bge_miibus_statchg(dev) + device_t dev; +{ + struct bge_softc *sc; + struct mii_data *mii; + + sc = device_get_softc(dev); + mii = device_get_softc(sc->bge_miibus); + + BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); + if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) { + BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); + } else { + BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); + } + + if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { + BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); + } else { + BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); + } + + bge_phy_hack(sc); + + return; +} + +/* + * Handle events that have triggered interrupts. + */ +static void +bge_handle_events(sc) + struct bge_softc *sc; +{ + + return; +} + +/* + * Memory management for jumbo frames. + */ + +static int +bge_alloc_jumbo_mem(sc) + struct bge_softc *sc; +{ + caddr_t ptr; + register int i; + struct bge_jpool_entry *entry; + + /* Grab a big chunk o' storage. */ + sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, + M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); + + if (sc->bge_cdata.bge_jumbo_buf == NULL) { + printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); + return(ENOBUFS); + } + + SLIST_INIT(&sc->bge_jfree_listhead); + SLIST_INIT(&sc->bge_jinuse_listhead); + + /* + * Now divide it up into 9K pieces and save the addresses + * in an array. + */ + ptr = sc->bge_cdata.bge_jumbo_buf; + for (i = 0; i < BGE_JSLOTS; i++) { + sc->bge_cdata.bge_jslots[i] = ptr; + ptr += BGE_JLEN; + entry = malloc(sizeof(struct bge_jpool_entry), + M_DEVBUF, M_NOWAIT); + if (entry == NULL) { + contigfree(sc->bge_cdata.bge_jumbo_buf, + BGE_JMEM, M_DEVBUF); + sc->bge_cdata.bge_jumbo_buf = NULL; + printf("bge%d: no memory for jumbo " + "buffer queue!\n", sc->bge_unit); + return(ENOBUFS); + } + entry->slot = i; + SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, + entry, jpool_entries); + } + + return(0); +} + +static void +bge_free_jumbo_mem(sc) + struct bge_softc *sc; +{ + int i; + struct bge_jpool_entry *entry; + + for (i = 0; i < BGE_JSLOTS; i++) { + entry = SLIST_FIRST(&sc->bge_jfree_listhead); + SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); + free(entry, M_DEVBUF); + } + + contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); + + return; +} + +/* + * Allocate a jumbo buffer. + */ +static void * +bge_jalloc(sc) + struct bge_softc *sc; +{ + struct bge_jpool_entry *entry; + + entry = SLIST_FIRST(&sc->bge_jfree_listhead); + + if (entry == NULL) { + printf("bge%d: no free jumbo buffers\n", sc->bge_unit); + return(NULL); + } + + SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); + SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); + return(sc->bge_cdata.bge_jslots[entry->slot]); +} + +/* + * Release a jumbo buffer. + */ +static void +bge_jfree(buf, args) + caddr_t buf; + void *args; +{ + struct bge_jpool_entry *entry; + struct bge_softc *sc; + int i; + + /* Extract the softc struct pointer. */ + sc = (struct bge_softc *)args; + + if (sc == NULL) + panic("bge_jfree: can't find softc pointer!"); + + /* calculate the slot this buffer belongs to */ + + i = ((vm_offset_t)buf + - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; + + if ((i < 0) || (i >= BGE_JSLOTS)) + panic("bge_jfree: asked to free buffer that we don't manage!"); + + entry = SLIST_FIRST(&sc->bge_jinuse_listhead); + if (entry == NULL) + panic("bge_jfree: buffer not in use!"); + entry->slot = i; + SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); + SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); + + return; +} + + +/* + * Intialize a standard receive ring descriptor. + */ +static int +bge_newbuf_std(sc, i, m) + struct bge_softc *sc; + int i; + struct mbuf *m; +{ + struct mbuf *m_new = NULL; + struct bge_rx_bd *r; + + if (m == NULL) { + MGETHDR(m_new, M_DONTWAIT, MT_DATA); + if (m_new == NULL) { + printf("bge%d: mbuf allocation failed " + "-- packet dropped!\n", sc->bge_unit); + return(ENOBUFS); + } + + MCLGET(m_new, M_DONTWAIT); + if (!(m_new->m_flags & M_EXT)) { + printf("bge%d: cluster allocation failed " + "-- packet dropped!\n", sc->bge_unit); + m_freem(m_new); + return(ENOBUFS); + } + m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; + } else { + m_new = m; + m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; + m_new->m_data = m_new->m_ext.ext_buf; + } + + m_adj(m_new, ETHER_ALIGN); + sc->bge_cdata.bge_rx_std_chain[i] = m_new; + r = &sc->bge_rdata->bge_rx_std_ring[i]; + BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); + r->bge_flags = BGE_RXBDFLAG_END; + r->bge_len = m_new->m_len; + r->bge_idx = i; + + return(0); +} + +/* + * Initialize a jumbo receive ring descriptor. This allocates + * a jumbo buffer from the pool managed internally by the driver. + */ +static int +bge_newbuf_jumbo(sc, i, m) + struct bge_softc *sc; + int i; + struct mbuf *m; +{ + struct mbuf *m_new = NULL; + struct bge_rx_bd *r; + + if (m == NULL) { + caddr_t *buf = NULL; + + /* Allocate the mbuf. */ + MGETHDR(m_new, M_DONTWAIT, MT_DATA); + if (m_new == NULL) { + printf("bge%d: mbuf allocation failed " + "-- packet dropped!\n", sc->bge_unit); + return(ENOBUFS); + } + + /* Allocate the jumbo buffer */ + buf = bge_jalloc(sc); + if (buf == NULL) { + m_freem(m_new); + printf("bge%d: jumbo allocation failed " + "-- packet dropped!\n", sc->bge_unit); + return(ENOBUFS); + } + + /* Attach the buffer to the mbuf. */ + m_new->m_data = (void *) buf; + m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; + MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, + (struct bge_softc *)sc, 0, EXT_NET_DRV); + } else { + m_new = m; + m_new->m_data = m_new->m_ext.ext_buf; + m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; + } + + m_adj(m_new, ETHER_ALIGN); + /* Set up the descriptor. */ + r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; + sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; + BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); + r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; + r->bge_len = m_new->m_len; + r->bge_idx = i; + + return(0); +} + +/* + * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, + * that's 1MB or memory, which is a lot. For now, we fill only the first + * 256 ring entries and hope that our CPU is fast enough to keep up with + * the NIC. + */ +static int +bge_init_rx_ring_std(sc) + struct bge_softc *sc; +{ + int i; + + for (i = 0; i < BGE_SSLOTS; i++) { + if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) + return(ENOBUFS); + }; + + sc->bge_std = i - 1; + CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); + + return(0); +} + +static void +bge_free_rx_ring_std(sc) + struct bge_softc *sc; +{ + int i; + + for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { + if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { + m_freem(sc->bge_cdata.bge_rx_std_chain[i]); + sc->bge_cdata.bge_rx_std_chain[i] = NULL; + } + bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], + sizeof(struct bge_rx_bd)); + } + + return; +} + +static int +bge_init_rx_ring_jumbo(sc) + struct bge_softc *sc; +{ + int i; + struct bge_rcb *rcb; + struct bge_rcb_opaque *rcbo; + + for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { + if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) + return(ENOBUFS); + }; + + sc->bge_jumbo = i - 1; + + rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; + rcbo = (struct bge_rcb_opaque *)rcb; + rcb->bge_flags = 0; + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); + + CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); + + return(0); +} + +static void +bge_free_rx_ring_jumbo(sc) + struct bge_softc *sc; +{ + int i; + + for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { + if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { + m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); + sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; + } + bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], + sizeof(struct bge_rx_bd)); + } + + return; +} + +static void +bge_free_tx_ring(sc) + struct bge_softc *sc; +{ + int i; + + if (sc->bge_rdata->bge_tx_ring == NULL) + return; + + for (i = 0; i < BGE_TX_RING_CNT; i++) { + if (sc->bge_cdata.bge_tx_chain[i] != NULL) { + m_freem(sc->bge_cdata.bge_tx_chain[i]); + sc->bge_cdata.bge_tx_chain[i] = NULL; + } + bzero((char *)&sc->bge_rdata->bge_tx_ring[i], + sizeof(struct bge_tx_bd)); + } + + return; +} + +static int +bge_init_tx_ring(sc) + struct bge_softc *sc; +{ + sc->bge_txcnt = 0; + sc->bge_tx_saved_considx = 0; + CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); + CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); + + return(0); +} + +#define BGE_POLY 0xEDB88320 + +static u_int32_t +bge_crc(addr) + caddr_t addr; +{ + u_int32_t idx, bit, data, crc; + + /* Compute CRC for the address value. */ + crc = 0xFFFFFFFF; /* initial value */ + + for (idx = 0; idx < 6; idx++) { + for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) + crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); + } + + return(crc & 0x7F); +} + +static void +bge_setmulti(sc) + struct bge_softc *sc; +{ + struct ifnet *ifp; + struct ifmultiaddr *ifma; + u_int32_t hashes[4] = { 0, 0, 0, 0 }; + int h, i; + + ifp = &sc->arpcom.ac_if; + + if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { + for (i = 0; i < 4; i++) + CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); + return; + } + + /* First, zot all the existing filters. */ + for (i = 0; i < 4; i++) + CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); + + /* Now program new ones. */ + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); + } + + for (i = 0; i < 4; i++) + CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); + + return; +} + +/* + * Do endian, PCI and DMA initialization. Also check the on-board ROM + * self-test results. + */ +static int +bge_chipinit(sc) + struct bge_softc *sc; +{ + u_int32_t cachesize; + int i; + + /* Set endianness before we access any non-PCI registers. */ +#if BYTE_ORDER == BIG_ENDIAN + pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, + BGE_BIGENDIAN_INIT, 4); +#else + pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, + BGE_LITTLEENDIAN_INIT, 4); +#endif + + /* + * Check the 'ROM failed' bit on the RX CPU to see if + * self-tests passed. + */ + if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { + printf("bge%d: RX CPU self-diagnostics failed!\n", + sc->bge_unit); + return(ENODEV); + } + + /* Clear the MAC control register */ + CSR_WRITE_4(sc, BGE_MAC_MODE, 0); + + /* + * Clear the MAC statistics block in the NIC's + * internal memory. + */ + for (i = BGE_STATS_BLOCK; + i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) + BGE_MEMWIN_WRITE(sc, i, 0); + + for (i = BGE_STATUS_BLOCK; + i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) + BGE_MEMWIN_WRITE(sc, i, 0); + + /* Set up the PCI DMA control register. */ + pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, + BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F, 4); + + /* + * Set up general mode register. + */ + CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| + BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| + BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| + BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM); + + /* Get cache line size. */ + cachesize = pci_read_config(sc->bge_dev, BGE_PCI_CACHESZ, 1); + + /* + * Avoid violating PCI spec on certain chip revs. + */ + if (pci_read_config(sc->bge_dev, BGE_PCI_CMD, 4) & PCIM_CMD_MWIEN) { + switch(cachesize) { + case 1: + PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, + BGE_PCI_WRITE_BNDRY_16BYTES, 4); + break; + case 2: + PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, + BGE_PCI_WRITE_BNDRY_32BYTES, 4); + break; + case 4: + PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, + BGE_PCI_WRITE_BNDRY_64BYTES, 4); + break; + case 8: + PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, + BGE_PCI_WRITE_BNDRY_128BYTES, 4); + break; + case 16: + PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, + BGE_PCI_WRITE_BNDRY_256BYTES, 4); + break; + case 32: + PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, + BGE_PCI_WRITE_BNDRY_512BYTES, 4); + break; + case 64: + PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, + BGE_PCI_WRITE_BNDRY_1024BYTES, 4); + break; + default: + /* Disable PCI memory write and invalidate. */ + if (bootverbose) + printf("bge%d: cache line size %d not " + "supported; disabling PCI MWI\n", + sc->bge_unit, cachesize); + PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, + PCIM_CMD_MWIEN, 4); + break; + } + } + +#ifdef __brokenalpha__ + /* + * Must insure that we do not cross an 8K (bytes) boundary + * for DMA reads. Our highest limit is 1K bytes. This is a + * restriction on some ALPHA platforms with early revision + * 21174 PCI chipsets, such as the AlphaPC 164lx + */ + PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); +#endif + + /* Set the timer prescaler (always 66Mhz) */ + CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); + + return(0); +} + +static int +bge_blockinit(sc) + struct bge_softc *sc; +{ + struct bge_rcb *rcb; + struct bge_rcb_opaque *rcbo; + int i; + + /* + * Initialize the memory window pointer register so that + * we can access the first 32K of internal NIC RAM. This will + * allow us to set up the TX send ring RCBs and the RX return + * ring RCBs, plus other things which live in NIC memory. + */ + CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); + + /* Configure mbuf memory pool */ + if (sc->bge_extram) { + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); + } else { + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); + } + + /* Configure DMA resource pool */ + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); + + /* Configure mbuf pool watermarks */ + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); + + /* Configure DMA resource watermarks */ + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); + + /* Enable buffer manager */ + CSR_WRITE_4(sc, BGE_BMAN_MODE, + BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); + + /* Poll for buffer manager start indication */ + for (i = 0; i < BGE_TIMEOUT; i++) { + if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) + break; + DELAY(10); + } + + if (i == BGE_TIMEOUT) { + printf("bge%d: buffer manager failed to start\n", + sc->bge_unit); + return(ENXIO); + } + + /* Enable flow-through queues */ + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); + + /* Wait until queue initialization is complete */ + for (i = 0; i < BGE_TIMEOUT; i++) { + if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) + break; + DELAY(10); + } + + if (i == BGE_TIMEOUT) { + printf("bge%d: flow-through queue init failed\n", + sc->bge_unit); + return(ENXIO); + } + + /* Initialize the standard RX ring control block */ + rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; + BGE_HOSTADDR(rcb->bge_hostaddr) = + vtophys(&sc->bge_rdata->bge_rx_std_ring); + rcb->bge_max_len = BGE_MAX_FRAMELEN; + if (sc->bge_extram) + rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; + else + rcb->bge_nicaddr = BGE_STD_RX_RINGS; + rcb->bge_flags = 0; + rcbo = (struct bge_rcb_opaque *)rcb; + CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); + CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); + CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); + CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); + + /* + * Initialize the jumbo RX ring control block + * We set the 'ring disabled' bit in the flags + * field until we're actually ready to start + * using this ring (i.e. once we set the MTU + * high enough to require it). + */ + rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; + BGE_HOSTADDR(rcb->bge_hostaddr) = + vtophys(&sc->bge_rdata->bge_rx_jumbo_ring); + rcb->bge_max_len = BGE_MAX_FRAMELEN; + if (sc->bge_extram) + rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; + else + rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; + rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; + + rcbo = (struct bge_rcb_opaque *)rcb; + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); + + /* Set up dummy disabled mini ring RCB */ + rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; + rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; + rcbo = (struct bge_rcb_opaque *)rcb; + CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); + + /* + * Set the BD ring replentish thresholds. The recommended + * values are 1/8th the number of descriptors allocated to + * each ring. + */ + CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); + CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); + + /* + * Disable all unused send rings by setting the 'ring disabled' + * bit in the flags field of all the TX send ring control blocks. + * These are located in NIC memory. + */ + rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + + BGE_SEND_RING_RCB); + for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { + rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; + rcb->bge_max_len = 0; + rcb->bge_nicaddr = 0; + rcb++; + } + + /* Configure TX RCB 0 (we use only the first ring) */ + rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + + BGE_SEND_RING_RCB); + rcb->bge_hostaddr.bge_addr_hi = 0; + BGE_HOSTADDR(rcb->bge_hostaddr) = + vtophys(&sc->bge_rdata->bge_tx_ring); + rcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); + rcb->bge_max_len = BGE_TX_RING_CNT; + rcb->bge_flags = 0; + + /* Disable all unused RX return rings */ + rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + + BGE_RX_RETURN_RING_RCB); + for (i = 0; i < BGE_RX_RINGS_MAX; i++) { + rcb->bge_hostaddr.bge_addr_hi = 0; + rcb->bge_hostaddr.bge_addr_lo = 0; + rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; + rcb->bge_max_len = BGE_RETURN_RING_CNT; + rcb->bge_nicaddr = 0; + CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + + (i * (sizeof(u_int64_t))), 0); + rcb++; + } + + /* Initialize RX ring indexes */ + CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); + CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); + CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); + + /* + * Set up RX return ring 0 + * Note that the NIC address for RX return rings is 0x00000000. + * The return rings live entirely within the host, so the + * nicaddr field in the RCB isn't used. + */ + rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + + BGE_RX_RETURN_RING_RCB); + rcb->bge_hostaddr.bge_addr_hi = 0; + BGE_HOSTADDR(rcb->bge_hostaddr) = + vtophys(&sc->bge_rdata->bge_rx_return_ring); + rcb->bge_nicaddr = 0x00000000; + rcb->bge_max_len = BGE_RETURN_RING_CNT; + rcb->bge_flags = 0; + + /* Set random backoff seed for TX */ + CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, + sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + + sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + + sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + + BGE_TX_BACKOFF_SEED_MASK); + + /* Set inter-packet gap */ + CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); + + /* + * Specify which ring to use for packets that don't match + * any RX rules. + */ + CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); + + /* + * Configure number of RX lists. One interrupt distribution + * list, sixteen active lists, one bad frames class. + */ + CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); + + /* Inialize RX list placement stats mask. */ + CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); + CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); + + /* Disable host coalescing until we get it set up */ + CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); + + /* Poll to make sure it's shut down. */ + for (i = 0; i < BGE_TIMEOUT; i++) { + if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) + break; + DELAY(10); + } + + if (i == BGE_TIMEOUT) { + printf("bge%d: host coalescing engine failed to idle\n", + sc->bge_unit); + return(ENXIO); + } + + /* Set up host coalescing defaults */ + CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); + CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); + CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); + CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); + CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); + CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); + CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); + CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); + CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); + + /* Set up address of statistics block */ + CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); + CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); + CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, + vtophys(&sc->bge_rdata->bge_info.bge_stats)); + + /* Set up address of status block */ + CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); + CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); + CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, + vtophys(&sc->bge_rdata->bge_status_block)); + sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; + sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; + + /* Turn on host coalescing state machine */ + CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); + + /* Turn on RX BD completion state machine and enable attentions */ + CSR_WRITE_4(sc, BGE_RBDC_MODE, + BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); + + /* Turn on RX list placement state machine */ + CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); + + /* Turn on RX list selector state machine. */ + CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); + + /* Turn on DMA, clear stats */ + CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| + BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| + BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| + BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| + (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); + + /* Set misc. local control, enable interrupts on attentions */ + CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); + +#ifdef notdef + /* Assert GPIO pins for PHY reset */ + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| + BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| + BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); +#endif + + /* Turn on DMA completion state machine */ + CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); + + /* Turn on write DMA state machine */ + CSR_WRITE_4(sc, BGE_WDMA_MODE, + BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); + + /* Turn on read DMA state machine */ + CSR_WRITE_4(sc, BGE_RDMA_MODE, + BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); + + /* Turn on RX data completion state machine */ + CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); + + /* Turn on RX BD initiator state machine */ + CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); + + /* Turn on RX data and RX BD initiator state machine */ + CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); + + /* Turn on Mbuf cluster free state machine */ + CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); + + /* Turn on send BD completion state machine */ + CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); + + /* Turn on send data completion state machine */ + CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); + + /* Turn on send data initiator state machine */ + CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); + + /* Turn on send BD initiator state machine */ + CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); + + /* Turn on send BD selector state machine */ + CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); + + CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); + CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, + BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); + + /* init LED register */ + CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); + + /* ack/clear link change events */ + CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| + BGE_MACSTAT_CFG_CHANGED); + CSR_WRITE_4(sc, BGE_MI_STS, 0); + + /* Enable PHY auto polling (for MII/GMII only) */ + if (sc->bge_tbi) { + CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); + } else + BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); + + /* Enable link state change attentions. */ + BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); + + return(0); +} + +/* + * Probe for a Broadcom chip. Check the PCI vendor and device IDs + * against our list and return its name if we find a match. Note + * that since the Broadcom controller contains VPD support, we + * can get the device name string from the controller itself instead + * of the compiled-in string. This is a little slow, but it guarantees + * we'll always announce the right product name. + */ +static int +bge_probe(dev) + device_t dev; +{ + struct bge_type *t; + struct bge_softc *sc; + + t = bge_devs; + + sc = device_get_softc(dev); + bzero(sc, sizeof(struct bge_softc)); + sc->bge_unit = device_get_unit(dev); + sc->bge_dev = dev; + + while(t->bge_name != NULL) { + if ((pci_get_vendor(dev) == t->bge_vid) && + (pci_get_device(dev) == t->bge_did)) { +#ifdef notdef + bge_vpd_read(sc); + device_set_desc(dev, sc->bge_vpd_prodname); +#endif + device_set_desc(dev, t->bge_name); + return(0); + } + t++; + } + + return(ENXIO); +} + +static int +bge_attach(dev) + device_t dev; +{ + int s; + u_int32_t command; + struct ifnet *ifp; + struct bge_softc *sc; + int unit, error = 0, rid; + + s = splimp(); + + sc = device_get_softc(dev); + unit = device_get_unit(dev); + sc->bge_dev = dev; + sc->bge_unit = unit; + + /* + * Map control/status registers. + */ + pci_enable_busmaster(dev); + pci_enable_io(dev, SYS_RES_MEMORY); + command = pci_read_config(dev, PCIR_COMMAND, 4); + + if (!(command & PCIM_CMD_MEMEN)) { + printf("bge%d: failed to enable memory mapping!\n", unit); + error = ENXIO; + goto fail; + } + + rid = BGE_PCI_BAR0; + sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, + 0, ~0, 1, RF_ACTIVE); + + if (sc->bge_res == NULL) { + printf ("bge%d: couldn't map memory\n", unit); + error = ENXIO; + goto fail; + } + + sc->bge_btag = rman_get_bustag(sc->bge_res); + sc->bge_bhandle = rman_get_bushandle(sc->bge_res); + sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); + + /* + * XXX FIXME: rman_get_virtual() on the alpha is currently + * broken and returns a physical address instead of a kernel + * virtual address. Consequently, we need to do a little + * extra mangling of the vhandle on the alpha. This should + * eventually be fixed! The whole idea here is to get rid + * of platform dependencies. + */ +#ifdef __alpha__ + if (pci_cvt_to_bwx(sc->bge_vhandle)) + sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle); + else + sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle); + sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle); +#endif + + /* Allocate interrupt */ + rid = 0; + + sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, + RF_SHAREABLE | RF_ACTIVE); + + if (sc->bge_irq == NULL) { + printf("bge%d: couldn't map interrupt\n", unit); + error = ENXIO; + goto fail; + } + + error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, + bge_intr, sc, &sc->bge_intrhand); + + if (error) { + bge_release_resources(sc); + printf("bge%d: couldn't set up irq\n", unit); + goto fail; + } + + sc->bge_unit = unit; + + /* Try to reset the chip. */ + bge_reset(sc); + + if (bge_chipinit(sc)) { + printf("bge%d: chip initialization failed\n", sc->bge_unit); + bge_release_resources(sc); + error = ENXIO; + goto fail; + } + + /* + * Get station address from the EEPROM. + */ + if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, + BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { + printf("bge%d: failed to read station address\n", unit); + bge_release_resources(sc); + error = ENXIO; + goto fail; + } + + /* + * A Broadcom chip was detected. Inform the world. + */ + printf("bge%d: Ethernet address: %6D\n", unit, + sc->arpcom.ac_enaddr, ":"); + + /* Allocate the general information block and ring buffers. */ + sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, + M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); + + if (sc->bge_rdata == NULL) { + bge_release_resources(sc); + error = ENXIO; + printf("bge%d: no memory for list buffers!\n", sc->bge_unit); + goto fail; + } + + bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); + + /* Try to allocate memory for jumbo buffers. */ + if (bge_alloc_jumbo_mem(sc)) { + printf("bge%d: jumbo buffer allocation " + "failed\n", sc->bge_unit); + bge_release_resources(sc); + error = ENXIO; + goto fail; + } + + /* Set default tuneable values. */ + sc->bge_stat_ticks = BGE_TICKS_PER_SEC; + sc->bge_rx_coal_ticks = 150; + sc->bge_tx_coal_ticks = 150; + sc->bge_rx_max_coal_bds = 64; + sc->bge_tx_max_coal_bds = 128; + + /* Set up ifnet structure */ + ifp = &sc->arpcom.ac_if; + ifp->if_softc = sc; + ifp->if_unit = sc->bge_unit; + ifp->if_name = "bge"; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = bge_ioctl; + ifp->if_output = ether_output; + ifp->if_start = bge_start; + ifp->if_watchdog = bge_watchdog; + ifp->if_init = bge_init; + ifp->if_mtu = ETHERMTU; + ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; + ifp->if_hwassist = BGE_CSUM_FEATURES; + ifp->if_capabilities = IFCAP_HWCSUM; + ifp->if_capenable = ifp->if_capabilities; + + /* The SysKonnect SK-9D41 is a 1000baseSX card. */ + if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) + sc->bge_tbi = 1; + + if (sc->bge_tbi) { + ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, + bge_ifmedia_upd, bge_ifmedia_sts); + ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); + ifmedia_add(&sc->bge_ifmedia, + IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); + ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); + ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); + } else { + /* + * Do transceiver setup. + */ + if (mii_phy_probe(dev, &sc->bge_miibus, + bge_ifmedia_upd, bge_ifmedia_sts)) { + printf("bge%d: MII without any PHY!\n", sc->bge_unit); + bge_release_resources(sc); + bge_free_jumbo_mem(sc); + error = ENXIO; + goto fail; + } + } + + /* + * Call MI attach routine. + */ + ether_ifattach(ifp, ETHER_BPF_SUPPORTED); + callout_handle_init(&sc->bge_stat_ch); + +fail: + splx(s); + + return(error); +} + +static int +bge_detach(dev) + device_t dev; +{ + struct bge_softc *sc; + struct ifnet *ifp; + int s; + + s = splimp(); + + sc = device_get_softc(dev); + ifp = &sc->arpcom.ac_if; + + ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); + bge_stop(sc); + bge_reset(sc); + + if (sc->bge_tbi) { + ifmedia_removeall(&sc->bge_ifmedia); + } else { + bus_generic_detach(dev); + device_delete_child(dev, sc->bge_miibus); + } + + bge_release_resources(sc); + bge_free_jumbo_mem(sc); + + splx(s); + + return(0); +} + +static void +bge_release_resources(sc) + struct bge_softc *sc; +{ + device_t dev; + + dev = sc->bge_dev; + + if (sc->bge_vpd_prodname != NULL) + free(sc->bge_vpd_prodname, M_DEVBUF); + + if (sc->bge_vpd_readonly != NULL) + free(sc->bge_vpd_readonly, M_DEVBUF); + + if (sc->bge_intrhand != NULL) + bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); + + if (sc->bge_irq != NULL) + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); + + if (sc->bge_res != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, + BGE_PCI_BAR0, sc->bge_res); + + if (sc->bge_rdata != NULL) + contigfree(sc->bge_rdata, + sizeof(struct bge_ring_data), M_DEVBUF); + + return; +} + +static void +bge_reset(sc) + struct bge_softc *sc; +{ + device_t dev; + u_int32_t cachesize, command, pcistate; + int i, val = 0; + + dev = sc->bge_dev; + + /* Save some important PCI state. */ + cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); + command = pci_read_config(dev, BGE_PCI_CMD, 4); + pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); + + pci_write_config(dev, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| + BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); + + /* Issue global reset */ + bge_writereg_ind(sc, BGE_MISC_CFG, + BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); + + DELAY(1000); + + /* Reset some of the PCI state that got zapped by reset */ + pci_write_config(dev, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| + BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); + pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); + pci_write_config(dev, BGE_PCI_CMD, command, 4); + bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); + + /* + * Prevent PXE restart: write a magic number to the + * general communications memory at 0xB50. + */ + bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); + /* + * Poll the value location we just wrote until + * we see the 1's complement of the magic number. + * This indicates that the firmware initialization + * is complete. + */ + for (i = 0; i < BGE_TIMEOUT; i++) { + val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); + if (val == ~BGE_MAGIC_NUMBER) + break; + DELAY(10); + } + + if (i == BGE_TIMEOUT) { + printf("bge%d: firmware handshake timed out\n", sc->bge_unit); + return; + } + + /* + * XXX Wait for the value of the PCISTATE register to + * return to its original pre-reset state. This is a + * fairly good indicator of reset completion. If we don't + * wait for the reset to fully complete, trying to read + * from the device's non-PCI registers may yield garbage + * results. + */ + for (i = 0; i < BGE_TIMEOUT; i++) { + if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) + break; + DELAY(10); + } + + /* Enable memory arbiter. */ + CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); + + /* Fix up byte swapping */ + CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| + BGE_MODECTL_BYTESWAP_DATA); + + CSR_WRITE_4(sc, BGE_MAC_MODE, 0); + + DELAY(10000); + + return; +} + +/* + * Frame reception handling. This is called if there's a frame + * on the receive return list. + * + * Note: we have to be able to handle two possibilities here: + * 1) the frame is from the jumbo recieve ring + * 2) the frame is from the standard receive ring + */ + +static void +bge_rxeof(sc) + struct bge_softc *sc; +{ + struct ifnet *ifp; + int stdcnt = 0, jumbocnt = 0; + + ifp = &sc->arpcom.ac_if; + + while(sc->bge_rx_saved_considx != + sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { + struct bge_rx_bd *cur_rx; + u_int32_t rxidx; + struct ether_header *eh; + struct mbuf *m = NULL; + u_int16_t vlan_tag = 0; + int have_tag = 0; + + cur_rx = + &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; + + rxidx = cur_rx->bge_idx; + BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); + + if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { + have_tag = 1; + vlan_tag = cur_rx->bge_vlan_tag; + } + + if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { + BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); + m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; + sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; + jumbocnt++; + if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { + ifp->if_ierrors++; + bge_newbuf_jumbo(sc, sc->bge_jumbo, m); + continue; + } + if (bge_newbuf_jumbo(sc, + sc->bge_jumbo, NULL) == ENOBUFS) { + ifp->if_ierrors++; + bge_newbuf_jumbo(sc, sc->bge_jumbo, m); + continue; + } + } else { + BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); + m = sc->bge_cdata.bge_rx_std_chain[rxidx]; + sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; + stdcnt++; + if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { + ifp->if_ierrors++; + bge_newbuf_std(sc, sc->bge_std, m); + continue; + } + if (bge_newbuf_std(sc, sc->bge_std, + NULL) == ENOBUFS) { + ifp->if_ierrors++; + bge_newbuf_std(sc, sc->bge_std, m); + continue; + } + } + + ifp->if_ipackets++; + eh = mtod(m, struct ether_header *); + m->m_pkthdr.len = m->m_len = cur_rx->bge_len; + m->m_pkthdr.rcvif = ifp; + + /* Remove header from mbuf and pass it on. */ + m_adj(m, sizeof(struct ether_header)); + + if (ifp->if_hwassist) { + m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; + if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) + m->m_pkthdr.csum_flags |= CSUM_IP_VALID; + if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { + m->m_pkthdr.csum_data = + cur_rx->bge_tcp_udp_csum; + m->m_pkthdr.csum_flags |= + CSUM_DATA_VALID|CSUM_PSEUDO_HDR; + } + } + + /* + * If we received a packet with a vlan tag, pass it + * to vlan_input() instead of ether_input(). + */ + if (have_tag) { + VLAN_INPUT_TAG(ifp, eh, m, vlan_tag); + have_tag = vlan_tag = 0; + continue; + } + + ether_input(ifp, eh, m); + } + + CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); + if (stdcnt) + CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); + if (jumbocnt) + CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); + + return; +} + +static void +bge_txeof(sc) + struct bge_softc *sc; +{ + struct bge_tx_bd *cur_tx = NULL; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + + /* + * Go through our tx ring and free mbufs for those + * frames that have been sent. + */ + while (sc->bge_tx_saved_considx != + sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { + u_int32_t idx = 0; + + idx = sc->bge_tx_saved_considx; + cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; + if (cur_tx->bge_flags & BGE_TXBDFLAG_END) + ifp->if_opackets++; + if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { + m_freem(sc->bge_cdata.bge_tx_chain[idx]); + sc->bge_cdata.bge_tx_chain[idx] = NULL; + } + sc->bge_txcnt--; + BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); + ifp->if_timer = 0; + } + + if (cur_tx != NULL) + ifp->if_flags &= ~IFF_OACTIVE; + + return; +} + +static void +bge_intr(xsc) + void *xsc; +{ + struct bge_softc *sc; + struct ifnet *ifp; + + sc = xsc; + ifp = &sc->arpcom.ac_if; + +#ifdef notdef + /* Avoid this for now -- checking this register is expensive. */ + /* Make sure this is really our interrupt. */ + if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) + return; +#endif + /* Ack interrupt and stop others from occuring. */ + CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); + + /* Process link state changes. */ + if (sc->bge_rdata->bge_status_block.bge_status & + BGE_STATFLAG_LINKSTATE_CHANGED) { + sc->bge_link = 0; + untimeout(bge_tick, sc, sc->bge_stat_ch); + bge_tick(sc); + /* ack the event to clear/reset it */ + CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| + BGE_MACSTAT_CFG_CHANGED); + CSR_WRITE_4(sc, BGE_MI_STS, 0); + } + + if (ifp->if_flags & IFF_RUNNING) { + /* Check RX return ring producer/consumer */ + bge_rxeof(sc); + + /* Check TX ring producer/consumer */ + bge_txeof(sc); + } + + bge_handle_events(sc); + + /* Re-enable interrupts. */ + CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); + + if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) + bge_start(ifp); + + return; +} + +static void +bge_tick(xsc) + void *xsc; +{ + struct bge_softc *sc; + struct mii_data *mii = NULL; + struct ifmedia *ifm = NULL; + struct ifnet *ifp; + int s; + + sc = xsc; + ifp = &sc->arpcom.ac_if; + + s = splimp(); + + bge_stats_update(sc); + sc->bge_stat_ch = timeout(bge_tick, sc, hz); + if (sc->bge_link) + return; + + if (sc->bge_tbi) { + ifm = &sc->bge_ifmedia; + if (CSR_READ_4(sc, BGE_MAC_STS) & + BGE_MACSTAT_TBI_PCS_SYNCHED) { + sc->bge_link++; + CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); + printf("bge%d: gigabit link up\n", sc->bge_unit); + if (ifp->if_snd.ifq_head != NULL) + bge_start(ifp); + } + return; + } + + mii = device_get_softc(sc->bge_miibus); + mii_tick(mii); + + if (!sc->bge_link) { + mii_pollstat(mii); + if (mii->mii_media_status & IFM_ACTIVE && + IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { + sc->bge_link++; + if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || + IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) + printf("bge%d: gigabit link up\n", + sc->bge_unit); + if (ifp->if_snd.ifq_head != NULL) + bge_start(ifp); + } + } + + splx(s); + + return; +} + +static void +bge_stats_update(sc) + struct bge_softc *sc; +{ + struct ifnet *ifp; + struct bge_stats *stats; + + ifp = &sc->arpcom.ac_if; + + stats = (struct bge_stats *)(sc->bge_vhandle + + BGE_MEMWIN_START + BGE_STATS_BLOCK); + + ifp->if_collisions += + (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + + stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + + stats->dot3StatsExcessiveCollisions.bge_addr_lo + + stats->dot3StatsLateCollisions.bge_addr_lo) - + ifp->if_collisions; + +#ifdef notdef + ifp->if_collisions += + (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + + sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + + sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + + sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - + ifp->if_collisions; +#endif + + return; +} + +/* + * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data + * pointers to descriptors. + */ +static int +bge_encap(sc, m_head, txidx) + struct bge_softc *sc; + struct mbuf *m_head; + u_int32_t *txidx; +{ + struct bge_tx_bd *f = NULL; + struct mbuf *m; + u_int32_t frag, cur, cnt = 0; + u_int16_t csum_flags = 0; + struct ifvlan *ifv = NULL; + + if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && + m_head->m_pkthdr.rcvif != NULL && + m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) + ifv = m_head->m_pkthdr.rcvif->if_softc; + + m = m_head; + cur = frag = *txidx; + + if (m_head->m_pkthdr.csum_flags) { + if (m_head->m_pkthdr.csum_flags & CSUM_IP) + csum_flags |= BGE_TXBDFLAG_IP_CSUM; + if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) + csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; + if (m_head->m_flags & M_LASTFRAG) + csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; + else if (m_head->m_flags & M_FRAG) + csum_flags |= BGE_TXBDFLAG_IP_FRAG; + } + + /* + * Start packing the mbufs in this chain into + * the fragment pointers. Stop when we run out + * of fragments or hit the end of the mbuf chain. + */ + for (m = m_head; m != NULL; m = m->m_next) { + if (m->m_len != 0) { + f = &sc->bge_rdata->bge_tx_ring[frag]; + if (sc->bge_cdata.bge_tx_chain[frag] != NULL) + break; + BGE_HOSTADDR(f->bge_addr) = + vtophys(mtod(m, vm_offset_t)); + f->bge_len = m->m_len; + f->bge_flags = csum_flags; + if (ifv != NULL) { + f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; + f->bge_vlan_tag = ifv->ifv_tag; + } else { + f->bge_vlan_tag = 0; + } + /* + * Sanity check: avoid coming within 16 descriptors + * of the end of the ring. + */ + if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) + return(ENOBUFS); + cur = frag; + BGE_INC(frag, BGE_TX_RING_CNT); + cnt++; + } + } + + if (m != NULL) + return(ENOBUFS); + + if (frag == sc->bge_tx_saved_considx) + return(ENOBUFS); + + sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; + sc->bge_cdata.bge_tx_chain[cur] = m_head; + sc->bge_txcnt += cnt; + + *txidx = frag; + + return(0); +} + +/* + * Main transmit routine. To avoid having to do mbuf copies, we put pointers + * to the mbuf data regions directly in the transmit descriptors. + */ +static void +bge_start(ifp) + struct ifnet *ifp; +{ + struct bge_softc *sc; + struct mbuf *m_head = NULL; + u_int32_t prodidx = 0; + + sc = ifp->if_softc; + + if (!sc->bge_link && ifp->if_snd.ifq_len < 10) + return; + + prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); + + while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { + IF_DEQUEUE(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + + /* + * XXX + * safety overkill. If this is a fragmented packet chain + * with delayed TCP/UDP checksums, then only encapsulate + * it if we have enough descriptors to handle the entire + * chain at once. + * (paranoia -- may not actually be needed) + */ + if (m_head->m_flags & M_FIRSTFRAG && + m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { + if ((BGE_TX_RING_CNT - sc->bge_txcnt) < + m_head->m_pkthdr.csum_data + 16) { + IF_PREPEND(&ifp->if_snd, m_head); + ifp->if_flags |= IFF_OACTIVE; + break; + } + } + + /* + * Pack the data into the transmit ring. If we + * don't have room, set the OACTIVE flag and wait + * for the NIC to drain the ring. + */ + if (bge_encap(sc, m_head, &prodidx)) { + IF_PREPEND(&ifp->if_snd, m_head); + ifp->if_flags |= IFF_OACTIVE; + break; + } + + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ + if (ifp->if_bpf) + bpf_mtap(ifp, m_head); + } + + /* Transmit */ + CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); + + /* + * Set a timeout in case the chip goes out to lunch. + */ + ifp->if_timer = 5; + + return; +} + +/* + * If we have a BCM5400 or BCM5401 PHY, we need to properly + * program its internal DSP. Failing to do this can result in + * massive packet loss at 1Gb speeds. + */ +static void +bge_phy_hack(sc) + struct bge_softc *sc; +{ + struct bge_bcom_hack bhack[] = { + { BRGPHY_MII_AUXCTL, 0x4C20 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, + { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, + { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, + { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, + { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, + { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, + { 0, 0 } }; + u_int16_t vid, did; + int i; + + vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1); + did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2); + + if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && + (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || + MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { + i = 0; + while(bhack[i].reg) { + bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg, + bhack[i].val); + i++; + } + } + + return; +} + +static void +bge_init(xsc) + void *xsc; +{ + struct bge_softc *sc = xsc; + struct ifnet *ifp; + u_int16_t *m; + int s; + + s = splimp(); + + ifp = &sc->arpcom.ac_if; + + if (ifp->if_flags & IFF_RUNNING) + return; + + /* Cancel pending I/O and flush buffers. */ + bge_stop(sc); + bge_reset(sc); + bge_chipinit(sc); + + /* + * Init the various state machines, ring + * control blocks and firmware. + */ + if (bge_blockinit(sc)) { + printf("bge%d: initialization failure\n", sc->bge_unit); + splx(s); + return; + } + + ifp = &sc->arpcom.ac_if; + + /* Specify MTU. */ + CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + + ETHER_HDR_LEN + ETHER_CRC_LEN); + + /* Load our MAC address. */ + m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; + CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); + CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); + + /* Enable or disable promiscuous mode as needed. */ + if (ifp->if_flags & IFF_PROMISC) { + BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); + } else { + BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); + } + + /* Program multicast filter. */ + bge_setmulti(sc); + + /* Init RX ring. */ + bge_init_rx_ring_std(sc); + + /* Init jumbo RX ring. */ + if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) + bge_init_rx_ring_jumbo(sc); + + /* Init our RX return ring index */ + sc->bge_rx_saved_considx = 0; + + /* Init TX ring. */ + bge_init_tx_ring(sc); + + /* Turn on transmitter */ + BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); + + /* Turn on receiver */ + BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); + + /* Tell firmware we're alive. */ + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + + /* Enable host interrupts. */ + BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); + BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); + CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); + + bge_ifmedia_upd(ifp); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + + splx(s); + + sc->bge_stat_ch = timeout(bge_tick, sc, hz); + + return; +} + +/* + * Set media options. + */ +static int +bge_ifmedia_upd(ifp) + struct ifnet *ifp; +{ + struct bge_softc *sc; + struct mii_data *mii; + struct ifmedia *ifm; + + sc = ifp->if_softc; + ifm = &sc->bge_ifmedia; + + /* If this is a 1000baseX NIC, enable the TBI port. */ + if (sc->bge_tbi) { + if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) + return(EINVAL); + switch(IFM_SUBTYPE(ifm->ifm_media)) { + case IFM_AUTO: + break; + case IFM_1000_SX: + if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { + BGE_CLRBIT(sc, BGE_MAC_MODE, + BGE_MACMODE_HALF_DUPLEX); + } else { + BGE_SETBIT(sc, BGE_MAC_MODE, + BGE_MACMODE_HALF_DUPLEX); + } + break; + default: + return(EINVAL); + } + return(0); + } + + mii = device_get_softc(sc->bge_miibus); + sc->bge_link = 0; + if (mii->mii_instance) { + struct mii_softc *miisc; + for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; + miisc = LIST_NEXT(miisc, mii_list)) + mii_phy_reset(miisc); + } + bge_phy_hack(sc); + mii_mediachg(mii); + + return(0); +} + +/* + * Report current media status. + */ +static void +bge_ifmedia_sts(ifp, ifmr) + struct ifnet *ifp; + struct ifmediareq *ifmr; +{ + struct bge_softc *sc; + struct mii_data *mii; + + sc = ifp->if_softc; + + if (sc->bge_tbi) { + ifmr->ifm_status = IFM_AVALID; + ifmr->ifm_active = IFM_ETHER; + if (CSR_READ_4(sc, BGE_MAC_STS) & + BGE_MACSTAT_TBI_PCS_SYNCHED) + ifmr->ifm_status |= IFM_ACTIVE; + ifmr->ifm_active |= IFM_1000_SX; + if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) + ifmr->ifm_active |= IFM_HDX; + else + ifmr->ifm_active |= IFM_FDX; + return; + } + + mii = device_get_softc(sc->bge_miibus); + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + + return; +} + +static int +bge_ioctl(ifp, command, data) + struct ifnet *ifp; + u_long command; + caddr_t data; +{ + struct bge_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *) data; + int s, mask, error = 0; + struct mii_data *mii; + + s = splimp(); + + switch(command) { + case SIOCSIFADDR: + case SIOCGIFADDR: + error = ether_ioctl(ifp, command, data); + break; + case SIOCSIFMTU: + if (ifr->ifr_mtu > BGE_JUMBO_MTU) + error = EINVAL; + else { + ifp->if_mtu = ifr->ifr_mtu; + ifp->if_flags &= ~IFF_RUNNING; + bge_init(sc); + } + break; + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + /* + * If only the state of the PROMISC flag changed, + * then just use the 'set promisc mode' command + * instead of reinitializing the entire NIC. Doing + * a full re-init means reloading the firmware and + * waiting for it to start up, which may take a + * second or two. + */ + if (ifp->if_flags & IFF_RUNNING && + ifp->if_flags & IFF_PROMISC && + !(sc->bge_if_flags & IFF_PROMISC)) { + BGE_SETBIT(sc, BGE_RX_MODE, + BGE_RXMODE_RX_PROMISC); + } else if (ifp->if_flags & IFF_RUNNING && + !(ifp->if_flags & IFF_PROMISC) && + sc->bge_if_flags & IFF_PROMISC) { + BGE_CLRBIT(sc, BGE_RX_MODE, + BGE_RXMODE_RX_PROMISC); + } else + bge_init(sc); + } else { + if (ifp->if_flags & IFF_RUNNING) { + bge_stop(sc); + } + } + sc->bge_if_flags = ifp->if_flags; + error = 0; + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + if (ifp->if_flags & IFF_RUNNING) { + bge_setmulti(sc); + error = 0; + } + break; + case SIOCSIFMEDIA: + case SIOCGIFMEDIA: + if (sc->bge_tbi) { + error = ifmedia_ioctl(ifp, ifr, + &sc->bge_ifmedia, command); + } else { + mii = device_get_softc(sc->bge_miibus); + error = ifmedia_ioctl(ifp, ifr, + &mii->mii_media, command); + } + break; + case SIOCSIFCAP: + mask = ifr->ifr_reqcap ^ ifp->if_capenable; + if (mask & IFCAP_HWCSUM) { + if (IFCAP_HWCSUM & ifp->if_capenable) + ifp->if_capenable &= ~IFCAP_HWCSUM; + else + ifp->if_capenable |= IFCAP_HWCSUM; + } + error = 0; + break; + default: + error = EINVAL; + break; + } + + (void)splx(s); + + return(error); +} + +static void +bge_watchdog(ifp) + struct ifnet *ifp; +{ + struct bge_softc *sc; + + sc = ifp->if_softc; + + printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); + + ifp->if_flags &= ~IFF_RUNNING; + bge_init(sc); + + ifp->if_oerrors++; + + return; +} + +/* + * Stop the adapter and free any mbufs allocated to the + * RX and TX lists. + */ +static void +bge_stop(sc) + struct bge_softc *sc; +{ + struct ifnet *ifp; + struct ifmedia_entry *ifm; + struct mii_data *mii = NULL; + int mtmp, itmp; + + ifp = &sc->arpcom.ac_if; + + if (!sc->bge_tbi) + mii = device_get_softc(sc->bge_miibus); + + untimeout(bge_tick, sc, sc->bge_stat_ch); + + /* + * Disable all of the receiver blocks + */ + BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); + + /* + * Disable all of the transmit blocks + */ + BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); + BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); + + /* + * Shut down all of the memory managers and related + * state machines. + */ + BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); + BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); + BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); + BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); + BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); + + /* Disable host interrupts. */ + BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); + CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); + + /* + * Tell firmware we're shutting down. + */ + BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + + /* Free the RX lists. */ + bge_free_rx_ring_std(sc); + + /* Free jumbo RX list. */ + bge_free_rx_ring_jumbo(sc); + + /* Free TX buffers. */ + bge_free_tx_ring(sc); + + /* + * Isolate/power down the PHY, but leave the media selection + * unchanged so that things will be put back to normal when + * we bring the interface back up. + */ + if (!sc->bge_tbi) { + itmp = ifp->if_flags; + ifp->if_flags |= IFF_UP; + ifm = mii->mii_media.ifm_cur; + mtmp = ifm->ifm_media; + ifm->ifm_media = IFM_ETHER|IFM_NONE; + mii_mediachg(mii); + ifm->ifm_media = mtmp; + ifp->if_flags = itmp; + } + + sc->bge_link = 0; + + sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; + + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + + return; +} + +/* + * Stop all chip I/O so that the kernel's probe routines don't + * get confused by errant DMAs when rebooting. + */ +static void +bge_shutdown(dev) + device_t dev; +{ + struct bge_softc *sc; + + sc = device_get_softc(dev); + + bge_stop(sc); + bge_reset(sc); + + return; +} diff --git a/sys/dev/bge/if_bgereg.h b/sys/dev/bge/if_bgereg.h new file mode 100644 index 000000000000..76ba5d58896f --- /dev/null +++ b/sys/dev/bge/if_bgereg.h @@ -0,0 +1,2132 @@ +/* + * Copyright (c) 2001 Wind River Systems + * Copyright (c) 1997, 1998, 1999, 2001 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * BCM570x memory map. The internal memory layout varies somewhat + * depending on whether or not we have external SSRAM attached. + * The BCM5700 can have up to 16MB of external memory. The BCM5701 + * is apparently not designed to use external SSRAM. The mappings + * up to the first 4 send rings are the same for both internal and + * external memory configurations. Note that mini RX ring space is + * only available with external SSRAM configurations, which means + * the mini RX ring is not supported on the BCM5701. + * + * The NIC's memory can be accessed by the host in one of 3 ways: + * + * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA + * registers in PCI config space can be used to read any 32-bit + * address within the NIC's memory. + * + * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config + * space can be used in conjunction with the memory window in the + * device register space at offset 0x8000 to read any 32K chunk + * of NIC memory. + * + * 3) Flat mode. If the 'flat mode' bit in the PCI state register is + * set, the device I/O mapping consumes 32MB of host address space, + * allowing all of the registers and internal NIC memory to be + * accessed directly. NIC memory addresses are offset by 0x01000000. + * Flat mode consumes so much host address space that it is not + * recommended. + */ +#define BGE_PAGE_ZERO 0x00000000 +#define BGE_PAGE_ZERO_END 0x000000FF +#define BGE_SEND_RING_RCB 0x00000100 +#define BGE_SEND_RING_RCB_END 0x000001FF +#define BGE_RX_RETURN_RING_RCB 0x00000200 +#define BGE_RX_RETURN_RING_RCB_END 0x000002FF +#define BGE_STATS_BLOCK 0x00000300 +#define BGE_STATS_BLOCK_END 0x00000AFF +#define BGE_STATUS_BLOCK 0x00000B00 +#define BGE_STATUS_BLOCK_END 0x00000B4F +#define BGE_SOFTWARE_GENCOMM 0x00000B50 +#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF +#define BGE_UNMAPPED 0x00001000 +#define BGE_UNMAPPED_END 0x00001FFF +#define BGE_DMA_DESCRIPTORS 0x00002000 +#define BGE_DMA_DESCRIPTORS_END 0x00003FFF +#define BGE_SEND_RING_1_TO_4 0x00004000 +#define BGE_SEND_RING_1_TO_4_END 0x00005FFF + +/* Mappings for internal memory configuration */ +#define BGE_STD_RX_RINGS 0x00006000 +#define BGE_STD_RX_RINGS_END 0x00006FFF +#define BGE_JUMBO_RX_RINGS 0x00007000 +#define BGE_JUMBO_RX_RINGS_END 0x00007FFF +#define BGE_BUFFPOOL_1 0x00008000 +#define BGE_BUFFPOOL_1_END 0x0000FFFF +#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ +#define BGE_BUFFPOOL_2_END 0x00017FFF +#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ +#define BGE_BUFFPOOL_3_END 0x0001FFFF + +/* Mappings for external SSRAM configurations */ +#define BGE_SEND_RING_5_TO_6 0x00006000 +#define BGE_SEND_RING_5_TO_6_END 0x00006FFF +#define BGE_SEND_RING_7_TO_8 0x00007000 +#define BGE_SEND_RING_7_TO_8_END 0x00007FFF +#define BGE_SEND_RING_9_TO_16 0x00008000 +#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF +#define BGE_EXT_STD_RX_RINGS 0x0000C000 +#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF +#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 +#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF +#define BGE_MINI_RX_RINGS 0x0000E000 +#define BGE_MINI_RX_RINGS_END 0x0000FFFF +#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ +#define BGE_AVAIL_REGION1_END 0x00017FFF +#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ +#define BGE_AVAIL_REGION2_END 0x0001FFFF +#define BGE_EXT_SSRAM 0x00020000 +#define BGE_EXT_SSRAM_END 0x000FFFFF + + +/* + * BCM570x register offsets. These are memory mapped registers + * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. + * Each register must be accessed using 32 bit operations. + * + * All registers are accessed through a 32K shared memory block. + * The first group of registers are actually copies of the PCI + * configuration space registers. + */ + +/* + * PCI registers defined in the PCI 2.2 spec. + */ +#define BGE_PCI_VID 0x00 +#define BGE_PCI_DID 0x02 +#define BGE_PCI_CMD 0x04 +#define BGE_PCI_STS 0x06 +#define BGE_PCI_REV 0x08 +#define BGE_PCI_CLASS 0x09 +#define BGE_PCI_CACHESZ 0x0C +#define BGE_PCI_LATTIMER 0x0D +#define BGE_PCI_HDRTYPE 0x0E +#define BGE_PCI_BIST 0x0F +#define BGE_PCI_BAR0 0x10 +#define BGE_PCI_BAR1 0x14 +#define BGE_PCI_SUBSYS 0x2C +#define BGE_PCI_SUBVID 0x2E +#define BGE_PCI_ROMBASE 0x30 +#define BGE_PCI_CAPPTR 0x34 +#define BGE_PCI_INTLINE 0x3C +#define BGE_PCI_INTPIN 0x3D +#define BGE_PCI_MINGNT 0x3E +#define BGE_PCI_MAXLAT 0x3F +#define BGE_PCI_PCIXCAP 0x40 +#define BGE_PCI_NEXTPTR_PM 0x41 +#define BGE_PCI_PCIX_CMD 0x42 +#define BGE_PCI_PCIX_STS 0x44 +#define BGE_PCI_PWRMGMT_CAPID 0x48 +#define BGE_PCI_NEXTPTR_VPD 0x49 +#define BGE_PCI_PWRMGMT_CAPS 0x4A +#define BGE_PCI_PWRMGMT_CMD 0x4C +#define BGE_PCI_PWRMGMT_STS 0x4D +#define BGE_PCI_PWRMGMT_DATA 0x4F +#define BGE_PCI_VPD_CAPID 0x50 +#define BGE_PCI_NEXTPTR_MSI 0x51 +#define BGE_PCI_VPD_ADDR 0x52 +#define BGE_PCI_VPD_DATA 0x54 +#define BGE_PCI_MSI_CAPID 0x58 +#define BGE_PCI_NEXTPTR_NONE 0x59 +#define BGE_PCI_MSI_CTL 0x5A +#define BGE_PCI_MSI_ADDR_HI 0x5C +#define BGE_PCI_MSI_ADDR_LO 0x60 +#define BGE_PCI_MSI_DATA 0x64 + +/* + * PCI registers specific to the BCM570x family. + */ +#define BGE_PCI_MISC_CTL 0x68 +#define BGE_PCI_DMA_RW_CTL 0x6C +#define BGE_PCI_PCISTATE 0x70 +#define BGE_PCI_CLKCTL 0x74 +#define BGE_PCI_REG_BASEADDR 0x78 +#define BGE_PCI_MEMWIN_BASEADDR 0x7C +#define BGE_PCI_REG_DATA 0x80 +#define BGE_PCI_MEMWIN_DATA 0x84 +#define BGE_PCI_MODECTL 0x88 +#define BGE_PCI_MISC_CFG 0x8C +#define BGE_PCI_MISC_LOCALCTL 0x90 +#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 +#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C +#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 +#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 +#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 +#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC +#define BGE_PCI_ISR_MBX_HI 0xB0 +#define BGE_PCI_ISR_MBX_LO 0xB4 + +/* PCI Misc. Host control register */ +#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 +#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 +#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 +#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 +#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 +#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 +#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 +#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 +#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 + +#define BGE_BIGENDIAN_INIT \ + (BGE_BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ + BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ + BGE_PCIMISCCTL_INDIRECT_ACCESS|PCIMISCCTL_MASK_PCI_INTR) + +#define BGE_LITTLEENDIAN_INIT \ + (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ + BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) + +#define BGE_ASICREV_TIGON_I 0x40000000 +#define BGE_ASICREV_TIGON_II 0x60000000 +#define BGE_ASICREV_BCM5700_B0 0x71000000 +#define BGE_ASICREV_BCM5700_B1 0x71020000 +#define BGE_ASICREV_BCM5700_B2 0x71030000 +#define BGE_ASICREV_BCM5700_ALTIMA 0x71040000 +#define BGE_ASICREV_BCM5700_C0 0x72000000 + +/* PCI DMA Read/Write Control register */ +#define BGE_PCIDMARWCTL_MINDMA 0x000000FF +#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 +#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 +#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 +#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 +#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 +#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 +#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 +#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 + +#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 +#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 +#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 +#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 +#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 +#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 +#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 +#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 + +#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 +#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 +#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 +#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 +#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 +#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 +#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 +#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 + +/* + * PCI state register -- note, this register is read only + * unless the PCISTATE_WR bit of the PCI Misc. Host Control + * register is set. + */ +#define BGE_PCISTATE_FORCE_RESET 0x00000001 +#define BGE_PCISTATE_INTR_STATE 0x00000002 +#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ +#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ +#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ +#define BGE_PCISTATE_WANT_EXPROM 0x00000020 +#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 +#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 +#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 + +/* + * PCI Clock Control register -- note, this register is read only + * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control + * register is set. + */ +#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F +#define BGE_PCICLOCKCTL_M66EN 0x00000080 +#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 +#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 +#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 +#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 +#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 +#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 +#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 +#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 + + +#ifndef PCIM_CMD_MWIEN +#define PCIM_CMD_MWIEN 0x0010 +#endif + +/* + * High priority mailbox registers + * Each mailbox is 64-bits wide, though we only use the + * lower 32 bits. To write a 64-bit value, write the upper 32 bits + * first. The NIC will load the mailbox after the lower 32 bit word + * has been updated. + */ +#define BGE_MBX_IRQ0_HI 0x0200 +#define BGE_MBX_IRQ0_LO 0x0204 +#define BGE_MBX_IRQ1_HI 0x0208 +#define BGE_MBX_IRQ1_LO 0x020C +#define BGE_MBX_IRQ2_HI 0x0210 +#define BGE_MBX_IRQ2_LO 0x0214 +#define BGE_MBX_IRQ3_HI 0x0218 +#define BGE_MBX_IRQ3_LO 0x021C +#define BGE_MBX_GEN0_HI 0x0220 +#define BGE_MBX_GEN0_LO 0x0224 +#define BGE_MBX_GEN1_HI 0x0228 +#define BGE_MBX_GEN1_LO 0x022C +#define BGE_MBX_GEN2_HI 0x0230 +#define BGE_MBX_GEN2_LO 0x0234 +#define BGE_MBX_GEN3_HI 0x0228 +#define BGE_MBX_GEN3_LO 0x022C +#define BGE_MBX_GEN4_HI 0x0240 +#define BGE_MBX_GEN4_LO 0x0244 +#define BGE_MBX_GEN5_HI 0x0248 +#define BGE_MBX_GEN5_LO 0x024C +#define BGE_MBX_GEN6_HI 0x0250 +#define BGE_MBX_GEN6_LO 0x0254 +#define BGE_MBX_GEN7_HI 0x0258 +#define BGE_MBX_GEN7_LO 0x025C +#define BGE_MBX_RELOAD_STATS_HI 0x0260 +#define BGE_MBX_RELOAD_STATS_LO 0x0264 +#define BGE_MBX_RX_STD_PROD_HI 0x0268 +#define BGE_MBX_RX_STD_PROD_LO 0x026C +#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 +#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 +#define BGE_MBX_RX_MINI_PROD_HI 0x0278 +#define BGE_MBX_RX_MINI_PROD_LO 0x027C +#define BGE_MBX_RX_CONS0_HI 0x0280 +#define BGE_MBX_RX_CONS0_LO 0x0284 +#define BGE_MBX_RX_CONS1_HI 0x0288 +#define BGE_MBX_RX_CONS1_LO 0x028C +#define BGE_MBX_RX_CONS2_HI 0x0290 +#define BGE_MBX_RX_CONS2_LO 0x0294 +#define BGE_MBX_RX_CONS3_HI 0x0298 +#define BGE_MBX_RX_CONS3_LO 0x029C +#define BGE_MBX_RX_CONS4_HI 0x02A0 +#define BGE_MBX_RX_CONS4_LO 0x02A4 +#define BGE_MBX_RX_CONS5_HI 0x02A8 +#define BGE_MBX_RX_CONS5_LO 0x02AC +#define BGE_MBX_RX_CONS6_HI 0x02B0 +#define BGE_MBX_RX_CONS6_LO 0x02B4 +#define BGE_MBX_RX_CONS7_HI 0x02B8 +#define BGE_MBX_RX_CONS7_LO 0x02BC +#define BGE_MBX_RX_CONS8_HI 0x02C0 +#define BGE_MBX_RX_CONS8_LO 0x02C4 +#define BGE_MBX_RX_CONS9_HI 0x02C8 +#define BGE_MBX_RX_CONS9_LO 0x02CC +#define BGE_MBX_RX_CONS10_HI 0x02D0 +#define BGE_MBX_RX_CONS10_LO 0x02D4 +#define BGE_MBX_RX_CONS11_HI 0x02D8 +#define BGE_MBX_RX_CONS11_LO 0x02DC +#define BGE_MBX_RX_CONS12_HI 0x02E0 +#define BGE_MBX_RX_CONS12_LO 0x02E4 +#define BGE_MBX_RX_CONS13_HI 0x02E8 +#define BGE_MBX_RX_CONS13_LO 0x02EC +#define BGE_MBX_RX_CONS14_HI 0x02F0 +#define BGE_MBX_RX_CONS14_LO 0x02F4 +#define BGE_MBX_RX_CONS15_HI 0x02F8 +#define BGE_MBX_RX_CONS15_LO 0x02FC +#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 +#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 +#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 +#define BGE_MBX_TX_HOST_PROD1_LO 0x030C +#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 +#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 +#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 +#define BGE_MBX_TX_HOST_PROD3_LO 0x031C +#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 +#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 +#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 +#define BGE_MBX_TX_HOST_PROD5_LO 0x032C +#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 +#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 +#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 +#define BGE_MBX_TX_HOST_PROD7_LO 0x033C +#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 +#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 +#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 +#define BGE_MBX_TX_HOST_PROD9_LO 0x034C +#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 +#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 +#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 +#define BGE_MBX_TX_HOST_PROD11_LO 0x035C +#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 +#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 +#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 +#define BGE_MBX_TX_HOST_PROD13_LO 0x036C +#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 +#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 +#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 +#define BGE_MBX_TX_HOST_PROD15_LO 0x037C +#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 +#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 +#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 +#define BGE_MBX_TX_NIC_PROD1_LO 0x038C +#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 +#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 +#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 +#define BGE_MBX_TX_NIC_PROD3_LO 0x039C +#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 +#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 +#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 +#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC +#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 +#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 +#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 +#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC +#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 +#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 +#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 +#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC +#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 +#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 +#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 +#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC +#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 +#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 +#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 +#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC +#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 +#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 +#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 +#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC + +#define BGE_TX_RINGS_MAX 4 +#define BGE_TX_RINGS_EXTSSRAM_MAX 16 +#define BGE_RX_RINGS_MAX 16 + +/* Ethernet MAC control registers */ +#define BGE_MAC_MODE 0x0400 +#define BGE_MAC_STS 0x0404 +#define BGE_MAC_EVT_ENB 0x0408 +#define BGE_MAC_LED_CTL 0x040C +#define BGE_MAC_ADDR1_LO 0x0410 +#define BGE_MAC_ADDR1_HI 0x0414 +#define BGE_MAC_ADDR2_LO 0x0418 +#define BGE_MAC_ADDR2_HI 0x041C +#define BGE_MAC_ADDR3_LO 0x0420 +#define BGE_MAC_ADDR3_HI 0x0424 +#define BGE_MAC_ADDR4_LO 0x0428 +#define BGE_MAC_ADDR4_HI 0x042C +#define BGE_WOL_PATPTR 0x0430 +#define BGE_WOL_PATCFG 0x0434 +#define BGE_TX_RANDOM_BACKOFF 0x0438 +#define BGE_RX_MTU 0x043C +#define BGE_GBIT_PCS_TEST 0x0440 +#define BGE_TX_TBI_AUTONEG 0x0444 +#define BGE_RX_TBI_AUTONEG 0x0448 +#define BGE_MI_COMM 0x044C +#define BGE_MI_STS 0x0450 +#define BGE_MI_MODE 0x0454 +#define BGE_AUTOPOLL_STS 0x0458 +#define BGE_TX_MODE 0x045C +#define BGE_TX_STS 0x0460 +#define BGE_TX_LENGTHS 0x0464 +#define BGE_RX_MODE 0x0468 +#define BGE_RX_STS 0x046C +#define BGE_MAR0 0x0470 +#define BGE_MAR1 0x0474 +#define BGE_MAR2 0x0478 +#define BGE_MAR3 0x047C +#define BGE_RX_BD_RULES_CTL0 0x0480 +#define BGE_RX_BD_RULES_MASKVAL0 0x0484 +#define BGE_RX_BD_RULES_CTL1 0x0488 +#define BGE_RX_BD_RULES_MASKVAL1 0x048C +#define BGE_RX_BD_RULES_CTL2 0x0490 +#define BGE_RX_BD_RULES_MASKVAL2 0x0494 +#define BGE_RX_BD_RULES_CTL3 0x0498 +#define BGE_RX_BD_RULES_MASKVAL3 0x049C +#define BGE_RX_BD_RULES_CTL4 0x04A0 +#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 +#define BGE_RX_BD_RULES_CTL5 0x04A8 +#define BGE_RX_BD_RULES_MASKVAL5 0x04AC +#define BGE_RX_BD_RULES_CTL6 0x04B0 +#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 +#define BGE_RX_BD_RULES_CTL7 0x04B8 +#define BGE_RX_BD_RULES_MASKVAL7 0x04BC +#define BGE_RX_BD_RULES_CTL8 0x04C0 +#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 +#define BGE_RX_BD_RULES_CTL9 0x04C8 +#define BGE_RX_BD_RULES_MASKVAL9 0x04CC +#define BGE_RX_BD_RULES_CTL10 0x04D0 +#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 +#define BGE_RX_BD_RULES_CTL11 0x04D8 +#define BGE_RX_BD_RULES_MASKVAL11 0x04DC +#define BGE_RX_BD_RULES_CTL12 0x04E0 +#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 +#define BGE_RX_BD_RULES_CTL13 0x04E8 +#define BGE_RX_BD_RULES_MASKVAL13 0x04EC +#define BGE_RX_BD_RULES_CTL14 0x04F0 +#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 +#define BGE_RX_BD_RULES_CTL15 0x04F8 +#define BGE_RX_BD_RULES_MASKVAL15 0x04FC +#define BGE_RX_RULES_CFG 0x0500 +#define BGE_RX_STATS 0x0800 +#define BGE_TX_STATS 0x0880 + +/* Ethernet MAC Mode register */ +#define BGE_MACMODE_RESET 0x00000001 +#define BGE_MACMODE_HALF_DUPLEX 0x00000002 +#define BGE_MACMODE_PORTMODE 0x0000000C +#define BGE_MACMODE_LOOPBACK 0x00000010 +#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 +#define BGE_MACMODE_TX_BURST_ENB 0x00000100 +#define BGE_MACMODE_MAX_DEFER 0x00000200 +#define BGE_MACMODE_LINK_POLARITY 0x00000400 +#define BGE_MACMODE_RX_STATS_ENB 0x00000800 +#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 +#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 +#define BGE_MACMODE_TX_STATS_ENB 0x00004000 +#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 +#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 +#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 +#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 +#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 +#define BGE_MACMODE_MIP_ENB 0x00100000 +#define BGE_MACMODE_TXDMA_ENB 0x00200000 +#define BGE_MACMODE_RXDMA_ENB 0x00400000 +#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 + +#define BGE_PORTMODE_NONE 0x00000000 +#define BGE_PORTMODE_MII 0x00000004 +#define BGE_PORTMODE_GMII 0x00000008 +#define BGE_PORTMODE_TBI 0x0000000C + +/* MAC Status register */ +#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 +#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 +#define BGE_MACSTAT_RX_CFG 0x00000004 +#define BGE_MACSTAT_CFG_CHANGED 0x00000008 +#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 +#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 +#define BGE_MACSTAT_LINK_CHANGED 0x00001000 +#define BGE_MACSTAT_MI_COMPLETE 0x00400000 +#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 +#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 +#define BGE_MACSTAT_ODI_ERROR 0x02000000 +#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 +#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 + +/* MAC Event Enable Register */ +#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 +#define BGE_EVTENB_LINK_CHANGED 0x00001000 +#define BGE_EVTENB_MI_COMPLETE 0x00400000 +#define BGE_EVTENB_MI_INTERRUPT 0x00800000 +#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 +#define BGE_EVTENB_ODI_ERROR 0x02000000 +#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 +#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 + +/* LED Control Register */ +#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 +#define BGE_LEDCTL_1000MBPS_LED 0x00000002 +#define BGE_LEDCTL_100MBPS_LED 0x00000004 +#define BGE_LEDCTL_10MBPS_LED 0x00000008 +#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 +#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 +#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 +#define BGE_LEDCTL_1000MBPS_STS 0x00000080 +#define BGE_LEDCTL_100MBPS_STS 0x00000100 +#define BGE_LEDCTL_10MBPS_STS 0x00000200 +#define BGE_LEDCTL_TRADLED_STS 0x00000400 +#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 +#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 + +/* TX backoff seed register */ +#define BGE_TX_BACKOFF_SEED_MASK 0x3F + +/* Autopoll status register */ +#define BGE_AUTOPOLLSTS_ERROR 0x00000001 + +/* Transmit MAC mode register */ +#define BGE_TXMODE_RESET 0x00000001 +#define BGE_TXMODE_ENABLE 0x00000002 +#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 +#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 +#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 + +/* Transmit MAC status register */ +#define BGE_TXSTAT_RX_XOFFED 0x00000001 +#define BGE_TXSTAT_SENT_XOFF 0x00000002 +#define BGE_TXSTAT_SENT_XON 0x00000004 +#define BGE_TXSTAT_LINK_UP 0x00000008 +#define BGE_TXSTAT_ODI_UFLOW 0x00000010 +#define BGE_TXSTAT_ODI_OFLOW 0x00000020 + +/* Transmit MAC lengths register */ +#define BGE_TXLEN_SLOTTIME 0x000000FF +#define BGE_TXLEN_IPG 0x00000F00 +#define BGE_TXLEN_CRS 0x00003000 + +/* Receive MAC mode register */ +#define BGE_RXMODE_RESET 0x00000001 +#define BGE_RXMODE_ENABLE 0x00000002 +#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 +#define BGE_RXMODE_RX_GIANTS 0x00000020 +#define BGE_RXMODE_RX_RUNTS 0x00000040 +#define BGE_RXMODE_8022_LENCHECK 0x00000080 +#define BGE_RXMODE_RX_PROMISC 0x00000100 +#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 +#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 + +/* Receive MAC status register */ +#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 +#define BGE_RXSTAT_RCVD_XOFF 0x00000002 +#define BGE_RXSTAT_RCVD_XON 0x00000004 + +/* Receive Rules Control register */ +#define BGE_RXRULECTL_OFFSET 0x000000FF +#define BGE_RXRULECTL_CLASS 0x00001F00 +#define BGE_RXRULECTL_HDRTYPE 0x0000E000 +#define BGE_RXRULECTL_COMPARE_OP 0x00030000 +#define BGE_RXRULECTL_MAP 0x01000000 +#define BGE_RXRULECTL_DISCARD 0x02000000 +#define BGE_RXRULECTL_MASK 0x04000000 +#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 +#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 +#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 +#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 + +/* Receive Rules Mask register */ +#define BGE_RXRULEMASK_VALUE 0x0000FFFF +#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 + +/* MI communication register */ +#define BGE_MICOMM_DATA 0x0000FFFF +#define BGE_MICOMM_REG 0x001F0000 +#define BGE_MICOMM_PHY 0x03E00000 +#define BGE_MICOMM_CMD 0x0C000000 +#define BGE_MICOMM_READFAIL 0x10000000 +#define BGE_MICOMM_BUSY 0x20000000 + +#define BGE_MIREG(x) ((x & 0x1F) << 16) +#define BGE_MIPHY(x) ((x & 0x1F) << 21) +#define BGE_MICMD_WRITE 0x04000000 +#define BGE_MICMD_READ 0x08000000 + +/* MI status register */ +#define BGE_MISTS_LINK 0x00000001 +#define BGE_MISTS_10MBPS 0x00000002 + +#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 +#define BGE_MIMODE_AUTOPOLL 0x00000010 +#define BGE_MIMODE_CLKCNT 0x001F0000 + + +/* + * Send data initiator control registers. + */ +#define BGE_SDI_MODE 0x0C00 +#define BGE_SDI_STATUS 0x0C04 +#define BGE_SDI_STATS_CTL 0x0C08 +#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C +#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 +#define BGE_LOCSTATS_COS0 0x0C80 +#define BGE_LOCSTATS_COS1 0x0C84 +#define BGE_LOCSTATS_COS2 0x0C88 +#define BGE_LOCSTATS_COS3 0x0C8C +#define BGE_LOCSTATS_COS4 0x0C90 +#define BGE_LOCSTATS_COS5 0x0C84 +#define BGE_LOCSTATS_COS6 0x0C98 +#define BGE_LOCSTATS_COS7 0x0C9C +#define BGE_LOCSTATS_COS8 0x0CA0 +#define BGE_LOCSTATS_COS9 0x0CA4 +#define BGE_LOCSTATS_COS10 0x0CA8 +#define BGE_LOCSTATS_COS11 0x0CAC +#define BGE_LOCSTATS_COS12 0x0CB0 +#define BGE_LOCSTATS_COS13 0x0CB4 +#define BGE_LOCSTATS_COS14 0x0CB8 +#define BGE_LOCSTATS_COS15 0x0CBC +#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 +#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 +#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 +#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC +#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 +#define BGE_LOCSTATS_IRQS 0x0CD4 +#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 +#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC + +/* Send Data Initiator mode register */ +#define BGE_SDIMODE_RESET 0x00000001 +#define BGE_SDIMODE_ENABLE 0x00000002 +#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 + +/* Send Data Initiator stats register */ +#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 + +/* Send Data Initiator stats control register */ +#define BGE_SDISTATSCTL_ENABLE 0x00000001 +#define BGE_SDISTATSCTL_FASTER 0x00000002 +#define BGE_SDISTATSCTL_CLEAR 0x00000004 +#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 +#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 + +/* + * Send Data Completion Control registers + */ +#define BGE_SDC_MODE 0x1000 +#define BGE_SDC_STATUS 0x1004 + +/* Send Data completion mode register */ +#define BGE_SDCMODE_RESET 0x00000001 +#define BGE_SDCMODE_ENABLE 0x00000002 +#define BGE_SDCMODE_ATTN 0x00000004 + +/* Send Data completion status register */ +#define BGE_SDCSTAT_ATTN 0x00000004 + +/* + * Send BD Ring Selector Control registers + */ +#define BGE_SRS_MODE 0x1400 +#define BGE_SRS_STATUS 0x1404 +#define BGE_SRS_HWDIAG 0x1408 +#define BGE_SRS_LOC_NIC_CONS0 0x1440 +#define BGE_SRS_LOC_NIC_CONS1 0x1444 +#define BGE_SRS_LOC_NIC_CONS2 0x1448 +#define BGE_SRS_LOC_NIC_CONS3 0x144C +#define BGE_SRS_LOC_NIC_CONS4 0x1450 +#define BGE_SRS_LOC_NIC_CONS5 0x1454 +#define BGE_SRS_LOC_NIC_CONS6 0x1458 +#define BGE_SRS_LOC_NIC_CONS7 0x145C +#define BGE_SRS_LOC_NIC_CONS8 0x1460 +#define BGE_SRS_LOC_NIC_CONS9 0x1464 +#define BGE_SRS_LOC_NIC_CONS10 0x1468 +#define BGE_SRS_LOC_NIC_CONS11 0x146C +#define BGE_SRS_LOC_NIC_CONS12 0x1470 +#define BGE_SRS_LOC_NIC_CONS13 0x1474 +#define BGE_SRS_LOC_NIC_CONS14 0x1478 +#define BGE_SRS_LOC_NIC_CONS15 0x147C + +/* Send BD Ring Selector Mode register */ +#define BGE_SRSMODE_RESET 0x00000001 +#define BGE_SRSMODE_ENABLE 0x00000002 +#define BGE_SRSMODE_ATTN 0x00000004 + +/* Send BD Ring Selector Status register */ +#define BGE_SRSSTAT_ERROR 0x00000004 + +/* Send BD Ring Selector HW Diagnostics register */ +#define BGE_SRSHWDIAG_STATE 0x0000000F +#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 +#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 +#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 + +/* + * Send BD Initiator Selector Control registers + */ +#define BGE_SBDI_MODE 0x1800 +#define BGE_SBDI_STATUS 0x1804 +#define BGE_SBDI_LOC_NIC_PROD0 0x1808 +#define BGE_SBDI_LOC_NIC_PROD1 0x180C +#define BGE_SBDI_LOC_NIC_PROD2 0x1810 +#define BGE_SBDI_LOC_NIC_PROD3 0x1814 +#define BGE_SBDI_LOC_NIC_PROD4 0x1818 +#define BGE_SBDI_LOC_NIC_PROD5 0x181C +#define BGE_SBDI_LOC_NIC_PROD6 0x1820 +#define BGE_SBDI_LOC_NIC_PROD7 0x1824 +#define BGE_SBDI_LOC_NIC_PROD8 0x1828 +#define BGE_SBDI_LOC_NIC_PROD9 0x182C +#define BGE_SBDI_LOC_NIC_PROD10 0x1830 +#define BGE_SBDI_LOC_NIC_PROD11 0x1834 +#define BGE_SBDI_LOC_NIC_PROD12 0x1838 +#define BGE_SBDI_LOC_NIC_PROD13 0x183C +#define BGE_SBDI_LOC_NIC_PROD14 0x1840 +#define BGE_SBDI_LOC_NIC_PROD15 0x1844 + +/* Send BD Initiator Mode register */ +#define BGE_SBDIMODE_RESET 0x00000001 +#define BGE_SBDIMODE_ENABLE 0x00000002 +#define BGE_SBDIMODE_ATTN 0x00000004 + +/* Send BD Initiator Status register */ +#define BGE_SBDISTAT_ERROR 0x00000004 + +/* + * Send BD Completion Control registers + */ +#define BGE_SBDC_MODE 0x1C00 +#define BGE_SBDC_STATUS 0x1C04 + +/* Send BD Completion Control Mode register */ +#define BGE_SBDCMODE_RESET 0x00000001 +#define BGE_SBDCMODE_ENABLE 0x00000002 +#define BGE_SBDCMODE_ATTN 0x00000004 + +/* Send BD Completion Control Status register */ +#define BGE_SBDCSTAT_ATTN 0x00000004 + +/* + * Receive List Placement Control registers + */ +#define BGE_RXLP_MODE 0x2000 +#define BGE_RXLP_STATUS 0x2004 +#define BGE_RXLP_SEL_LIST_LOCK 0x2008 +#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C +#define BGE_RXLP_CFG 0x2010 +#define BGE_RXLP_STATS_CTL 0x2014 +#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 +#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C +#define BGE_RXLP_HEAD0 0x2100 +#define BGE_RXLP_TAIL0 0x2104 +#define BGE_RXLP_COUNT0 0x2108 +#define BGE_RXLP_HEAD1 0x2110 +#define BGE_RXLP_TAIL1 0x2114 +#define BGE_RXLP_COUNT1 0x2118 +#define BGE_RXLP_HEAD2 0x2120 +#define BGE_RXLP_TAIL2 0x2124 +#define BGE_RXLP_COUNT2 0x2128 +#define BGE_RXLP_HEAD3 0x2130 +#define BGE_RXLP_TAIL3 0x2134 +#define BGE_RXLP_COUNT3 0x2138 +#define BGE_RXLP_HEAD4 0x2140 +#define BGE_RXLP_TAIL4 0x2144 +#define BGE_RXLP_COUNT4 0x2148 +#define BGE_RXLP_HEAD5 0x2150 +#define BGE_RXLP_TAIL5 0x2154 +#define BGE_RXLP_COUNT5 0x2158 +#define BGE_RXLP_HEAD6 0x2160 +#define BGE_RXLP_TAIL6 0x2164 +#define BGE_RXLP_COUNT6 0x2168 +#define BGE_RXLP_HEAD7 0x2170 +#define BGE_RXLP_TAIL7 0x2174 +#define BGE_RXLP_COUNT7 0x2178 +#define BGE_RXLP_HEAD8 0x2180 +#define BGE_RXLP_TAIL8 0x2184 +#define BGE_RXLP_COUNT8 0x2188 +#define BGE_RXLP_HEAD9 0x2190 +#define BGE_RXLP_TAIL9 0x2194 +#define BGE_RXLP_COUNT9 0x2198 +#define BGE_RXLP_HEAD10 0x21A0 +#define BGE_RXLP_TAIL10 0x21A4 +#define BGE_RXLP_COUNT10 0x21A8 +#define BGE_RXLP_HEAD11 0x21B0 +#define BGE_RXLP_TAIL11 0x21B4 +#define BGE_RXLP_COUNT11 0x21B8 +#define BGE_RXLP_HEAD12 0x21C0 +#define BGE_RXLP_TAIL12 0x21C4 +#define BGE_RXLP_COUNT12 0x21C8 +#define BGE_RXLP_HEAD13 0x21D0 +#define BGE_RXLP_TAIL13 0x21D4 +#define BGE_RXLP_COUNT13 0x21D8 +#define BGE_RXLP_HEAD14 0x21E0 +#define BGE_RXLP_TAIL14 0x21E4 +#define BGE_RXLP_COUNT14 0x21E8 +#define BGE_RXLP_HEAD15 0x21F0 +#define BGE_RXLP_TAIL15 0x21F4 +#define BGE_RXLP_COUNT15 0x21F8 +#define BGE_RXLP_LOCSTAT_COS0 0x2200 +#define BGE_RXLP_LOCSTAT_COS1 0x2204 +#define BGE_RXLP_LOCSTAT_COS2 0x2208 +#define BGE_RXLP_LOCSTAT_COS3 0x220C +#define BGE_RXLP_LOCSTAT_COS4 0x2210 +#define BGE_RXLP_LOCSTAT_COS5 0x2214 +#define BGE_RXLP_LOCSTAT_COS6 0x2218 +#define BGE_RXLP_LOCSTAT_COS7 0x221C +#define BGE_RXLP_LOCSTAT_COS8 0x2220 +#define BGE_RXLP_LOCSTAT_COS9 0x2224 +#define BGE_RXLP_LOCSTAT_COS10 0x2228 +#define BGE_RXLP_LOCSTAT_COS11 0x222C +#define BGE_RXLP_LOCSTAT_COS12 0x2230 +#define BGE_RXLP_LOCSTAT_COS13 0x2234 +#define BGE_RXLP_LOCSTAT_COS14 0x2238 +#define BGE_RXLP_LOCSTAT_COS15 0x223C +#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 +#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 +#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 +#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C +#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 +#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 +#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 + + +/* Receive List Placement mode register */ +#define BGE_RXLPMODE_RESET 0x00000001 +#define BGE_RXLPMODE_ENABLE 0x00000002 +#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 +#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 +#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 + +/* Receive List Placement Status register */ +#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 +#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 +#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 + +/* + * Receive Data and Receive BD Initiator Control Registers + */ +#define BGE_RDBDI_MODE 0x2400 +#define BGE_RDBDI_STATUS 0x2404 +#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 +#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 +#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 +#define BGE_RX_JUMBO_RCB_NICADDR 0x244C +#define BGE_RX_STD_RCB_HADDR_HI 0x2450 +#define BGE_RX_STD_RCB_HADDR_LO 0x2454 +#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 +#define BGE_RX_STD_RCB_NICADDR 0x245C +#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 +#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 +#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 +#define BGE_RX_MINI_RCB_NICADDR 0x246C +#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 +#define BGE_RDBDI_STD_RX_CONS 0x2474 +#define BGE_RDBDI_MINI_RX_CONS 0x2478 +#define BGE_RDBDI_RETURN_PROD0 0x2480 +#define BGE_RDBDI_RETURN_PROD1 0x2484 +#define BGE_RDBDI_RETURN_PROD2 0x2488 +#define BGE_RDBDI_RETURN_PROD3 0x248C +#define BGE_RDBDI_RETURN_PROD4 0x2490 +#define BGE_RDBDI_RETURN_PROD5 0x2494 +#define BGE_RDBDI_RETURN_PROD6 0x2498 +#define BGE_RDBDI_RETURN_PROD7 0x249C +#define BGE_RDBDI_RETURN_PROD8 0x24A0 +#define BGE_RDBDI_RETURN_PROD9 0x24A4 +#define BGE_RDBDI_RETURN_PROD10 0x24A8 +#define BGE_RDBDI_RETURN_PROD11 0x24AC +#define BGE_RDBDI_RETURN_PROD12 0x24B0 +#define BGE_RDBDI_RETURN_PROD13 0x24B4 +#define BGE_RDBDI_RETURN_PROD14 0x24B8 +#define BGE_RDBDI_RETURN_PROD15 0x24BC +#define BGE_RDBDI_HWDIAG 0x24C0 + + +/* Receive Data and Receive BD Initiator Mode register */ +#define BGE_RDBDIMODE_RESET 0x00000001 +#define BGE_RDBDIMODE_ENABLE 0x00000002 +#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 +#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 +#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 + +/* Receive Data and Receive BD Initiator Status register */ +#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 +#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 +#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 + + +/* + * Receive Data Completion Control registers + */ +#define BGE_RDC_MODE 0x2800 + +/* Receive Data Completion Mode register */ +#define BGE_RDCMODE_RESET 0x00000001 +#define BGE_RDCMODE_ENABLE 0x00000002 +#define BGE_RDCMODE_ATTN 0x00000004 + +/* + * Receive BD Initiator Control registers + */ +#define BGE_RBDI_MODE 0x2C00 +#define BGE_RBDI_STATUS 0x2C04 +#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 +#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C +#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 +#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 +#define BGE_RBDI_STD_REPL_THRESH 0x2C18 +#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C + +/* Receive BD Initiator Mode register */ +#define BGE_RBDIMODE_RESET 0x00000001 +#define BGE_RBDIMODE_ENABLE 0x00000002 +#define BGE_RBDIMODE_ATTN 0x00000004 + +/* Receive BD Initiator Status register */ +#define BGE_RBDISTAT_ATTN 0x00000004 + +/* + * Receive BD Completion Control registers + */ +#define BGE_RBDC_MODE 0x3000 +#define BGE_RBDC_STATUS 0x3004 +#define BGE_RBDC_JUMBO_BD_PROD 0x3008 +#define BGE_RBDC_STD_BD_PROD 0x300C +#define BGE_RBDC_MINI_BD_PROD 0x3010 + +/* Receive BD completion mode register */ +#define BGE_RBDCMODE_RESET 0x00000001 +#define BGE_RBDCMODE_ENABLE 0x00000002 +#define BGE_RBDCMODE_ATTN 0x00000004 + +/* Receive BD completion status register */ +#define BGE_RBDCSTAT_ERROR 0x00000004 + +/* + * Receive List Selector Control registers + */ +#define BGE_RXLS_MODE 0x3400 +#define BGE_RXLS_STATUS 0x3404 + +/* Receive List Selector Mode register */ +#define BGE_RXLSMODE_RESET 0x00000001 +#define BGE_RXLSMODE_ENABLE 0x00000002 +#define BGE_RXLSMODE_ATTN 0x00000004 + +/* Receive List Selector Status register */ +#define BGE_RXLSSTAT_ERROR 0x00000004 + +/* + * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) + */ +#define BGE_MBCF_MODE 0x3800 +#define BGE_MBCF_STATUS 0x3804 + +/* Mbuf Cluster Free mode register */ +#define BGE_MBCFMODE_RESET 0x00000001 +#define BGE_MBCFMODE_ENABLE 0x00000002 +#define BGE_MBCFMODE_ATTN 0x00000004 + +/* Mbuf Cluster Free status register */ +#define BGE_MBCFSTAT_ERROR 0x00000004 + +/* + * Host Coalescing Control registers + */ +#define BGE_HCC_MODE 0x3C00 +#define BGE_HCC_STATUS 0x3C04 +#define BGE_HCC_RX_COAL_TICKS 0x3C08 +#define BGE_HCC_TX_COAL_TICKS 0x3C0C +#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 +#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 +#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ +#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ +#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ +#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ +#define BGE_HCC_STATS_TICKS 0x3C28 +#define BGE_HCC_STATS_ADDR_HI 0x3C30 +#define BGE_HCC_STATS_ADDR_LO 0x3C34 +#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 +#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C +#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ +#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ +#define BGE_FLOW_ATTN 0x3C48 +#define BGE_HCC_JUMBO_BD_CONS 0x3C50 +#define BGE_HCC_STD_BD_CONS 0x3C54 +#define BGE_HCC_MINI_BD_CONS 0x3C58 +#define BGE_HCC_RX_RETURN_PROD0 0x3C80 +#define BGE_HCC_RX_RETURN_PROD1 0x3C84 +#define BGE_HCC_RX_RETURN_PROD2 0x3C88 +#define BGE_HCC_RX_RETURN_PROD3 0x3C8C +#define BGE_HCC_RX_RETURN_PROD4 0x3C90 +#define BGE_HCC_RX_RETURN_PROD5 0x3C94 +#define BGE_HCC_RX_RETURN_PROD6 0x3C98 +#define BGE_HCC_RX_RETURN_PROD7 0x3C9C +#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 +#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 +#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 +#define BGE_HCC_RX_RETURN_PROD11 0x3CAC +#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 +#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 +#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 +#define BGE_HCC_RX_RETURN_PROD15 0x3CBC +#define BGE_HCC_TX_BD_CONS0 0x3CC0 +#define BGE_HCC_TX_BD_CONS1 0x3CC4 +#define BGE_HCC_TX_BD_CONS2 0x3CC8 +#define BGE_HCC_TX_BD_CONS3 0x3CCC +#define BGE_HCC_TX_BD_CONS4 0x3CD0 +#define BGE_HCC_TX_BD_CONS5 0x3CD4 +#define BGE_HCC_TX_BD_CONS6 0x3CD8 +#define BGE_HCC_TX_BD_CONS7 0x3CDC +#define BGE_HCC_TX_BD_CONS8 0x3CE0 +#define BGE_HCC_TX_BD_CONS9 0x3CE4 +#define BGE_HCC_TX_BD_CONS10 0x3CE8 +#define BGE_HCC_TX_BD_CONS11 0x3CEC +#define BGE_HCC_TX_BD_CONS12 0x3CF0 +#define BGE_HCC_TX_BD_CONS13 0x3CF4 +#define BGE_HCC_TX_BD_CONS14 0x3CF8 +#define BGE_HCC_TX_BD_CONS15 0x3CFC + + +/* Host coalescing mode register */ +#define BGE_HCCMODE_RESET 0x00000001 +#define BGE_HCCMODE_ENABLE 0x00000002 +#define BGE_HCCMODE_ATTN 0x00000004 +#define BGE_HCCMODE_COAL_NOW 0x00000008 +#define BGE_HCCMODE_MSI_BITS 0x0x000070 +#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 + +#define BGE_STATBLKSZ_FULL 0x00000000 +#define BGE_STATBLKSZ_64BYTE 0x00000080 +#define BGE_STATBLKSZ_32BYTE 0x00000100 + +/* Host coalescing status register */ +#define BGE_HCCSTAT_ERROR 0x00000004 + +/* Flow attention register */ +#define BGE_FLOWATTN_MB_LOWAT 0x00000040 +#define BGE_FLOWATTN_MEMARB 0x00000080 +#define BGE_FLOWATTN_HOSTCOAL 0x00008000 +#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 +#define BGE_FLOWATTN_RCB_INVAL 0x00020000 +#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 +#define BGE_FLOWATTN_RDBDI 0x00080000 +#define BGE_FLOWATTN_RXLS 0x00100000 +#define BGE_FLOWATTN_RXLP 0x00200000 +#define BGE_FLOWATTN_RBDC 0x00400000 +#define BGE_FLOWATTN_RBDI 0x00800000 +#define BGE_FLOWATTN_SDC 0x08000000 +#define BGE_FLOWATTN_SDI 0x10000000 +#define BGE_FLOWATTN_SRS 0x20000000 +#define BGE_FLOWATTN_SBDC 0x40000000 +#define BGE_FLOWATTN_SBDI 0x80000000 + +/* + * Memory arbiter registers + */ +#define BGE_MARB_MODE 0x4000 +#define BGE_MARB_STATUS 0x4004 +#define BGE_MARB_TRAPADDR_HI 0x4008 +#define BGE_MARB_TRAPADDR_LO 0x400C + +/* Memory arbiter mode register */ +#define BGE_MARBMODE_RESET 0x00000001 +#define BGE_MARBMODE_ENABLE 0x00000002 +#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 +#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 +#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 +#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 +#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 +#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 +#define BGE_MARBMODE_PCI_TRAP 0x00000100 +#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 +#define BGE_MARBMODE_RXQ_TRAP 0x00000400 +#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 +#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 +#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 +#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 +#define BGE_MARBMODE_MBUF_TRAP 0x00008000 +#define BGE_MARBMODE_TXDI_TRAP 0x00010000 +#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 +#define BGE_MARBMODE_TXBD_TRAP 0x00040000 +#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 +#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 +#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 +#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 +#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 +#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 +#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 + +/* Memory arbiter status register */ +#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 +#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 +#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 +#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 +#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 +#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 +#define BGE_MARBSTAT_PCI_TRAP 0x00000100 +#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 +#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 +#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 +#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 +#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 +#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 +#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 +#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 +#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 +#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 +#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 +#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 +#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 +#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 +#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 +#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 +#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 + +/* + * Buffer manager control registers + */ +#define BGE_BMAN_MODE 0x4400 +#define BGE_BMAN_STATUS 0x4404 +#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 +#define BGE_BMAN_MBUFPOOL_LEN 0x440C +#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 +#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 +#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 +#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C +#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 +#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 +#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 +#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C +#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 +#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 +#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 +#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C +#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 +#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 +#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 +#define BGE_BMAN_HWDIAG_1 0x444C +#define BGE_BMAN_HWDIAG_2 0x4450 +#define BGE_BMAN_HWDIAG_3 0x4454 + +/* Buffer manager mode register */ +#define BGE_BMANMODE_RESET 0x00000001 +#define BGE_BMANMODE_ENABLE 0x00000002 +#define BGE_BMANMODE_ATTN 0x00000004 +#define BGE_BMANMODE_TESTMODE 0x00000008 +#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 + +/* Buffer manager status register */ +#define BGE_BMANSTAT_ERRO 0x00000004 +#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 + + +/* + * Read DMA Control registers + */ +#define BGE_RDMA_MODE 0x4800 +#define BGE_RDMA_STATUS 0x4804 + +/* Read DMA mode register */ +#define BGE_RDMAMODE_RESET 0x00000001 +#define BGE_RDMAMODE_ENABLE 0x00000002 +#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 +#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 +#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC + +/* Read DMA status register */ +#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 +#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 + +/* + * Write DMA control registers + */ +#define BGE_WDMA_MODE 0x4C00 +#define BGE_WDMA_STATUS 0x4C04 + +/* Write DMA mode register */ +#define BGE_WDMAMODE_RESET 0x00000001 +#define BGE_WDMAMODE_ENABLE 0x00000002 +#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 +#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 +#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC + +/* Write DMA status register */ +#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 +#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 + + +/* + * RX CPU registers + */ +#define BGE_RXCPU_MODE 0x5000 +#define BGE_RXCPU_STATUS 0x5004 +#define BGE_RXCPU_PC 0x501C + +/* RX CPU mode register */ +#define BGE_RXCPUMODE_RESET 0x00000001 +#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 +#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 +#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 +#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 +#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 +#define BGE_RXCPUMODE_ROMFAIL 0x00000040 +#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 +#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 +#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 +#define BGE_RXCPUMODE_HALTCPU 0x00000400 +#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 +#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 +#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 + +/* RX CPU status register */ +#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 +#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 +#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 +#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 +#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 +#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 +#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 +#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 +#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 +#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 +#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 +#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 +#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 +#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 +#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 +#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 +#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 + + +/* + * TX CPU registers + */ +#define BGE_TXCPU_MODE 0x5400 +#define BGE_TXCPU_STATUS 0x5404 +#define BGE_TXCPU_PC 0x541C + +/* TX CPU mode register */ +#define BGE_TXCPUMODE_RESET 0x00000001 +#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 +#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 +#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 +#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 +#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 +#define BGE_TXCPUMODE_ROMFAIL 0x00000040 +#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 +#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 +#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 +#define BGE_TXCPUMODE_HALTCPU 0x00000400 +#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 +#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 + +/* TX CPU status register */ +#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 +#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 +#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 +#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 +#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 +#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 +#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 +#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 +#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 +#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 +#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 +#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 +#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 +#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 +#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 +#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 +#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 + + +/* + * Low priority mailbox registers + */ +#define BGE_LPMBX_IRQ0_HI 0x5800 +#define BGE_LPMBX_IRQ0_LO 0x5804 +#define BGE_LPMBX_IRQ1_HI 0x5808 +#define BGE_LPMBX_IRQ1_LO 0x580C +#define BGE_LPMBX_IRQ2_HI 0x5810 +#define BGE_LPMBX_IRQ2_LO 0x5814 +#define BGE_LPMBX_IRQ3_HI 0x5818 +#define BGE_LPMBX_IRQ3_LO 0x581C +#define BGE_LPMBX_GEN0_HI 0x5820 +#define BGE_LPMBX_GEN0_LO 0x5824 +#define BGE_LPMBX_GEN1_HI 0x5828 +#define BGE_LPMBX_GEN1_LO 0x582C +#define BGE_LPMBX_GEN2_HI 0x5830 +#define BGE_LPMBX_GEN2_LO 0x5834 +#define BGE_LPMBX_GEN3_HI 0x5828 +#define BGE_LPMBX_GEN3_LO 0x582C +#define BGE_LPMBX_GEN4_HI 0x5840 +#define BGE_LPMBX_GEN4_LO 0x5844 +#define BGE_LPMBX_GEN5_HI 0x5848 +#define BGE_LPMBX_GEN5_LO 0x584C +#define BGE_LPMBX_GEN6_HI 0x5850 +#define BGE_LPMBX_GEN6_LO 0x5854 +#define BGE_LPMBX_GEN7_HI 0x5858 +#define BGE_LPMBX_GEN7_LO 0x585C +#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 +#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 +#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 +#define BGE_LPMBX_RX_STD_PROD_LO 0x586C +#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 +#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 +#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 +#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C +#define BGE_LPMBX_RX_CONS0_HI 0x5880 +#define BGE_LPMBX_RX_CONS0_LO 0x5884 +#define BGE_LPMBX_RX_CONS1_HI 0x5888 +#define BGE_LPMBX_RX_CONS1_LO 0x588C +#define BGE_LPMBX_RX_CONS2_HI 0x5890 +#define BGE_LPMBX_RX_CONS2_LO 0x5894 +#define BGE_LPMBX_RX_CONS3_HI 0x5898 +#define BGE_LPMBX_RX_CONS3_LO 0x589C +#define BGE_LPMBX_RX_CONS4_HI 0x58A0 +#define BGE_LPMBX_RX_CONS4_LO 0x58A4 +#define BGE_LPMBX_RX_CONS5_HI 0x58A8 +#define BGE_LPMBX_RX_CONS5_LO 0x58AC +#define BGE_LPMBX_RX_CONS6_HI 0x58B0 +#define BGE_LPMBX_RX_CONS6_LO 0x58B4 +#define BGE_LPMBX_RX_CONS7_HI 0x58B8 +#define BGE_LPMBX_RX_CONS7_LO 0x58BC +#define BGE_LPMBX_RX_CONS8_HI 0x58C0 +#define BGE_LPMBX_RX_CONS8_LO 0x58C4 +#define BGE_LPMBX_RX_CONS9_HI 0x58C8 +#define BGE_LPMBX_RX_CONS9_LO 0x58CC +#define BGE_LPMBX_RX_CONS10_HI 0x58D0 +#define BGE_LPMBX_RX_CONS10_LO 0x58D4 +#define BGE_LPMBX_RX_CONS11_HI 0x58D8 +#define BGE_LPMBX_RX_CONS11_LO 0x58DC +#define BGE_LPMBX_RX_CONS12_HI 0x58E0 +#define BGE_LPMBX_RX_CONS12_LO 0x58E4 +#define BGE_LPMBX_RX_CONS13_HI 0x58E8 +#define BGE_LPMBX_RX_CONS13_LO 0x58EC +#define BGE_LPMBX_RX_CONS14_HI 0x58F0 +#define BGE_LPMBX_RX_CONS14_LO 0x58F4 +#define BGE_LPMBX_RX_CONS15_HI 0x58F8 +#define BGE_LPMBX_RX_CONS15_LO 0x58FC +#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 +#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 +#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 +#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C +#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 +#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 +#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 +#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C +#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 +#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 +#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 +#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C +#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 +#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 +#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 +#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C +#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 +#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 +#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 +#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C +#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 +#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 +#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 +#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C +#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 +#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 +#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 +#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C +#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 +#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 +#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 +#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C +#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 +#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 +#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 +#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C +#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 +#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 +#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 +#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C +#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 +#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 +#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 +#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC +#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 +#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 +#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 +#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC +#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 +#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 +#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 +#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC +#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 +#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 +#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 +#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC +#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 +#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 +#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 +#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC +#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 +#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 +#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 +#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC + +/* + * Flow throw Queue reset register + */ +#define BGE_FTQ_RESET 0x5C00 + +#define BGE_FTQRESET_DMAREAD 0x00000002 +#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 +#define BGE_FTQRESET_DMADONE 0x00000010 +#define BGE_FTQRESET_SBDC 0x00000020 +#define BGE_FTQRESET_SDI 0x00000040 +#define BGE_FTQRESET_WDMA 0x00000080 +#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 +#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 +#define BGE_FTQRESET_SDC 0x00000400 +#define BGE_FTQRESET_HCC 0x00000800 +#define BGE_FTQRESET_TXFIFO 0x00001000 +#define BGE_FTQRESET_MBC 0x00002000 +#define BGE_FTQRESET_RBDC 0x00004000 +#define BGE_FTQRESET_RXLP 0x00008000 +#define BGE_FTQRESET_RDBDI 0x00010000 +#define BGE_FTQRESET_RDC 0x00020000 +#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 + +/* + * Message Signaled Interrupt registers + */ +#define BGE_MSI_MODE 0x6000 +#define BGE_MSI_STATUS 0x6004 +#define BGE_MSI_FIFOACCESS 0x6008 + +/* MSI mode register */ +#define BGE_MSIMODE_RESET 0x00000001 +#define BGE_MSIMODE_ENABLE 0x00000002 +#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 +#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 +#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 + +/* MSI status register */ +#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 +#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 +#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 + + +/* + * DMA Completion registers + */ +#define BGE_DMAC_MODE 0x6400 + +/* DMA Completion mode register */ +#define BGE_DMACMODE_RESET 0x00000001 +#define BGE_DMACMODE_ENABLE 0x00000002 + + +/* + * General control registers. + */ +#define BGE_MODE_CTL 0x6800 +#define BGE_MISC_CFG 0x6804 +#define BGE_MISC_LOCAL_CTL 0x6808 +#define BGE_EE_ADDR 0x6838 +#define BGE_EE_DATA 0x683C +#define BGE_EE_CTL 0x6840 +#define BGE_MDI_CTL 0x6844 +#define BGE_EE_DELAY 0x6848 + +/* Mode control register */ +#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 +#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 +#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 +#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 +#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 +#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 +#define BGE_MODECTL_NO_RX_CRC 0x00000400 +#define BGE_MODECTL_RX_BADFRAMES 0x00000800 +#define BGE_MODECTL_NO_TX_INTR 0x00002000 +#define BGE_MODECTL_NO_RX_INTR 0x00004000 +#define BGE_MODECTL_FORCE_PCI32 0x00008000 +#define BGE_MODECTL_STACKUP 0x00010000 +#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 +#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 +#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 +#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 +#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 +#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 +#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 +#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 +#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 +#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 + +/* Misc. config register */ +#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 +#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE + +#define BGE_32BITTIME_66MHZ (0x41 << 1) + +/* Misc. Local Control */ +#define BGE_MLC_INTR_STATE 0x00000001 +#define BGE_MLC_INTR_CLR 0x00000002 +#define BGE_MLC_INTR_SET 0x00000004 +#define BGE_MLC_INTR_ONATTN 0x00000008 +#define BGE_MLC_MISCIO_IN0 0x00000100 +#define BGE_MLC_MISCIO_IN1 0x00000200 +#define BGE_MLC_MISCIO_IN2 0x00000400 +#define BGE_MLC_MISCIO_OUTEN0 0x00000800 +#define BGE_MLC_MISCIO_OUTEN1 0x00001000 +#define BGE_MLC_MISCIO_OUTEN2 0x00002000 +#define BGE_MLC_MISCIO_OUT0 0x00004000 +#define BGE_MLC_MISCIO_OUT1 0x00008000 +#define BGE_MLC_MISCIO_OUT2 0x00010000 +#define BGE_MLC_EXTRAM_ENB 0x00020000 +#define BGE_MLC_SRAM_SIZE 0x001C0000 +#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ +#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ +#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 +#define BGE_MLC_AUTO_EEPROM 0x01000000 + +#define BGE_SSRAMSIZE_256KB 0x00000000 +#define BGE_SSRAMSIZE_512KB 0x00040000 +#define BGE_SSRAMSIZE_1MB 0x00080000 +#define BGE_SSRAMSIZE_2MB 0x000C0000 +#define BGE_SSRAMSIZE_4MB 0x00100000 +#define BGE_SSRAMSIZE_8MB 0x00140000 +#define BGE_SSRAMSIZE_16M 0x00180000 + +/* EEPROM address register */ +#define BGE_EEADDR_ADDRESS 0x0000FFFC +#define BGE_EEADDR_HALFCLK 0x01FF0000 +#define BGE_EEADDR_START 0x02000000 +#define BGE_EEADDR_DEVID 0x1C000000 +#define BGE_EEADDR_RESET 0x20000000 +#define BGE_EEADDR_DONE 0x40000000 +#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ + +#define BGE_EEDEVID(x) ((x & 7) << 26) +#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) +#define BGE_HALFCLK_384SCL 0x60 +#define BGE_EE_READCMD \ + (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ + BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) +#define BGE_EE_WRCMD \ + (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ + BGE_EEADDR_START|BGE_EEADDR_DONE) + +/* EEPROM Control register */ +#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 +#define BGE_EECTL_CLKOUT 0x00000002 +#define BGE_EECTL_CLKIN 0x00000004 +#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 +#define BGE_EECTL_DATAOUT 0x00000010 +#define BGE_EECTL_DATAIN 0x00000020 + +/* MDI (MII/GMII) access register */ +#define BGE_MDI_DATA 0x00000001 +#define BGE_MDI_DIR 0x00000002 +#define BGE_MDI_SEL 0x00000004 +#define BGE_MDI_CLK 0x00000008 + +#define BGE_MEMWIN_START 0x00008000 +#define BGE_MEMWIN_END 0x0000FFFF + + +#define BGE_MEMWIN_READ(sc, x, val) \ + do { \ + pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ + (0xFFFF0000 & x), 4); \ + val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ + } while(0) + +#define BGE_MEMWIN_WRITE(sc, x, val) \ + do { \ + pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ + (0xFFFF0000 & x), 4); \ + CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ + } while(0) + +/* + * This magic number is used to prevent PXE restart when we + * issue a software reset. We write this magic number to the + * firmware mailbox at 0xB50 in order to prevent the PXE boot + * code from running. + */ +#define BGE_MAGIC_NUMBER 0x4B657654 + +typedef struct { + u_int32_t bge_addr_hi; + u_int32_t bge_addr_lo; +} bge_hostaddr; +#define BGE_HOSTADDR(x) x.bge_addr_lo + +/* Ring control block structure */ +struct bge_rcb { + bge_hostaddr bge_hostaddr; + u_int16_t bge_flags; + u_int16_t bge_max_len; + u_int32_t bge_nicaddr; +}; + +struct bge_rcb_opaque { + u_int32_t bge_reg0; + u_int32_t bge_reg1; + u_int32_t bge_reg2; + u_int32_t bge_reg3; +}; + +#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 +#define BGE_RCB_FLAG_RING_DISABLED 0x0002 + +struct bge_tx_bd { + bge_hostaddr bge_addr; + u_int16_t bge_flags; + u_int16_t bge_len; + u_int16_t bge_vlan_tag; + u_int16_t bge_rsvd; +}; + +#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 +#define BGE_TXBDFLAG_IP_CSUM 0x0002 +#define BGE_TXBDFLAG_END 0x0004 +#define BGE_TXBDFLAG_IP_FRAG 0x0008 +#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 +#define BGE_TXBDFLAG_VLAN_TAG 0x0040 +#define BGE_TXBDFLAG_COAL_NOW 0x0080 +#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 +#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 +#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 +#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 +#define BGE_TXBDFLAG_NO_CRC 0x8000 + +#define BGE_NIC_TXRING_ADDR(ringno, size) \ + BGE_SEND_RING_1_TO_4 + \ + ((ringno * sizeof(struct bge_tx_bd) * size) / 4) + +struct bge_rx_bd { + bge_hostaddr bge_addr; + u_int16_t bge_len; + u_int16_t bge_idx; + u_int16_t bge_flags; + u_int16_t bge_type; + u_int16_t bge_tcp_udp_csum; + u_int16_t bge_ip_csum; + u_int16_t bge_vlan_tag; + u_int16_t bge_error_flag; + u_int32_t bge_rsvd; + u_int32_t bge_opaque; +}; + +#define BGE_RXBDFLAG_END 0x0004 +#define BGE_RXBDFLAG_JUMBO_RING 0x0020 +#define BGE_RXBDFLAG_VLAN_TAG 0x0040 +#define BGE_RXBDFLAG_ERROR 0x0400 +#define BGE_RXBDFLAG_MINI_RING 0x0800 +#define BGE_RXBDFLAG_IP_CSUM 0x1000 +#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 +#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 + +#define BGE_RXERRFLAG_BAD_CRC 0x0001 +#define BGE_RXERRFLAG_COLL_DETECT 0x0002 +#define BGE_RXERRFLAG_LINK_LOST 0x0004 +#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 +#define BGE_RXERRFLAG_MAC_ABORT 0x0010 +#define BGE_RXERRFLAG_RUNT 0x0020 +#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 +#define BGE_RXERRFLAG_GIANT 0x0080 + +struct bge_sts_idx { + u_int16_t bge_rx_prod_idx; + u_int16_t bge_tx_cons_idx; +}; + +struct bge_status_block { + u_int32_t bge_status; + u_int32_t bge_rsvd0; + u_int16_t bge_rx_jumbo_cons_idx; + u_int16_t bge_rx_std_cons_idx; + u_int16_t bge_rx_mini_cons_idx; + u_int16_t bge_rsvd1; + struct bge_sts_idx bge_idx[16]; +}; + +#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx +#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx + +#define BGE_STATFLAG_UPDATED 0x00000001 +#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 +#define BGE_STATFLAG_ERROR 0x00000004 + + +/* + * Broadcom Vendor ID + * (Note: the BCM570x still defaults to the Alteon PCI vendor ID + * even though they're now manufactured by Broadcom) + */ +#define BCOM_VENDORID 0x14E4 +#define BCOM_DEVICEID_BCM5700 0x1644 +#define BCOM_DEVICEID_BCM5701 0x1645 + +/* + * Alteon AceNIC PCI vendor/device ID. + */ +#define ALT_VENDORID 0x12AE +#define ALT_DEVICEID_ACENIC 0x0001 +#define ALT_DEVICEID_ACENIC_COPPER 0x0002 +#define ALT_DEVICEID_BCM5700 0x0003 +#define ALT_DEVICEID_BCM5701 0x0004 + +/* + * 3Com 3c985 PCI vendor/device ID. + */ +#define TC_VENDORID 0x10B7 +#define TC_DEVICEID_3C985 0x0001 +#define TC_DEVICEID_3C996 0x0003 + +/* + * SysKonnect PCI vendor ID + */ +#define SK_VENDORID 0x1148 +#define SK_DEVICEID_ALTIMA 0x4400 +#define SK_SUBSYSID_9D21 0x4421 +#define SK_SUBSYSID_9D41 0x4441 + +/* + * Offset of MAC address inside EEPROM. + */ +#define BGE_EE_MAC_OFFSET 0x7C +#define BGE_EE_HWCFG_OFFSET 0xC8 + +#define BGE_PCI_READ_CMD 0x06000000 +#define BGE_PCI_WRITE_CMD 0x70000000 + +#define BGE_TICKS_PER_SEC 1000000 + +/* + * Ring size constants. + */ +#define BGE_EVENT_RING_CNT 256 +#define BGE_CMD_RING_CNT 64 +#define BGE_STD_RX_RING_CNT 512 +#define BGE_JUMBO_RX_RING_CNT 256 +#define BGE_MINI_RX_RING_CNT 1024 +#define BGE_RETURN_RING_CNT 1024 + +/* + * Possible TX ring sizes. + */ +#define BGE_TX_RING_CNT_128 128 +#define BGE_TX_RING_BASE_128 0x3800 + +#define BGE_TX_RING_CNT_256 256 +#define BGE_TX_RING_BASE_256 0x3000 + +#define BGE_TX_RING_CNT_512 512 +#define BGE_TX_RING_BASE_512 0x2000 + +#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 +#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 + +/* + * Tigon III statistics counters. + */ +struct bge_stats { + u_int8_t Reserved0[256]; + + /* Statistics maintained by Receive MAC. */ + bge_hostaddr ifHCInOctets; + bge_hostaddr Reserved1; + bge_hostaddr etherStatsFragments; + bge_hostaddr ifHCInUcastPkts; + bge_hostaddr ifHCInMulticastPkts; + bge_hostaddr ifHCInBroadcastPkts; + bge_hostaddr dot3StatsFCSErrors; + bge_hostaddr dot3StatsAlignmentErrors; + bge_hostaddr xonPauseFramesReceived; + bge_hostaddr xoffPauseFramesReceived; + bge_hostaddr macControlFramesReceived; + bge_hostaddr xoffStateEntered; + bge_hostaddr dot3StatsFramesTooLong; + bge_hostaddr etherStatsJabbers; + bge_hostaddr etherStatsUndersizePkts; + bge_hostaddr inRangeLengthError; + bge_hostaddr outRangeLengthError; + bge_hostaddr etherStatsPkts64Octets; + bge_hostaddr etherStatsPkts65Octetsto127Octets; + bge_hostaddr etherStatsPkts128Octetsto255Octets; + bge_hostaddr etherStatsPkts256Octetsto511Octets; + bge_hostaddr etherStatsPkts512Octetsto1023Octets; + bge_hostaddr etherStatsPkts1024Octetsto1522Octets; + bge_hostaddr etherStatsPkts1523Octetsto2047Octets; + bge_hostaddr etherStatsPkts2048Octetsto4095Octets; + bge_hostaddr etherStatsPkts4096Octetsto8191Octets; + bge_hostaddr etherStatsPkts8192Octetsto9022Octets; + + bge_hostaddr Unused1[37]; + + /* Statistics maintained by Transmit MAC. */ + bge_hostaddr ifHCOutOctets; + bge_hostaddr Reserved2; + bge_hostaddr etherStatsCollisions; + bge_hostaddr outXonSent; + bge_hostaddr outXoffSent; + bge_hostaddr flowControlDone; + bge_hostaddr dot3StatsInternalMacTransmitErrors; + bge_hostaddr dot3StatsSingleCollisionFrames; + bge_hostaddr dot3StatsMultipleCollisionFrames; + bge_hostaddr dot3StatsDeferredTransmissions; + bge_hostaddr Reserved3; + bge_hostaddr dot3StatsExcessiveCollisions; + bge_hostaddr dot3StatsLateCollisions; + bge_hostaddr dot3Collided2Times; + bge_hostaddr dot3Collided3Times; + bge_hostaddr dot3Collided4Times; + bge_hostaddr dot3Collided5Times; + bge_hostaddr dot3Collided6Times; + bge_hostaddr dot3Collided7Times; + bge_hostaddr dot3Collided8Times; + bge_hostaddr dot3Collided9Times; + bge_hostaddr dot3Collided10Times; + bge_hostaddr dot3Collided11Times; + bge_hostaddr dot3Collided12Times; + bge_hostaddr dot3Collided13Times; + bge_hostaddr dot3Collided14Times; + bge_hostaddr dot3Collided15Times; + bge_hostaddr ifHCOutUcastPkts; + bge_hostaddr ifHCOutMulticastPkts; + bge_hostaddr ifHCOutBroadcastPkts; + bge_hostaddr dot3StatsCarrierSenseErrors; + bge_hostaddr ifOutDiscards; + bge_hostaddr ifOutErrors; + + bge_hostaddr Unused2[31]; + + /* Statistics maintained by Receive List Placement. */ + bge_hostaddr COSIfHCInPkts[16]; + bge_hostaddr COSFramesDroppedDueToFilters; + bge_hostaddr nicDmaWriteQueueFull; + bge_hostaddr nicDmaWriteHighPriQueueFull; + bge_hostaddr nicNoMoreRxBDs; + bge_hostaddr ifInDiscards; + bge_hostaddr ifInErrors; + bge_hostaddr nicRecvThresholdHit; + + bge_hostaddr Unused3[9]; + + /* Statistics maintained by Send Data Initiator. */ + bge_hostaddr COSIfHCOutPkts[16]; + bge_hostaddr nicDmaReadQueueFull; + bge_hostaddr nicDmaReadHighPriQueueFull; + bge_hostaddr nicSendDataCompQueueFull; + + /* Statistics maintained by Host Coalescing. */ + bge_hostaddr nicRingSetSendProdIndex; + bge_hostaddr nicRingStatusUpdate; + bge_hostaddr nicInterrupts; + bge_hostaddr nicAvoidedInterrupts; + bge_hostaddr nicSendThresholdHit; + + u_int8_t Reserved4[320]; +}; + +/* + * Tigon general information block. This resides in host memory + * and contains the status counters, ring control blocks and + * producer pointers. + */ + +struct bge_gib { + struct bge_stats bge_stats; + struct bge_rcb bge_tx_rcb[16]; + struct bge_rcb bge_std_rx_rcb; + struct bge_rcb bge_jumbo_rx_rcb; + struct bge_rcb bge_mini_rx_rcb; + struct bge_rcb bge_return_rcb; +}; + +/* + * NOTE! On the Alpha, we have an alignment constraint. + * The first thing in the packet is a 14-byte Ethernet header. + * This means that the packet is misaligned. To compensate, + * we actually offset the data 2 bytes into the cluster. This + * alignes the packet after the Ethernet header at a 32-bit + * boundary. + */ + +#define ETHER_ALIGN 2 + +#define BGE_FRAMELEN 1518 +#define BGE_MAX_FRAMELEN 1536 +#define BGE_JUMBO_FRAMELEN 9018 +#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) +#define BGE_PAGE_SIZE PAGE_SIZE +#define BGE_MIN_FRAMELEN 60 + +/* + * Other utility macros. + */ +#define BGE_INC(x, y) (x) = (x + 1) % y + +/* + * Vital product data and structures. + */ +#define BGE_VPD_FLAG 0x8000 + +/* VPD structures */ +struct vpd_res { + u_int8_t vr_id; + u_int8_t vr_len; + u_int8_t vr_pad; +}; + +struct vpd_key { + char vk_key[2]; + u_int8_t vk_len; +}; + +#define VPD_RES_ID 0x82 /* ID string */ +#define VPD_RES_READ 0x90 /* start of read only area */ +#define VPD_RES_WRITE 0x81 /* start of read/write area */ +#define VPD_RES_END 0x78 /* end tag */ + + +/* + * Register access macros. The Tigon always uses memory mapped register + * accesses and all registers must be accessed with 32 bit operations. + */ + +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) + +#define CSR_READ_4(sc, reg) \ + bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) + +#define BGE_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) +#define BGE_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) + +#define PCI_SETBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s) +#define PCI_CLRBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s) + +/* + * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS + * values are tuneable. They control the actual amount of buffers + * allocated for the standard, mini and jumbo receive rings. + */ + +#define BGE_SSLOTS 256 +#define BGE_MSLOTS 256 +#define BGE_JSLOTS 384 + +#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) +#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ + (BGE_JRAWLEN % sizeof(u_int64_t)))) +#define BGE_JPAGESZ PAGE_SIZE +#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) +#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) + +/* + * Ring structures. Most of these reside in host memory and we tell + * the NIC where they are via the ring control blocks. The exceptions + * are the tx and command rings, which live in NIC memory and which + * we access via the shared memory window. + */ +struct bge_ring_data { + struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; + struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; + struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; + struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; + struct bge_status_block bge_status_block; + struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ + struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ + struct bge_gib bge_info; +}; + +/* + * Mbuf pointers. We need these to keep track of the virtual addresses + * of our mbuf chains since we can only convert from physical to virtual, + * not the other way around. + */ +struct bge_chain_data { + struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; + struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; + struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; + struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; + /* Stick the jumbo mem management stuff here too. */ + caddr_t bge_jslots[BGE_JSLOTS]; + void *bge_jumbo_buf; +}; + +struct bge_type { + u_int16_t bge_vid; + u_int16_t bge_did; + char *bge_name; +}; + +#define BGE_HWREV_TIGON 0x01 +#define BGE_HWREV_TIGON_II 0x02 +#define BGE_TIMEOUT 1000 +#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ + +struct bge_jpool_entry { + int slot; + SLIST_ENTRY(bge_jpool_entry) jpool_entries; +}; + +struct bge_bcom_hack { + int reg; + int val; +}; + +struct bge_softc { + struct arpcom arpcom; /* interface info */ + device_t bge_dev; + device_t bge_miibus; + bus_space_handle_t bge_bhandle; + vm_offset_t bge_vhandle; + bus_space_tag_t bge_btag; + void *bge_intrhand; + struct resource *bge_irq; + struct resource *bge_res; + struct ifmedia bge_ifmedia; /* TBI media info */ + u_int8_t bge_unit; /* interface number */ + u_int8_t bge_extram; /* has external SSRAM */ + u_int8_t bge_tbi; + struct bge_ring_data *bge_rdata; /* rings */ + struct bge_chain_data bge_cdata; /* mbufs */ + u_int16_t bge_tx_saved_considx; + u_int16_t bge_rx_saved_considx; + u_int16_t bge_ev_saved_considx; + u_int16_t bge_std; /* current std ring head */ + u_int16_t bge_jumbo; /* current jumo ring head */ + SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; + SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; + u_int32_t bge_stat_ticks; + u_int32_t bge_rx_coal_ticks; + u_int32_t bge_tx_coal_ticks; + u_int32_t bge_rx_max_coal_bds; + u_int32_t bge_tx_max_coal_bds; + u_int32_t bge_tx_buf_ratio; + int bge_if_flags; + int bge_txcnt; + int bge_link; + struct callout_handle bge_stat_ch; + char *bge_vpd_prodname; + char *bge_vpd_readonly; +}; + +#ifdef __alpha__ +#undef vtophys +#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) +#endif diff --git a/sys/i386/conf/NOTES b/sys/i386/conf/NOTES index 60e29be6795a..ae3e901214d2 100644 --- a/sys/i386/conf/NOTES +++ b/sys/i386/conf/NOTES @@ -1665,6 +1665,10 @@ device miibus # (requires sppp) # awi: Support for IEEE 802.11 PC Card devices using the AMD Am79C930 and # Harris (Intersil) Chipset with PCnetMobile firmware by AMD. +# bge: Support for gigabit ethernet adapters based on the Broadcom +# BCM570x familiy of controllers, including the 3Com 3c996-T, +# the SysKonnect SK-9D21 and SK-9D41, and the embedded gigE NICs +# on Dell PowerEdge 2550 servers. # cnw: Xircom CNW/Netware Airsurfer PC Card adapter # cs: IBM Etherjet and other Crystal Semi CS89x0-based adapters # cx: Cronyx/Sigma multiport sync/async (with Cisco or PPP framing) @@ -1872,9 +1876,11 @@ device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'') # PCI Ethernet NICs. device de # DEC/Intel DC21x4x (``Tulip'') +device txp # 3Com 3cR990 (``Typhoon'') device vx # 3Com 3c590, 3c595 (``Vortex'') # PCI Gigabit & FDDI NICs. +device bge device lge device nge device sk diff --git a/sys/modules/Makefile b/sys/modules/Makefile index f7ef8f94b4e7..d6d4680d6b9e 100644 --- a/sys/modules/Makefile +++ b/sys/modules/Makefile @@ -12,6 +12,7 @@ SUBDIR= 3dfx \ amr \ an \ aue \ + bge \ cam \ ccd \ cd9660 \ diff --git a/sys/modules/bge/Makefile b/sys/modules/bge/Makefile new file mode 100644 index 000000000000..6c51eb253deb --- /dev/null +++ b/sys/modules/bge/Makefile @@ -0,0 +1,8 @@ +# $FreeBSD$ + +.PATH: ${.CURDIR}/../../dev/bge + +KMOD= if_bge +SRCS= if_bge.c miibus_if.h opt_bdg.h device_if.h bus_if.h pci_if.h + +.include diff --git a/usr.sbin/sade/devices.c b/usr.sbin/sade/devices.c index 2366277d48bf..30993760b192 100644 --- a/usr.sbin/sade/devices.c +++ b/usr.sbin/sade/devices.c @@ -82,6 +82,7 @@ static struct _devname { { DEVICE_TYPE_DISK, "aacd%d", "Adaptec FSA RAID array", 151, 65538, 8, 4 }, { DEVICE_TYPE_FLOPPY, "fd%d", "floppy drive unit A", 9, 0, 64, 4 }, { DEVICE_TYPE_NETWORK, "aue", "ADMtek USB ethernet adapter" }, + { DEVICE_TYPE_NETWORK, "bge", "Broadcom BCM570x PCI gigabit ethernet card" }, { DEVICE_TYPE_NETWORK, "cue", "CATC USB ethernet adapter" }, { DEVICE_TYPE_NETWORK, "fpa", "DEC DEFPA PCI FDDI card" }, { DEVICE_TYPE_NETWORK, "sr", "SDL T1/E1 sync serial PCI card" }, diff --git a/usr.sbin/sysinstall/devices.c b/usr.sbin/sysinstall/devices.c index 2366277d48bf..30993760b192 100644 --- a/usr.sbin/sysinstall/devices.c +++ b/usr.sbin/sysinstall/devices.c @@ -82,6 +82,7 @@ static struct _devname { { DEVICE_TYPE_DISK, "aacd%d", "Adaptec FSA RAID array", 151, 65538, 8, 4 }, { DEVICE_TYPE_FLOPPY, "fd%d", "floppy drive unit A", 9, 0, 64, 4 }, { DEVICE_TYPE_NETWORK, "aue", "ADMtek USB ethernet adapter" }, + { DEVICE_TYPE_NETWORK, "bge", "Broadcom BCM570x PCI gigabit ethernet card" }, { DEVICE_TYPE_NETWORK, "cue", "CATC USB ethernet adapter" }, { DEVICE_TYPE_NETWORK, "fpa", "DEC DEFPA PCI FDDI card" }, { DEVICE_TYPE_NETWORK, "sr", "SDL T1/E1 sync serial PCI card" },