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cxgbe(4): Update the T4, T5, and T6 firmwares to 1.16.45.0.

Browse Source 
The latest firmware has a number of link related fixes, support for a
new custom card, and the fix for a bug that affected rate limiting on
FreeBSD.

Obtained from:	Chelsio Communications
MFC after:	1 week
Sponsored by:	Chelsio Communications
This commit is contained in:
np 2017-05-23 23:40:17 +00:00
parent 5387dbf595
commit 95e69f2666
14 changed files with 32101 additions and 29344 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
sys/conf/files
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@ -1376,7 +1376,7 @@ t4fw.fwo optional cxgbe \
no-implicit-rule \
clean "t4fw.fwo"
t4fw.fw optional cxgbe \
dependency "$S/dev/cxgbe/firmware/t4fw-1.16.26.0.bin.uu" \
dependency "$S/dev/cxgbe/firmware/t4fw-1.16.45.0.bin.uu" \
compile-with "${NORMAL_FW}" \
no-obj no-implicit-rule \
clean "t4fw.fw"
@ -1400,7 +1400,7 @@ t5fw.fwo optional cxgbe \
no-implicit-rule \
clean "t5fw.fwo"
t5fw.fw optional cxgbe \
dependency "$S/dev/cxgbe/firmware/t5fw-1.16.26.0.bin.uu" \
dependency "$S/dev/cxgbe/firmware/t5fw-1.16.45.0.bin.uu" \
compile-with "${NORMAL_FW}" \
no-obj no-implicit-rule \
clean "t5fw.fw"
@ -1424,7 +1424,7 @@ t6fw.fwo optional cxgbe \
no-implicit-rule \
clean "t6fw.fwo"
t6fw.fw optional cxgbe \
dependency "$S/dev/cxgbe/firmware/t6fw-1.16.26.0.bin.uu" \
dependency "$S/dev/cxgbe/firmware/t6fw-1.16.45.0.bin.uu" \
compile-with "${NORMAL_FW}" \
no-obj no-implicit-rule \
clean "t6fw.fw"

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sys/dev/cxgbe/firmware/t4fw-1.16.26.0.bin.uu
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sys/dev/cxgbe/firmware/t4fw-1.16.45.0.bin.uu Normal file
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6
sys/dev/cxgbe/firmware/t4fw_cfg_uwire.txt
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@ -1,6 +1,6 @@
# Chelsio T4 Factory Default configuration file.
#
# Copyright (C) 2010-2014 Chelsio Communications. All rights reserved.
# Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
#
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF
# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
@ -550,8 +550,8 @@
dcb_app_tlv[2] = 3260, socketnum, 5
[fini]
version = 0x1425001c
checksum = 0x5ceab41e
version = 0x01000028
checksum = 0x5ceab421
# Total resources used by above allocations:
# Virtual Interfaces: 104

150
sys/dev/cxgbe/firmware/t4fw_interface.h
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@ -1,5 +1,5 @@
/*-
* Copyright (c) 2012-2016 Chelsio Communications, Inc.
* Copyright (c) 2012-2017 Chelsio Communications, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -100,6 +100,7 @@ enum fw_wr_opcodes {
FW_ETH_TX_PKT_WR = 0x08,
FW_ETH_TX_PKT2_WR = 0x44,
FW_ETH_TX_PKTS_WR = 0x09,
FW_ETH_TX_PKTS2_WR = 0x78,
FW_ETH_TX_EO_WR = 0x1c,
FW_EQ_FLUSH_WR = 0x1b,
FW_OFLD_CONNECTION_WR = 0x2f,
@ -144,6 +145,7 @@ enum fw_wr_opcodes {
FW_COiSCSI_TGT_XMIT_WR = 0x72,
FW_ISNS_WR = 0x75,
FW_ISNS_XMIT_WR = 0x76,
FW_FILTER2_WR = 0x77,
FW_LASTC2E_WR = 0x80
};
@ -301,6 +303,17 @@ enum fw_filter_wr_cookie {
FW_FILTER_WR_EINVAL,
};
enum fw_filter_wr_nat_mode {
FW_FILTER_WR_NATMODE_NONE = 0,
FW_FILTER_WR_NATMODE_DIP ,
FW_FILTER_WR_NATMODE_DIPDP,
FW_FILTER_WR_NATMODE_DIPDPSIP,
FW_FILTER_WR_NATMODE_DIPDPSP,
FW_FILTER_WR_NATMODE_SIPSP,
FW_FILTER_WR_NATMODE_DIPSIPSP,
FW_FILTER_WR_NATMODE_FOURTUPLE,
};
struct fw_filter_wr {
__be32 op_pkd;
__be32 len16_pkd;
@ -333,6 +346,51 @@ struct fw_filter_wr {
__u8 sma[6];
};
struct fw_filter2_wr {
__be32 op_pkd;
__be32 len16_pkd;
__be64 r3;
__be32 tid_to_iq;
__be32 del_filter_to_l2tix;
__be16 ethtype;
__be16 ethtypem;
__u8 frag_to_ovlan_vldm;
__u8 smac_sel;
__be16 rx_chan_rx_rpl_iq;
__be32 maci_to_matchtypem;
__u8 ptcl;
__u8 ptclm;
__u8 ttyp;
__u8 ttypm;
__be16 ivlan;
__be16 ivlanm;
__be16 ovlan;
__be16 ovlanm;
__u8 lip[16];
__u8 lipm[16];
__u8 fip[16];
__u8 fipm[16];
__be16 lp;
__be16 lpm;
__be16 fp;
__be16 fpm;
__be16 r7;
__u8 sma[6];
__u8 r8_hi[2];
__u8 filter_type_swapmac;
__u8 natmode_to_ulp_type;
__be16 newlport;
__be16 newfport;
__u8 newlip[16];
__u8 newfip[16];
__be32 natseqcheck;
__be32 dip_hit_vni;
__be64 r10;
__be64 r11;
__be64 r12;
__be64 r13;
};
#define S_FW_FILTER_WR_TID 12
#define M_FW_FILTER_WR_TID 0xfffff
#define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
@ -517,6 +575,52 @@ struct fw_filter_wr {
#define G_FW_FILTER_WR_RX_RPL_IQ(x) \
(((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
#define S_FW_FILTER2_WR_FILTER_TYPE 1
#define M_FW_FILTER2_WR_FILTER_TYPE 0x1
#define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE)
#define G_FW_FILTER2_WR_FILTER_TYPE(x) \
(((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE)
#define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U)
#define S_FW_FILTER2_WR_SWAPMAC 0
#define M_FW_FILTER2_WR_SWAPMAC 0x1
#define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
#define G_FW_FILTER2_WR_SWAPMAC(x) \
(((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC)
#define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U)
#define S_FW_FILTER2_WR_NATMODE 5
#define M_FW_FILTER2_WR_NATMODE 0x7
#define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
#define G_FW_FILTER2_WR_NATMODE(x) \
(((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE)
#define S_FW_FILTER2_WR_NATFLAGCHECK 4
#define M_FW_FILTER2_WR_NATFLAGCHECK 0x1
#define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK)
#define G_FW_FILTER2_WR_NATFLAGCHECK(x) \
(((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK)
#define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U)
#define S_FW_FILTER2_WR_ULP_TYPE 0
#define M_FW_FILTER2_WR_ULP_TYPE 0xf
#define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
#define G_FW_FILTER2_WR_ULP_TYPE(x) \
(((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE)
#define S_FW_FILTER2_WR_DIP_HIT 24
#define M_FW_FILTER2_WR_DIP_HIT 0x1
#define V_FW_FILTER2_WR_DIP_HIT(x) ((x) << S_FW_FILTER2_WR_DIP_HIT)
#define G_FW_FILTER2_WR_DIP_HIT(x) \
(((x) >> S_FW_FILTER2_WR_DIP_HIT) & M_FW_FILTER2_WR_DIP_HIT)
#define F_FW_FILTER2_WR_DIP_HIT V_FW_FILTER2_WR_DIP_HIT(1U)
#define S_FW_FILTER2_WR_VNI 0
#define M_FW_FILTER2_WR_VNI 0xffffff
#define V_FW_FILTER2_WR_VNI(x) ((x) << S_FW_FILTER2_WR_VNI)
#define G_FW_FILTER2_WR_VNI(x) \
(((x) >> S_FW_FILTER2_WR_VNI) & M_FW_FILTER2_WR_VNI)
#define S_FW_FILTER_WR_MACI 23
#define M_FW_FILTER_WR_MACI 0x1ff
#define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
@ -1447,6 +1551,12 @@ struct fw_ri_res_wr {
#endif
};
#define S_FW_RI_RES_WR_VFN 8
#define M_FW_RI_RES_WR_VFN 0xff
#define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN)
#define G_FW_RI_RES_WR_VFN(x) \
(((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN)
#define S_FW_RI_RES_WR_NRES 0
#define M_FW_RI_RES_WR_NRES 0xff
#define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES)
@ -4689,6 +4799,10 @@ enum fw_params_param_dev {
FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E,
FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F,
};
/*
@ -4776,6 +4890,7 @@ enum fw_params_param_pfvf {
FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38,
FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
};
/*
@ -4867,6 +4982,22 @@ enum fw_params_param_chnet_flags {
#define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
(((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST)
#define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29
#define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7
#define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \
((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
#define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \
(((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \
M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
#define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0
#define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff
#define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \
((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
#define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \
(((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \
M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
struct fw_params_cmd {
__be32 op_to_vfn;
__be32 retval_len16;
@ -4992,7 +5123,8 @@ struct fw_pfvf_cmd {
*/
enum fw_iq_type {
FW_IQ_TYPE_FL_INT_CAP,
FW_IQ_TYPE_NO_FL_INT_CAP
FW_IQ_TYPE_NO_FL_INT_CAP,
FW_IQ_TYPE_VF_CQ
};
struct fw_iq_cmd {
@ -7247,12 +7379,12 @@ enum fw_port_type {
FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G, Backplane */
FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G */
FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G */
FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G using Backplane */
FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
};
@ -9314,17 +9446,17 @@ enum fw_hdr_chip {
enum {
T4FW_VERSION_MAJOR = 0x01,
T4FW_VERSION_MINOR = 0x10,
T4FW_VERSION_MICRO = 0x1a,
T4FW_VERSION_MICRO = 0x2d,
T4FW_VERSION_BUILD = 0x00,
T5FW_VERSION_MAJOR = 0x01,
T5FW_VERSION_MINOR = 0x10,
T5FW_VERSION_MICRO = 0x1a,
T5FW_VERSION_MICRO = 0x2d,
T5FW_VERSION_BUILD = 0x00,
T6FW_VERSION_MAJOR = 0x01,
T6FW_VERSION_MINOR = 0x10,
T6FW_VERSION_MICRO = 0x1a,
T6FW_VERSION_MICRO = 0x2d,
T6FW_VERSION_BUILD = 0x00,
};

10681
sys/dev/cxgbe/firmware/t5fw-1.16.26.0.bin.uu
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30
sys/dev/cxgbe/firmware/t5fw_cfg_uwire.txt
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@ -1,6 +1,6 @@
# Chelsio T5 Factory Default configuration file.
#
# Copyright (C) 2010-2016 Chelsio Communications. All rights reserved.
# Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
#
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
@ -494,9 +494,9 @@
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
niqflint = 6 # 2 "Queue Sets" + NXIQ
nethctrl = 4 # 2 "Queue Sets"
neq = 8 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x1 # access to only one port ...
@ -506,9 +506,9 @@
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
niqflint = 6 # 2 "Queue Sets" + NXIQ
nethctrl = 4 # 2 "Queue Sets"
neq = 8 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x2 # access to only one port ...
@ -518,9 +518,9 @@
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
niqflint = 6 # 2 "Queue Sets" + NXIQ
nethctrl = 4 # 2 "Queue Sets"
neq = 8 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x4 # access to only one port ...
@ -530,9 +530,9 @@
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
niqflint = 6 # 2 "Queue Sets" + NXIQ
nethctrl = 4 # 2 "Queue Sets"
neq = 8 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x8 # access to only one port ...
@ -601,8 +601,8 @@
[fini]
version = 0x01000025
checksum = 0x2e1a8474
version = 0x01000028
checksum = 0x36228c7d
# Total resources used by above allocations:
# Virtual Interfaces: 104

9001
sys/dev/cxgbe/firmware/t6fw-1.16.26.0.bin.uu
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sys/dev/cxgbe/firmware/t6fw-1.16.45.0.bin.uu Normal file
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46
sys/dev/cxgbe/firmware/t6fw_cfg_uwire.txt
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@ -1,6 +1,6 @@
# Chelsio T6 Factory Default configuration file.
#
# Copyright (C) 2014-2016 Chelsio Communications. All rights reserved.
# Copyright (C) 2014-2017 Chelsio Communications. All rights reserved.
#
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
@ -79,7 +79,7 @@
# The firmware will convert these values to Core Clock Ticks when
# it processes the configuration parameters.
#
reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
reg[0x1008] = 0x40800/0x21c70 # SGE_CONTROL
reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
@ -109,10 +109,10 @@
# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
# protocol, tos, vlan, vnic_id, port, fcoe
# valid filterModes are described the Terminator 5 Data Book
filterMode = srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
# filter tuples enforced in LE active region (equal to or subset of filterMode)
filterMask = protocol
filterMask = protocol, fcoe
# Percentage of dynamic memory (in either the EDRAM or external MEM)
# to use for TP RX payload
@ -390,7 +390,7 @@
r_caps = all # read permissions for all commands
nvi = 28 # NVI_UNIFIED
niqflint = 202 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32)
nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD
nethctrl = 116 # NETHCTRL_UNIFIED + NETHCTRL_WD + ncrypto_lookaside
neq = 256 # NEQ_UNIFIED + NEQ_WD
nqpcq = 12288
nexactf = 40 # NMPSTCAM_UNIFIED
@ -403,7 +403,7 @@
nfilter = 496 # number of filter region entries
nserver = 496 # number of server region entries
nhash = 12288 # number of hash region entries
nhpfilter = 0 # number of high priority filter region entries
nhpfilter = 64 # number of high priority filter region entries
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside
tp_l2t = 3072
tp_ddp = 2
@ -486,9 +486,9 @@
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
niqflint = 6 # 2 "Queue Sets" + NXIQ
nethctrl = 4 # 2 "Queue Sets"
neq = 8 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x1 # access to only one port ...
@ -498,9 +498,9 @@
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
niqflint = 6 # 2 "Queue Sets" + NXIQ
nethctrl = 4 # 2 "Queue Sets"
neq = 8 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x2 # access to only one port ...
@ -509,9 +509,9 @@
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
niqflint = 6 # 2 "Queue Sets" + NXIQ
nethctrl = 4 # 2 "Queue Sets"
neq = 8 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x1 # access to only one port ...
@ -521,9 +521,9 @@
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
niqflint = 6 # 2 "Queue Sets" + NXIQ
nethctrl = 4 # 2 "Queue Sets"
neq = 8 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x2 # access to only one port ...
@ -552,9 +552,6 @@
dcb_app_tlv[0] = 0x8906, ethertype, 3
dcb_app_tlv[1] = 0x8914, ethertype, 3
dcb_app_tlv[2] = 3260, socketnum, 5
#aec_retry_cnt = 4
flags = an_dis
[port "1"]
dcb = ppp, dcbx
@ -566,13 +563,10 @@
dcb_app_tlv[0] = 0x8906, ethertype, 3
dcb_app_tlv[1] = 0x8914, ethertype, 3
dcb_app_tlv[2] = 3260, socketnum, 5
#aec_retry_cnt = 4
flags = an_dis
[fini]
version = 0x01000025
checksum = 0xb23e8983
version = 0x01000028
checksum = 0x4f820cc6
# Total resources used by above allocations:
# Virtual Interfaces: 104

2
sys/modules/cxgbe/t4_firmware/Makefile
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@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
.endif
.endfor
T4FW_VER= 1.16.26.0
T4FW_VER= 1.16.45.0
FIRMWS+= t4fw.fw:t4fw:${T4FW_VER}
CLEANFILES+= t4fw.fw

2
sys/modules/cxgbe/t5_firmware/Makefile
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@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
.endif
.endfor
T5FW_VER= 1.16.26.0
T5FW_VER= 1.16.45.0
FIRMWS+= t5fw.fw:t5fw:${T5FW_VER}
CLEANFILES+= t5fw.fw

2
sys/modules/cxgbe/t6_firmware/Makefile
View File

@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
.endif
.endfor
T6FW_VER= 1.16.26.0
T6FW_VER= 1.16.45.0
FIRMWS+= t6fw.fw:t6fw:${T6FW_VER}
CLEANFILES+= t6fw.fw