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XLR/XLS hardware interrupts should be programmed level triggered at the

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PIC.  This should fix the interrupt releated issues seen after the
interrupt handling re-write for SMP.
This commit is contained in:
Jayachandran C. 2010-09-06 06:18:49 +00:00
parent 1dc7e010ec
commit 96001a35e1
3 changed files with 12 additions and 15 deletions
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8
sys/mips/rmi/iodi.c
View File

@ -104,7 +104,7 @@ iodi_setup_intr(device_t dev, device_t child,
/* FIXME uart 1? */
cpu_establish_hardintr("uart", filt, intr, arg,
PIC_UART_0_IRQ, flags, cookiep);
pic_setup_intr(PIC_IRT_UART_0_INDEX, PIC_UART_0_IRQ, 0x1, 0);
pic_setup_intr(PIC_IRT_UART_0_INDEX, PIC_UART_0_IRQ, 0x1, 1);
} else if (strcmp(name, "rge") == 0 || strcmp(name, "nlge") == 0) {
int irq;
@ -112,15 +112,15 @@ iodi_setup_intr(device_t dev, device_t child,
irq = (intptr_t)ires->__r_i;
cpu_establish_hardintr("rge", filt, intr, arg, irq, flags,
cookiep);
pic_setup_intr(irq - PIC_IRQ_BASE, irq, 0x1, 0);
pic_setup_intr(irq - PIC_IRQ_BASE, irq, 0x1, 1);
} else if (strcmp(name, "ehci") == 0) {
cpu_establish_hardintr("ehci", filt, intr, arg, PIC_USB_IRQ, flags,
cookiep);
pic_setup_intr(PIC_USB_IRQ - PIC_IRQ_BASE, PIC_USB_IRQ, 0x1, 0);
pic_setup_intr(PIC_USB_IRQ - PIC_IRQ_BASE, PIC_USB_IRQ, 0x1, 1);
} else if (strcmp(name, "ata") == 0) {
xlr_establish_intr("ata", filt, intr, arg, PIC_PCMCIA_IRQ, flags,
cookiep, bridge_pcmcia_ack);
pic_setup_intr(PIC_PCMCIA_IRQ - PIC_IRQ_BASE, PIC_PCMCIA_IRQ, 0x1, 0);
pic_setup_intr(PIC_PCMCIA_IRQ - PIC_IRQ_BASE, PIC_PCMCIA_IRQ, 0x1, 1);
}
return (0);
}

15
sys/mips/rmi/xlr_machdep.c
View File

@ -297,7 +297,7 @@ xlr_pic_init(void)
2000, /* quality (adjusted in code) */
};
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
int i, level, irq;
int i, irq;
write_c0_eimr64(0ULL);
mtx_init(&xlr_pic_lock, "pic", NULL, MTX_SPIN);
@ -306,17 +306,14 @@ xlr_pic_init(void)
/* Initialize all IRT entries */
for (i = 0; i < PIC_NUM_IRTS; i++) {
irq = PIC_INTR_TO_IRQ(i);
level = PIC_IS_EDGE_TRIGGERED(i);
/* Bind all PIC irqs to cpu 0 */
xlr_write_reg(mmio, PIC_IRT_0(i), 0x01);
/*
* Use local scheduling and high polarity for all IRTs
* Invalidate all IRTs, by default
* Disable all IRTs. Set defaults (local scheduling, high
* polarity, level * triggered, and CPU irq)
*/
xlr_write_reg(mmio, PIC_IRT_1(i), (level << 30) | (1 << 6) |
irq);
xlr_write_reg(mmio, PIC_IRT_1(i), (1 << 30) | (1 << 6) | irq);
/* Bind all PIC irqs to cpu 0 */
xlr_write_reg(mmio, PIC_IRT_0(i), 0x01);
}
/* Setup timer 7 of PIC as a timestamp, no interrupts */

4
sys/mips/rmi/xlr_pci.c
View File

@ -461,11 +461,11 @@ mips_platform_pci_setup_intr(device_t dev, device_t child,
if (xlr_board_info.is_xls == 0) {
xlr_establish_intr(device_get_name(child), filt,
intr, arg, PIC_PCIX_IRQ, flags, cookiep, bridge_pcix_ack);
pic_setup_intr(PIC_IRT_PCIX_INDEX, PIC_PCIX_IRQ, 0x1, 0);
pic_setup_intr(PIC_IRT_PCIX_INDEX, PIC_PCIX_IRQ, 0x1, 1);
} else {
xlr_establish_intr(device_get_name(child), filt,
intr, arg, xlrirq, flags, cookiep, bridge_pcie_ack);
pic_setup_intr(xlrirq - PIC_IRQ_BASE, xlrirq, 0x1, 0);
pic_setup_intr(xlrirq - PIC_IRQ_BASE, xlrirq, 0x1, 1);
}
return (bus_generic_setup_intr(dev, child, irq, flags, filt, intr,