Add the SMP support for Raspberry Pi 2 (BCM2836).
Tested with the build of some ports and a buildworld. Submitted by: Daisuke Aoyama <aoyama@peach.ne.jp>
This commit is contained in:
Luiz Otavio O Souza
parent
696e43653b
commit
962940ce6c
@ -1425,7 +1425,10 @@ static int
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bcm2835_cpufreq_probe(device_t dev)
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{
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if (device_get_unit(dev) != 0)
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return (ENXIO);
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device_set_desc(dev, "CPU Frequency Control");
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return (0);
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}
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@ -52,7 +52,9 @@ __FBSDID("$FreeBSD$");
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#define ARM_LOCAL_INT_TIMER(n) (0x40 + (n) * 4)
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#define ARM_LOCAL_INT_MAILBOX(n) (0x50 + (n) * 4)
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#define ARM_LOCAL_INT_PENDING(n) (0x60 + (n) * 4)
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#define INT_PENDING_MASK 0x0f
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#define INT_PENDING_MASK 0x01f
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#define MAILBOX0_IRQ 4
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#define MAILBOX0_IRQEN (1 << 0)
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/*
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* A driver for features of the bcm2836.
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@ -141,12 +143,27 @@ void
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bcm2836_mask_irq(uintptr_t irq)
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{
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uint32_t reg;
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#ifdef SMP
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int cpu;
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#endif
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int i;
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if (irq < MAILBOX0_IRQ) {
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for (i = 0; i < 4; i++) {
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reg = bus_read_4(softc->sc_mem, ARM_LOCAL_INT_TIMER(i));
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reg = bus_read_4(softc->sc_mem,
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ARM_LOCAL_INT_TIMER(i));
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reg &= ~(1 << irq);
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bus_write_4(softc->sc_mem, ARM_LOCAL_INT_TIMER(i), reg);
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bus_write_4(softc->sc_mem,
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ARM_LOCAL_INT_TIMER(i), reg);
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}
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#ifdef SMP
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} else if (irq == MAILBOX0_IRQ) {
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/* Mailbox 0 for IPI */
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cpu = PCPU_GET(cpuid);
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reg = bus_read_4(softc->sc_mem, ARM_LOCAL_INT_MAILBOX(cpu));
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reg &= ~MAILBOX0_IRQEN;
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bus_write_4(softc->sc_mem, ARM_LOCAL_INT_MAILBOX(cpu), reg);
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#endif
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}
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}
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@ -154,12 +171,27 @@ void
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bcm2836_unmask_irq(uintptr_t irq)
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{
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uint32_t reg;
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#ifdef SMP
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int cpu;
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#endif
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int i;
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if (irq < MAILBOX0_IRQ) {
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for (i = 0; i < 4; i++) {
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reg = bus_read_4(softc->sc_mem, ARM_LOCAL_INT_TIMER(i));
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reg = bus_read_4(softc->sc_mem,
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ARM_LOCAL_INT_TIMER(i));
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reg |= (1 << irq);
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bus_write_4(softc->sc_mem, ARM_LOCAL_INT_TIMER(i), reg);
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bus_write_4(softc->sc_mem,
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ARM_LOCAL_INT_TIMER(i), reg);
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}
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#ifdef SMP
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} else if (irq == MAILBOX0_IRQ) {
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/* Mailbox 0 for IPI */
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cpu = PCPU_GET(cpuid);
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reg = bus_read_4(softc->sc_mem, ARM_LOCAL_INT_MAILBOX(cpu));
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reg |= MAILBOX0_IRQEN;
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bus_write_4(softc->sc_mem, ARM_LOCAL_INT_MAILBOX(cpu), reg);
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#endif
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}
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}
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207
sys/arm/broadcom/bcm2835/bcm2836_mp.c
Normal file
207
sys/arm/broadcom/bcm2835/bcm2836_mp.c
Normal file
@ -0,0 +1,207 @@
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/*-
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* Copyright (C) 2015 Daisuke Aoyama <aoyama@peach.ne.jp>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/smp.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#ifdef DEBUG
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#define DPRINTF(fmt, ...) do { \
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printf("%s:%u: ", __func__, __LINE__); \
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printf(fmt, ##__VA_ARGS__); \
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} while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define ARM_LOCAL_BASE 0x40000000
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#define ARM_LOCAL_SIZE 0x00001000
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/* mailbox registers */
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#define MBOXINTRCTRL_CORE(n) (0x00000050 + (0x04 * (n)))
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#define MBOX0SET_CORE(n) (0x00000080 + (0x10 * (n)))
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#define MBOX1SET_CORE(n) (0x00000084 + (0x10 * (n)))
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#define MBOX2SET_CORE(n) (0x00000088 + (0x10 * (n)))
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#define MBOX3SET_CORE(n) (0x0000008C + (0x10 * (n)))
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#define MBOX0CLR_CORE(n) (0x000000C0 + (0x10 * (n)))
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#define MBOX1CLR_CORE(n) (0x000000C4 + (0x10 * (n)))
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#define MBOX2CLR_CORE(n) (0x000000C8 + (0x10 * (n)))
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#define MBOX3CLR_CORE(n) (0x000000CC + (0x10 * (n)))
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static bus_space_handle_t bs_periph;
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#define BSRD4(addr) \
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bus_space_read_4(fdtbus_bs_tag, bs_periph, (addr))
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#define BSWR4(addr, val) \
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bus_space_write_4(fdtbus_bs_tag, bs_periph, (addr), (val))
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void
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platform_mp_init_secondary(void)
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{
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}
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void
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platform_mp_setmaxid(void)
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{
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DPRINTF("platform_mp_setmaxid\n");
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if (mp_ncpus != 0)
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return;
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mp_ncpus = 4;
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mp_maxid = mp_ncpus - 1;
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DPRINTF("mp_maxid=%d\n", mp_maxid);
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}
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int
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platform_mp_probe(void)
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{
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DPRINTF("platform_mp_probe\n");
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CPU_SETOF(0, &all_cpus);
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if (mp_ncpus == 0)
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platform_mp_setmaxid();
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return (mp_ncpus > 1);
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}
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void
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platform_mp_start_ap(void)
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{
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uint32_t val;
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int i, retry;
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DPRINTF("platform_mp_start_ap\n");
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/* initialize */
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if (bus_space_map(fdtbus_bs_tag, ARM_LOCAL_BASE, ARM_LOCAL_SIZE,
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0, &bs_periph) != 0)
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panic("can't map local peripheral\n");
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for (i = 0; i < mp_ncpus; i++) {
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/* clear mailbox 0/3 */
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BSWR4(MBOX0CLR_CORE(i), 0xffffffff);
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BSWR4(MBOX3CLR_CORE(i), 0xffffffff);
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}
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wmb();
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/* boot secondary CPUs */
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for (i = 1; i < mp_ncpus; i++) {
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/* set entry point to mailbox 3 */
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BSWR4(MBOX3SET_CORE(i),
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(uint32_t)pmap_kextract((vm_offset_t)mpentry));
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wmb();
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/* wait for bootup */
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retry = 1000;
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do {
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/* check entry point */
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val = BSRD4(MBOX3CLR_CORE(i));
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if (val == 0)
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break;
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DELAY(100);
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retry--;
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if (retry <= 0) {
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printf("can't start for CPU%d\n", i);
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break;
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}
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} while (1);
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/* dsb and sev */
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armv7_sev();
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/* recode AP in CPU map */
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CPU_SET(i, &all_cpus);
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}
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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}
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void
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pic_ipi_send(cpuset_t cpus, u_int ipi)
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{
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int i;
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dsb();
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for (i = 0; i < mp_ncpus; i++) {
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if (CPU_ISSET(i, &cpus))
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BSWR4(MBOX0SET_CORE(i), 1 << ipi);
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}
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wmb();
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}
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int
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pic_ipi_read(int i)
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{
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uint32_t val;
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int cpu, ipi;
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cpu = PCPU_GET(cpuid);
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dsb();
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if (i != -1) {
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val = BSRD4(MBOX0CLR_CORE(cpu));
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if (val == 0)
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return (0);
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ipi = ffs(val) - 1;
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return (ipi);
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}
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return (0x3ff);
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}
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void
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pic_ipi_clear(int ipi)
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{
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int cpu;
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cpu = PCPU_GET(cpuid);
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dsb();
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BSWR4(MBOX0CLR_CORE(cpu), 1 << ipi);
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wmb();
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}
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void
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platform_ipi_send(cpuset_t cpus, u_int ipi)
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{
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pic_ipi_send(cpus, ipi);
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}
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@ -3,3 +3,4 @@
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arm/arm/generic_timer.c standard
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arm/broadcom/bcm2835/bcm2836.c standard
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arm/broadcom/bcm2835/bcm2836_mp.c optional smp
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@ -6,6 +6,7 @@ makeoptions CONF_CFLAGS="-march=armv7a"
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options SOC_BCM2836
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options ARM_L2_PIPT
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options IPI_IRQ_START=76
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files "../broadcom/bcm2835/files.bcm2836"
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files "../broadcom/bcm2835/files.bcm283x"
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@ -25,7 +25,8 @@ include "../broadcom/bcm2835/std.rpi"
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include "../broadcom/bcm2835/std.bcm2836"
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options HZ=100
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options SCHED_4BSD # 4BSD scheduler
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options SCHED_ULE # ULE scheduler
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options SMP # Enable multiple cores
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options PLATFORM
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# Debugging for use in -current
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@ -43,6 +43,24 @@
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reg = <0xf00>; /* CPU ID=0xf00 */
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clock-frequency = <800000000>; /* 800MHz */
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf01>; /* CPU ID=0xf01 */
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clock-frequency = <800000000>; /* 800MHz */
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};
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cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf02>; /* CPU ID=0xf02 */
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clock-frequency = <800000000>; /* 800MHz */
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};
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cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf03>; /* CPU ID=0xf03 */
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clock-frequency = <800000000>; /* 800MHz */
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};
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};
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memory {
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