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Add the CR4 values for P3 SIMD enabling support. FXSR tells the cpu that

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the OS does FXSAVE/FXRESTOR instructions (fast FPU save/restore) during
context switching and also enables SIMD since this enables saving the
extra CPU context that isn't saved with normal FPU regs.  The other
enables the SIMD instructions to use exception 16 (FPU) error reporting.
Note, this doesn't turn on SIMD, just defines the bits.
This commit is contained in:
peter 1999-09-10 15:51:44 +00:00
parent c45b612ff1
commit 9686d60c61
2 changed files with 4 additions and 0 deletions
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2
sys/amd64/include/specialreg.h
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@ -71,6 +71,8 @@
#define CR4_MCE 0x00000040 /* Machine check enable */
#define CR4_PGE 0x00000080 /* Page global enable */
#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
/*
* CPUID instruction features register

2
sys/i386/include/specialreg.h
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@ -71,6 +71,8 @@
#define CR4_MCE 0x00000040 /* Machine check enable */
#define CR4_PGE 0x00000080 /* Page global enable */
#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
/*
* CPUID instruction features register