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Merge commit c6b09bff5 from llvm git (by Luís Marques):

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[RISCV] Fix wrong CFI directives

  Summary: Removes CFI CFA directives that could incorrectly propagate
  beyond the basic block they were inteded for. Specifically it removes
  the epilogue CFI directives. See the branch_and_tail_call test for an
  example of the issue. Should fix the stack unwinding issues caused by
  the incorrect directives.

  Reviewers: asb, lenary, shiva0217
  Reviewed By: lenary
  Tags: #llvm
  Differential Revision: https://reviews.llvm.org/D69723

This is a prerequisite for building and linking hard- and soft-float
riscv worlds with clang and lld.

Requested by:	jhb
MFC after:	1 week
X-MFC-With:	r353358
This commit is contained in:
Dimitry Andric 2020-01-03 20:19:17 +00:00
parent 5c72868c4c
commit 96d5330da8
1 changed files with 0 additions and 40 deletions
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40
contrib/llvm-project/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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@ -205,7 +205,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
MachineFrameInfo &MFI = MF.getFrameInfo();
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
DebugLoc DL = MBBI->getDebugLoc();
const RISCVInstrInfo *TII = STI.getInstrInfo();
unsigned FPReg = getFPReg(STI);
unsigned SPReg = getSPReg(STI);
@ -226,47 +225,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
MachineInstr::FrameDestroy);
}
if (hasFP(MF)) {
// To find the instruction restoring FP from stack.
for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
if (I->mayLoad() && I->getOperand(0).isReg()) {
unsigned DestReg = I->getOperand(0).getReg();
if (DestReg == FPReg) {
// If there is frame pointer, after restoring $fp registers, we
// need adjust CFA to ($sp - FPOffset).
// Emit ".cfi_def_cfa $sp, -FPOffset"
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
nullptr, RI->getDwarfRegNum(SPReg, true), -FPOffset));
BuildMI(MBB, std::next(I), DL,
TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
break;
}
}
}
}
// Add CFI directives for callee-saved registers.
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
// Iterate over list of callee-saved registers and emit .cfi_restore
// directives.
for (const auto &Entry : CSI) {
unsigned Reg = Entry.getReg();
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
nullptr, RI->getDwarfRegNum(Reg, true)));
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}
// Deallocate stack
adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
// After restoring $sp, we need to adjust CFA to $(sp + 0)
// Emit ".cfi_def_cfa_offset 0"
unsigned CFIIndex =
MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}
int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,