Simplify the PCI bus scanning logic.
Rather than special casing on PCIC_BRIDGE || PCIC_PROCESSOR, allow all HDRTYPE_BRIDGE types. Obtained from: Semihalf Sponsored by: Alex Perez/Intertial Computing
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41d50cd6b7
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@ -265,7 +265,7 @@ fsl_pcib_attach(device_t dev)
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*/
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sc->sc_busnr = 0;
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maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX;
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fsl_pcib_init(sc, sc->sc_busnr, maxslot);
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sc->sc_busnr = fsl_pcib_init(sc, sc->sc_busnr, maxslot);
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if (sc->sc_pcie) {
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ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
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@ -570,19 +570,8 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_SUBCLASS, 1);
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/*
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* The PCI Root Complex comes up as a Processor/PowerPC,
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* but is a bridge.
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*/
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/* Allow only proper PCI-PCI briges */
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if (class != PCIC_BRIDGE && class != PCIC_PROCESSOR)
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continue;
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if (subclass != PCIS_BRIDGE_PCI &&
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subclass != PCIS_PROCESSOR_POWERPC)
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continue;
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if (subclass == PCIS_PROCESSOR_POWERPC &&
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hdrtype != PCIM_HDRTYPE_BRIDGE)
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/* Allow all DEVTYPE 1 devices */
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if (hdrtype != PCIM_HDRTYPE_BRIDGE)
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continue;
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secbus++;
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