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Remove unused cpufunc arm11 and armv6 code. While here only define the

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remaining functions in the context we use them in.
This commit is contained in:
andrew 2015-03-29 18:44:15 +00:00
parent de83eaff79
commit 978db77056
3 changed files with 22 additions and 80 deletions
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14
sys/arm/arm/cpufunc_asm_arm11.S
View File

@ -37,20 +37,6 @@
#include <machine/asm.h>
__FBSDID("$FreeBSD$");
/*
* Functions to set the MMU Translation Table Base register
*
* We need to clean and flush the cache as it uses virtual
* addresses that are about to change.
*/
ENTRY(arm11_setttb)
mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
RET
END(arm11_setttb)
/*
* TLB functions
*/

38
sys/arm/arm/cpufunc_asm_armv6.S
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@ -61,29 +61,6 @@ END(armv6_setttb)
* Cache operations.
*/
/* LINTSTUB: void armv6_icache_sync_range(vaddr_t, vsize_t); */
ENTRY_NP(armv6_icache_sync_range)
add r1, r1, r0
sub r1, r1, #1
mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */
mcrr p15, 0, r1, r0, c12 /* clean D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_icache_sync_range)
/* LINTSTUB: void armv6_icache_sync_all(void); */
ENTRY_NP(armv6_icache_sync_all)
/*
* We assume that the code here can never be out of sync with the
* dcache, so that we can safely flush the Icache and fall through
* into the Dcache cleaning code.
*/
mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
mcr p15, 0, r0, c7, c10, 0 /* Clean D cache */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_icache_sync_all)
/* LINTSTUB: void armv6_dcache_wb_range(vaddr_t, vsize_t); */
ENTRY(armv6_dcache_wb_range)
add r1, r1, r0
@ -116,16 +93,6 @@ ENTRY(armv6_dcache_inv_range)
RET
END(armv6_dcache_inv_range)
/* LINTSTUB: void armv6_idcache_wbinv_range(vaddr_t, vsize_t); */
ENTRY(armv6_idcache_wbinv_range)
add r1, r1, r0
sub r1, r1, #1
mcrr p15, 0, r1, r0, c5 /* invaliate I cache range */
mcrr p15, 0, r1, r0, c14 /* clean & invaliate D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_idcache_wbinv_range)
/* LINTSTUB: void armv6_idcache_wbinv_all(void); */
ENTRY_NP(armv6_idcache_wbinv_all)
/*
@ -134,14 +101,11 @@ ENTRY_NP(armv6_idcache_wbinv_all)
* into the Dcache purging code.
*/
mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
/* Fall through to purge Dcache. */
/* LINTSTUB: void armv6_dcache_wbinv_all(void); */
EENTRY(armv6_dcache_wbinv_all)
/* Purge Dcache. */
mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
EEND(armv6_dcache_wbinv_all)
END(armv6_idcache_wbinv_all)
ENTRY(armv6_idcache_inv_all)

50
sys/arm/include/cpufunc.h
View File

@ -355,36 +355,10 @@ void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
void sheeva_l2cache_wbinv_all (void);
#endif
#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \
defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
void arm11_setttb (u_int);
void arm11_sleep (int);
void arm11_tlb_flushID_SE (u_int);
void arm11_tlb_flushI_SE (u_int);
void arm11_context_switch (void);
void arm11_setup (char *string);
void arm11_tlb_flushID (void);
void arm11_tlb_flushI (void);
void arm11_tlb_flushD (void);
void arm11_tlb_flushD_SE (u_int va);
void arm11_drain_writebuf (void);
void armv6_icache_sync_all (void);
void armv6_icache_sync_range (vm_offset_t, vm_size_t);
void armv6_dcache_wbinv_all (void);
void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t);
void armv6_dcache_inv_range (vm_offset_t, vm_size_t);
void armv6_dcache_wb_range (vm_offset_t, vm_size_t);
void armv6_idcache_inv_all (void);
#if defined(CPU_MV_PJ4B)
void armv6_idcache_wbinv_all (void);
void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t);
#endif
#if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
void armv7_setttb (u_int);
void armv7_tlb_flushID (void);
void armv7_tlb_flushID_SE (u_int);
@ -413,6 +387,23 @@ void cortexa_setup (char *);
#endif
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
void arm11_tlb_flushID (void);
void arm11_tlb_flushID_SE (u_int);
void arm11_tlb_flushI (void);
void arm11_tlb_flushI_SE (u_int);
void arm11_tlb_flushD (void);
void arm11_tlb_flushD_SE (u_int va);
void arm11_context_switch (void);
void arm11_drain_writebuf (void);
void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t);
void armv6_dcache_inv_range (vm_offset_t, vm_size_t);
void armv6_dcache_wb_range (vm_offset_t, vm_size_t);
void armv6_idcache_inv_all (void);
void arm11x6_setttb (u_int);
void arm11x6_idcache_wbinv_all (void);
void arm11x6_dcache_wbinv_all (void);
@ -424,6 +415,7 @@ void arm11x6_setup (char *string);
void arm11x6_sleep (int); /* no ref. for errata */
#endif
#if defined(CPU_ARM1136)
void arm11_sleep (int);
void arm1136_sleep_rev0 (int); /* for errata 336501 */
#endif