Remove deprecated DT sources of Armada 38x SoCs
Now, as all platform code and drivers support Linux DT binding, safely remove deprecated sources and rely on sys/gnu/dts from now on. Obtained from: Semihalf Sponsored by: Stormshield
This commit is contained in:
mw
parent
be1fef5d07
commit
97c2ab4351
@ -1,156 +0,0 @@
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/*
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* Device Tree Include file for Marvell Armada 380 SoC.
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*
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* Copyright (C) 2014 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "armada-38x.dtsi"
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/ {
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model = "Marvell Armada 380 family SoC";
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compatible = "marvell,armada380";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,armada-380-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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};
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soc {
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internal-regs {
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pinctrl@18000 {
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compatible = "marvell,mv88f6810-pinctrl";
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};
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};
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pcie-controller {
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compatible = "marvell,armada-370-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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ranges =
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<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
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0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
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0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
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0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
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0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
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0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
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/* x1 port */
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 8>;
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status = "disabled";
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};
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/* x1 port */
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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};
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/* x1 port */
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pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
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reg = <0x1800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
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0x81000000 0 0 0x81000000 0x3 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 6>;
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status = "disabled";
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};
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};
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};
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};
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@ -1,275 +0,0 @@
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/*
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* Device Tree file for Marvell Armada 385 Access Point Development board
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* (DB-88F6820-AP)
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*
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* Copyright (C) 2014 Marvell
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*
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* Nadav Haklai <nadavh@marvell.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* $FreeBSD$
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*/
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/dts-v1/;
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#include "armada-385.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Marvell Armada 385 Access Point Development Board";
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compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
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chosen {
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stdout-path = "serial1";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x80000000>; /* 2GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
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internal-regs {
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i2c0: i2c@11000 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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/*
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* This bus is wired to two EEPROM
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* sockets, one of which holding the
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* board ID used by the bootloader.
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* Erasing this EEPROM's content will
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* brick the board.
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* Use this bus with caution.
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*/
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};
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mdio@72004 {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>;
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phy0: ethernet-phy@1 {
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reg = <1>;
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};
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phy1: ethernet-phy@4 {
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reg = <4>;
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};
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phy2: ethernet-phy@6 {
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reg = <6>;
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};
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};
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/* UART0 is exposed through the JP8 connector */
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uart0: serial@12000 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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/*
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* UART1 is exposed through a FTDI chip
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* wired to the mini-USB connector
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*/
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uart1: serial@12100 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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pinctrl@18000 {
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xhci0_vbus_pins: xhci0-vbus-pins {
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marvell,pins = "mpp44";
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marvell,function = "gpio";
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};
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};
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/* CON3 */
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ethernet@30000 {
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status = "okay";
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phy = <&phy2>;
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phy-mode = "sgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <1>;
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bm,pool-short = <3>;
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};
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/* CON2 */
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ethernet@34000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "sgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <2>;
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bm,pool-short = <3>;
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};
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usb@58000 {
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status = "okay";
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};
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/* CON4 */
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ethernet@70000 {
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pinctrl-names = "default";
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/*
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* The Reference Clock 0 is used to
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* provide a clock to the PHY
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*/
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pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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buffer-manager = <&bm>;
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bm,pool-long = <0>;
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bm,pool-short = <3>;
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};
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crypto@90000 {
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status = "okay";
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};
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crypto@92000 {
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status = "okay";
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};
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bm@c8000 {
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status = "okay";
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};
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nfc: flash@d0000 {
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status = "okay";
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num-cs = <1>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x00000000 0x00800000>;
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read-only;
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};
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partition@800000 {
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label = "uImage";
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reg = <0x00800000 0x00400000>;
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read-only;
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};
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partition@c00000 {
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label = "Root";
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reg = <0x00c00000 0x3f400000>;
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};
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};
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};
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usb3@f0000 {
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status = "okay";
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usb-phy = <&usb3_phy>;
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};
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};
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bm-bppi {
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status = "okay";
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};
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pcie-controller {
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status = "okay";
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/*
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* The three PCIe units are accessible through
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* standard mini-PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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pcie@3,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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};
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};
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usb3_phy: usb3_phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <®_xhci0_vbus>;
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};
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reg_xhci0_vbus: xhci0-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&xhci0_vbus_pins>;
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regulator-name = "xhci0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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};
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins>;
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p128", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <54000000>;
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};
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};
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@ -1,187 +0,0 @@
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/*
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* Device Tree Include file for Marvell Armada 385 SoC.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#include "armada-38x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 family SoC";
|
||||
compatible = "marvell,armada385", "marvell,armada380";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-380-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6820-pinctrl";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
|
||||
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
|
||||
|
||||
/*
|
||||
* This port can be either x4 or x1. When
|
||||
* configured in x4 by the bootloader, then
|
||||
* pcie@4,0 is not available.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* x1 port only available when pcie@1,0 is
|
||||
* configured as a x1 port
|
||||
*/
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
@ -1,459 +0,0 @@
|
||||
/*
|
||||
* Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
|
||||
*
|
||||
* Copyright (C) 2015 Russell King
|
||||
*
|
||||
* This board is in development; the contents of this file work with
|
||||
* the A1 rev 2.0 of the board, which does not represent final
|
||||
* production board. Things will change, don't expect this file to
|
||||
* remain compatible info the future.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-388.dtsi"
|
||||
#include "armada-38x-solidrun-microsom.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SolidRun Clearfog A1";
|
||||
compatible = "solidrun,clearfog-a1", "marvell,armada388",
|
||||
"marvell,armada385", "marvell,armada380";
|
||||
|
||||
aliases {
|
||||
/* So that mvebu u-boot can update the MAC addresses */
|
||||
ethernet1 = ð0;
|
||||
ethernet2 = ð1;
|
||||
ethernet3 = ð2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
ethernet@30000 {
|
||||
phy-mode = "sgmii";
|
||||
buffer-manager = <&bm>;
|
||||
bm,pool-long = <2>;
|
||||
bm,pool-short = <1>;
|
||||
status = "okay";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@34000 {
|
||||
phy-mode = "sgmii";
|
||||
buffer-manager = <&bm>;
|
||||
bm,pool-long = <3>;
|
||||
bm,pool-short = <1>;
|
||||
status = "okay";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
/* Is there anything on this? */
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* PCA9655 GPIO expander, up to 1MHz clock.
|
||||
* 0-CON3 CLKREQ#
|
||||
* 1-CON3 PERST#
|
||||
* 2-CON2 PERST#
|
||||
* 3-CON3 W_DISABLE
|
||||
* 4-CON2 CLKREQ#
|
||||
* 5-USB3 overcurrent
|
||||
* 6-USB3 power
|
||||
* 7-CON2 W_DISABLE
|
||||
* 8-JP4 P1
|
||||
* 9-JP4 P4
|
||||
* 10-JP4 P5
|
||||
* 11-m.2 DEVSLP
|
||||
* 12-SFP_LOS
|
||||
* 13-SFP_TX_FAULT
|
||||
* 14-SFP_TX_DISABLE
|
||||
* 15-SFP_MOD_DEF0
|
||||
*/
|
||||
expander0: gpio-expander@20 {
|
||||
/*
|
||||
* This is how it should be:
|
||||
* compatible = "onnn,pca9655",
|
||||
* "nxp,pca9555";
|
||||
* but you can't do this because of
|
||||
* the way I2C works.
|
||||
*/
|
||||
compatible = "nxp,pca9555";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x20>;
|
||||
|
||||
pcie1_0_clkreq {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "pcie1.0-clkreq";
|
||||
};
|
||||
pcie1_0_w_disable {
|
||||
gpio-hog;
|
||||
gpios = <3 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "pcie1.0-w-disable";
|
||||
};
|
||||
pcie2_0_clkreq {
|
||||
gpio-hog;
|
||||
gpios = <4 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "pcie2.0-clkreq";
|
||||
};
|
||||
pcie2_0_w_disable {
|
||||
gpio-hog;
|
||||
gpios = <7 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "pcie2.0-w-disable";
|
||||
};
|
||||
usb3_ilimit {
|
||||
gpio-hog;
|
||||
gpios = <5 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "usb3-current-limit";
|
||||
};
|
||||
usb3_power {
|
||||
gpio-hog;
|
||||
gpios = <6 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "usb3-power";
|
||||
};
|
||||
m2_devslp {
|
||||
gpio-hog;
|
||||
gpios = <11 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "m.2 devslp";
|
||||
};
|
||||
sfp_los {
|
||||
/* SFP loss of signal */
|
||||
gpio-hog;
|
||||
gpios = <12 GPIO_ACTIVE_HIGH>;
|
||||
input;
|
||||
line-name = "sfp-los";
|
||||
};
|
||||
sfp_tx_fault {
|
||||
/* SFP laser fault */
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||
input;
|
||||
line-name = "sfp-tx-fault";
|
||||
};
|
||||
sfp_tx_disable {
|
||||
/* SFP transmit disable */
|
||||
gpio-hog;
|
||||
gpios = <14 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "sfp-tx-disable";
|
||||
};
|
||||
sfp_mod_def0 {
|
||||
/* SFP module present */
|
||||
gpio-hog;
|
||||
gpios = <15 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "sfp-mod-def0";
|
||||
};
|
||||
};
|
||||
|
||||
/* The MCP3021 is 100kHz clock only */
|
||||
mikrobus_adc: mcp3021@4c {
|
||||
compatible = "microchip,mcp3021";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
/* Also something at 0x64 */
|
||||
};
|
||||
|
||||
i2c@11100 {
|
||||
/*
|
||||
* Routed to SFP, mikrobus, and PCIe.
|
||||
* SFP limits this to 100kHz, and requires
|
||||
* an AT24C01A/02/04 with address pins tied
|
||||
* low, which takes addresses 0x50 and 0x51.
|
||||
* Mikrobus doesn't specify beyond an I2C
|
||||
* bus being present.
|
||||
* PCIe uses ARP to assign addresses, or
|
||||
* 0x63-0x64.
|
||||
*/
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&clearfog_i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@18000 {
|
||||
clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
|
||||
marvell,pins = "mpp46";
|
||||
marvell,function = "ref";
|
||||
};
|
||||
clearfog_dsa0_pins: clearfog-dsa0-pins {
|
||||
marvell,pins = "mpp23", "mpp41";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
clearfog_i2c1_pins: i2c1-pins {
|
||||
/* SFP, PCIe, mSATA, mikrobus */
|
||||
marvell,pins = "mpp26", "mpp27";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
|
||||
marvell,pins = "mpp20";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
clearfog_sdhci_pins: clearfog-sdhci-pins {
|
||||
marvell,pins = "mpp21", "mpp28",
|
||||
"mpp37", "mpp38",
|
||||
"mpp39", "mpp40";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
clearfog_spi1_cs_pins: spi1-cs-pins {
|
||||
marvell,pins = "mpp55";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
mikro_pins: mikro-pins {
|
||||
/* int: mpp22 rst: mpp29 */
|
||||
marvell,pins = "mpp22", "mpp29";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
mikro_spi_pins: mikro-spi-pins {
|
||||
marvell,pins = "mpp43";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
mikro_uart_pins: mikro-uart-pins {
|
||||
marvell,pins = "mpp24", "mpp25";
|
||||
marvell,function = "ua1";
|
||||
};
|
||||
rear_button_pins: rear-button-pins {
|
||||
marvell,pins = "mpp34";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
/* pinctrl? */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
/* pinctrl? */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@d8000 {
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
pinctrl-0 = <&clearfog_sdhci_pins
|
||||
&clearfog_sdhci_cd_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
vmmc = <®_3p3v>;
|
||||
wp-inverted;
|
||||
};
|
||||
|
||||
serial@12100 {
|
||||
/* mikrobus uart */
|
||||
pinctrl-0 = <&mikro_uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@58000 {
|
||||
/* CON3, nearest power. */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@92000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3@f0000 {
|
||||
/* CON2, nearest CPU, USB2 only. */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3@f8000 {
|
||||
/* CON7 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/*
|
||||
* The two PCIe units are accessible through
|
||||
* the mini-PCIe connectors on the board.
|
||||
*/
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0. CON3, nearest power. */
|
||||
reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
pcie@3,0 {
|
||||
/* Port 2, Lane 0. CON2, nearest CPU. */
|
||||
reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsa@0 {
|
||||
compatible = "marvell,dsa";
|
||||
dsa,ethernet = <ð1>;
|
||||
dsa,mii-bus = <&mdio>;
|
||||
pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4 0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan5";
|
||||
vlangroup = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan4";
|
||||
vlangroup = <0>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
vlangroup = <0>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan2";
|
||||
vlangroup = <0>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
vlangroup = <0>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
vlangroup = <0>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
/* 88E1512 external phy */
|
||||
reg = <6>;
|
||||
label = "lan6";
|
||||
vlangroup = <0>;
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&rear_button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
button_0 {
|
||||
/* The rear SW3 button */
|
||||
label = "Rear Button";
|
||||
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
||||
linux,can-disable;
|
||||
linux,code = <BTN_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
/*
|
||||
* We don't seem to have the W25Q32 on the
|
||||
* A1 Rev 2.0 boards, so disable SPI.
|
||||
* CS0: W25Q32 (doesn't appear to be present)
|
||||
* CS1:
|
||||
* CS2: mikrobus
|
||||
*/
|
||||
pinctrl-0 = <&spi1_pins
|
||||
&clearfog_spi1_cs_pins
|
||||
&mikro_spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "w25q32", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <3000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@ -1,425 +0,0 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada 385 development board
|
||||
* (RD-88F6820-GP)
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-388.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 GP";
|
||||
compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000>; /* 2 GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
|
||||
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
crypto@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
crypto@92000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi@10600 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
/*
|
||||
* The EEPROM located at adresse 54 is needed
|
||||
* for the boot - DO NOT ERASE IT -
|
||||
*/
|
||||
|
||||
expander0: pca9555@20 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pca0_pins>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x20>;
|
||||
};
|
||||
|
||||
expander1: pca9555@21 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x21>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
/*
|
||||
* Exported on the micro USB connector CON16
|
||||
* through an FTDI
|
||||
*/
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* GE1 CON15 */
|
||||
ethernet@30000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
/* CON4 */
|
||||
usb@58000 {
|
||||
vcc-supply = <®_usb2_0_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* GE0 CON1 */
|
||||
ethernet@70000 {
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* The Reference Clock 0 is used to provide a
|
||||
* clock to the PHY
|
||||
*/
|
||||
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
|
||||
mdio@72004 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata0: sata-port@0 {
|
||||
reg = <0>;
|
||||
target-supply = <®_5v_sata0>;
|
||||
};
|
||||
|
||||
sata1: sata-port@1 {
|
||||
reg = <1>;
|
||||
target-supply = <®_5v_sata1>;
|
||||
};
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata2: sata-port@0 {
|
||||
reg = <0>;
|
||||
target-supply = <®_5v_sata2>;
|
||||
};
|
||||
|
||||
sata3: sata-port@1 {
|
||||
reg = <1>;
|
||||
target-supply = <®_5v_sata3>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@d8000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhci_pins>;
|
||||
cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
wp-inverted;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON5 */
|
||||
usb3@f0000 {
|
||||
vcc-supply = <®_usb2_1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON7 */
|
||||
usb3@f8000 {
|
||||
vcc-supply = <®_usb3_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-fan {
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = < 0 0
|
||||
3000 1>;
|
||||
};
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/*
|
||||
* One PCIe units is accessible through
|
||||
* standard PCIe slot on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* The two other PCIe units are accessible
|
||||
* through mini PCIe slot on the board.
|
||||
*/
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@3,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
reg_usb3_vbus: usb3-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb3-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_0_vbus: v5-vbus0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_1_vbus: v5-vbus1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_1_vbus: v5-vbus1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_sata0: pwr-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata0";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
|
||||
};
|
||||
|
||||
reg_5v_sata0: v5-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
reg_12v_sata0: v12-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
reg_sata1: pwr-sata1 {
|
||||
regulator-name = "pwr_en_sata1";
|
||||
compatible = "regulator-fixed";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata1: v5-sata1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
reg_12v_sata1: v12-sata1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata1";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
reg_sata2: pwr-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata2";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata2: v5-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata2";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata2>;
|
||||
};
|
||||
|
||||
reg_12v_sata2: v12-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata2";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata2>;
|
||||
};
|
||||
|
||||
reg_sata3: pwr-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata3";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata3: v5-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata3";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata3>;
|
||||
};
|
||||
|
||||
reg_12v_sata3: v12-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata3";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata3>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pca0_pins: pca0_pins {
|
||||
marvell,pins = "mpp18";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
@ -1,72 +0,0 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 388 SoC.
|
||||
*
|
||||
* Copyright (C) 2015 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*
|
||||
* The main difference with the Armada 385 is that the 388 can handle two more
|
||||
* SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
|
||||
* property and the name of the SoC, and add the second SATA host which control
|
||||
* the 2 other ports.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#include "armada-385.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 388 family SoC";
|
||||
compatible = "marvell,armada388", "marvell,armada385",
|
||||
"marvell,armada380";
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6828-pinctrl";
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,130 +0,0 @@
|
||||
/*
|
||||
* Device Tree file for SolidRun Armada 38x Microsom
|
||||
*
|
||||
* Copyright (C) 2015 Russell King
|
||||
*
|
||||
* This board is in development; the contents of this file work with
|
||||
* the A1 rev 2.0 of the board, which does not represent final
|
||||
* production board. Things will change, don't expect this file to
|
||||
* remain compatible info the future.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
|
||||
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
ethernet@70000 {
|
||||
pinctrl-0 = <&ge0_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy = <&phy_dedicated>;
|
||||
phy-mode = "rgmii-id";
|
||||
buffer-manager = <&bm>;
|
||||
bm,pool-long = <0>;
|
||||
bm,pool-short = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio@72004 {
|
||||
/*
|
||||
* Add the phy clock here, so the phy can be
|
||||
* accessed to read its IDs prior to binding
|
||||
* with the driver.
|
||||
*/
|
||||
pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy_dedicated: ethernet-phy@0 {
|
||||
/*
|
||||
* Annoyingly, the marvell phy driver
|
||||
* configures the LED register, rather
|
||||
* than preserving reset-loaded setting.
|
||||
* We undo that rubbish here.
|
||||
*/
|
||||
marvell,reg-init = <3 16 0 0x101e>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@18000 {
|
||||
microsom_phy_clk_pins: microsom-phy-clk-pins {
|
||||
marvell,pins = "mpp45";
|
||||
marvell,function = "ref";
|
||||
};
|
||||
};
|
||||
|
||||
rtc@a3800 {
|
||||
/*
|
||||
* If the rtc doesn't work, run "date reset"
|
||||
* twice in u-boot.
|
||||
*/
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
bm@c8000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
bm-bppi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
@ -1,664 +0,0 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 38x family of SoCs.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 38x family SoC";
|
||||
compatible = "marvell,armada380";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
sram0 = &SRAM0;
|
||||
sram1 = &SRAM1;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts-extended = <&mpic 3>;
|
||||
};
|
||||
|
||||
SRAM0: sram@f1100000 {
|
||||
compatible = "mrvl,cesa-sram";
|
||||
reg = <0xf1100000 0x0010000>;
|
||||
};
|
||||
|
||||
SRAM1: sram@f1110000 {
|
||||
compatible = "mrvl,cesa-sram";
|
||||
reg = <0xf1110000 0x0010000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armada380-mbus", "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
controller = <&mbusc>;
|
||||
interrupt-parent = <&gic>;
|
||||
pcie-mem-aperture = <0xe0000000 0x8000000>;
|
||||
pcie-io-aperture = <0xe8000000 0x100000>;
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
|
||||
};
|
||||
|
||||
devbus-bootcs {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs0 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs1 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs2 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs3 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
||||
|
||||
crypto@90000 {
|
||||
compatible = "mrvl,cesa";
|
||||
reg = <0x90000 0x1000 /* tdma base reg chan 0 */
|
||||
0x9D000 0x1000>; /* cesa base reg chan 0 */
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
sram-handle = <&SRAM0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crypto@92000 {
|
||||
compatible = "mrvl,cesa";
|
||||
reg = <0x92000 0x1000 /* tdma base reg chan 1 */
|
||||
0x9F000 0x1000>; /* cesa base reg chan 1 */
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
sram-handle = <&SRAM1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
L2: cache-controller@8000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x8000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
arm,double-linefill-incr = <1>;
|
||||
arm,double-linefill-wrap = <0>;
|
||||
arm,double-linefill = <1>;
|
||||
prefetch-data = <1>;
|
||||
};
|
||||
|
||||
scu@c000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0xc000 0x58>;
|
||||
};
|
||||
|
||||
timer@c200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0xc200 0x20>;
|
||||
interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
|
||||
clocks = <&coreclk 2>;
|
||||
};
|
||||
|
||||
timer@c600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xc600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
|
||||
clocks = <&coreclk 2>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@d000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0xd000 0x1000>,
|
||||
<0xc100 0x100>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@12100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@18000 {
|
||||
reg = <0x18000 0x20>;
|
||||
|
||||
ge0_rgmii_pins: ge-rgmii-pins-0 {
|
||||
marvell,pins = "mpp6", "mpp7", "mpp8",
|
||||
"mpp9", "mpp10", "mpp11",
|
||||
"mpp12", "mpp13", "mpp14",
|
||||
"mpp15", "mpp16", "mpp17";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
ge1_rgmii_pins: ge-rgmii-pins-1 {
|
||||
marvell,pins = "mpp21", "mpp27", "mpp28",
|
||||
"mpp29", "mpp30", "mpp31",
|
||||
"mpp32", "mpp37", "mpp38",
|
||||
"mpp39", "mpp40", "mpp41";
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c-pins-0 {
|
||||
marvell,pins = "mpp2", "mpp3";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
mdio_pins: mdio-pins {
|
||||
marvell,pins = "mpp4", "mpp5";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
|
||||
ref_clk0_pins: ref-clk-pins-0 {
|
||||
marvell,pins = "mpp45";
|
||||
marvell,function = "ref";
|
||||
};
|
||||
|
||||
ref_clk1_pins: ref-clk-pins-1 {
|
||||
marvell,pins = "mpp46";
|
||||
marvell,function = "ref";
|
||||
};
|
||||
|
||||
spi0_pins: spi-pins-0 {
|
||||
marvell,pins = "mpp22", "mpp23", "mpp24",
|
||||
"mpp25";
|
||||
marvell,function = "spi0";
|
||||
};
|
||||
|
||||
spi1_pins: spi-pins-1 {
|
||||
marvell,pins = "mpp56", "mpp57", "mpp58",
|
||||
"mpp59";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
uart0_pins: uart-pins-0 {
|
||||
marvell,pins = "mpp0", "mpp1";
|
||||
marvell,function = "ua0";
|
||||
};
|
||||
|
||||
uart1_pins: uart-pins-1 {
|
||||
marvell,pins = "mpp19", "mpp20";
|
||||
marvell,function = "ua1";
|
||||
};
|
||||
|
||||
sdhci_pins: sdhci-pins {
|
||||
marvell,pins = "mpp48", "mpp49", "mpp50",
|
||||
"mpp52", "mpp53", "mpp54",
|
||||
"mpp55", "mpp57", "mpp58",
|
||||
"mpp59";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
|
||||
sata0_pins: sata-pins-0 {
|
||||
marvell,pins = "mpp20";
|
||||
marvell,function = "sata0";
|
||||
};
|
||||
|
||||
sata1_pins: sata-pins-1 {
|
||||
marvell,pins = "mpp19";
|
||||
marvell,function = "sata1";
|
||||
};
|
||||
|
||||
sata2_pins: sata-pins-2 {
|
||||
marvell,pins = "mpp47";
|
||||
marvell,function = "sata2";
|
||||
};
|
||||
|
||||
sata3_pins: sata-pins-3 {
|
||||
marvell,pins = "mpp44";
|
||||
marvell,function = "sata3";
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <28>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-380-system-controller",
|
||||
"marvell,armada-370-xp-system-controller";
|
||||
reg = <0x18200 0x100>;
|
||||
};
|
||||
|
||||
gateclk: clock-gating-control@18220 {
|
||||
compatible = "marvell,armada-380-gating-clock";
|
||||
reg = <0x18220 0x4>;
|
||||
clocks = <&coreclk 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
coreclk: mvebu-sar@18600 {
|
||||
compatible = "marvell,armada-380-core-clock";
|
||||
reg = <0x18600 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@20a00 {
|
||||
compatible = "marvell,mpic";
|
||||
reg = <0x20a00 0x2d0>, <0x21870 0x300>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "marvell,armada-380-timer",
|
||||
"marvell,armada-xp-timer";
|
||||
reg = <0x20300 0x30>, <0x21040 0x30>;
|
||||
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&mpic 5>,
|
||||
<&mpic 6>;
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-380-wdt";
|
||||
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x10>;
|
||||
};
|
||||
|
||||
mpcore-soc-ctrl@20d20 {
|
||||
compatible = "marvell,armada-380-mpcore-soc-ctrl";
|
||||
reg = <0x20d20 0x6c>;
|
||||
};
|
||||
|
||||
coherency-fabric@21010 {
|
||||
compatible = "marvell,armada-380-coherency-fabric";
|
||||
reg = <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
pmsu@22000 {
|
||||
compatible = "marvell,armada-380-pmsu";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
eth1: ethernet@30000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x30000 0x4000>;
|
||||
interrupts-extended = <&mpic 10>;
|
||||
clocks = <&gateclk 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth2: ethernet@34000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x34000 0x4000>;
|
||||
interrupts-extended = <&mpic 12>;
|
||||
clocks = <&gateclk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@58000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x58000 0x500>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60800 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60800 0x100
|
||||
0x60a00 0x100>;
|
||||
clocks = <&gateclk 22>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
clocks = <&gateclk 28>;
|
||||
status = "okay";
|
||||
|
||||
xor10 {
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor11 {
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@70000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts-extended = <&mpic 8>;
|
||||
clocks = <&gateclk 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio: mdio@72004 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x72004 0x4>;
|
||||
clocks = <&gateclk 4>;
|
||||
};
|
||||
|
||||
rtc@a3800 {
|
||||
compatible = "marvell,armada-380-rtc";
|
||||
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
|
||||
reg-names = "rtc", "rtc-soc";
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xa8000 0x2000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bm: bm@c8000 {
|
||||
compatible = "marvell,armada-380-neta-bm";
|
||||
reg = <0xc8000 0xac>;
|
||||
clocks = <&gateclk 13>;
|
||||
internal-mem = <&bm_bppi>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
coredivclk: clock@e4250 {
|
||||
compatible = "marvell,armada-380-corediv-clock";
|
||||
reg = <0xe4250 0xc>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&mainpll>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
thermal@e8078 {
|
||||
compatible = "marvell,armada380-thermal";
|
||||
reg = <0xe4078 0x4>, <0xe4074 0x4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
flash@d0000 {
|
||||
compatible = "marvell,armada370-nand";
|
||||
reg = <0xd0000 0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coredivclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@d8000 {
|
||||
compatible = "marvell,armada-380-sdhci";
|
||||
reg-names = "sdhci", "mbus", "conf-sdio3";
|
||||
reg = <0xd8000 0x1000>,
|
||||
<0xdc000 0x100>,
|
||||
<0x18454 0x4>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 17>;
|
||||
mrvl,clk-delay-cycles = <0x1F>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@f0000 {
|
||||
compatible = "marvell,armada-380-xhci";
|
||||
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@f8000 {
|
||||
compatible = "marvell,armada-380-xhci";
|
||||
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
bm_bppi: bm-bppi {
|
||||
compatible = "mmio-sram";
|
||||
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
|
||||
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&gateclk 13>;
|
||||
no-memory-wc;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 2 GHz fixed main PLL */
|
||||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
|
||||
/* 25 MHz reference crystal */
|
||||
refclk: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
x
Reference in New Issue
Block a user