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ath: clean up empty lines in .c and .h files

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This commit is contained in:
Mateusz Guzik 2020-09-01 21:41:07 +00:00
parent 1529c50966
commit 9966c0f962
99 changed files with 83 additions and 197 deletions
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1
sys/dev/ath/ah_osdep.c
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@ -447,7 +447,6 @@ ath_hal_modevent(module_t mod __unused, int type, void *data __unused)
default: default:
error = EOPNOTSUPP; error = EOPNOTSUPP;
break; break;
} }
return (error); return (error);
} }

1
sys/dev/ath/ah_osdep_ar5210.c
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@ -64,7 +64,6 @@ ath_hal_ar5210_modevent(module_t mod __unused, int type, void *data __unused)
default: default:
error = EOPNOTSUPP; error = EOPNOTSUPP;
break; break;
} }
return (error); return (error);
} }

1
sys/dev/ath/ah_osdep_ar5211.c
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@ -64,7 +64,6 @@ ath_hal_ar5211_modevent(module_t mod __unused, int type, void *data __unused)
default: default:
error = EOPNOTSUPP; error = EOPNOTSUPP;
break; break;
} }
return (error); return (error);
} }

1
sys/dev/ath/ah_osdep_ar5212.c
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@ -85,7 +85,6 @@ ath_hal_ar5212_modevent(module_t mod __unused, int type, void *data __unused)
default: default:
error = EOPNOTSUPP; error = EOPNOTSUPP;
break; break;
} }
return (error); return (error);
} }

1
sys/dev/ath/ah_osdep_ar5416.c
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@ -92,7 +92,6 @@ ath_hal_ar5416_modevent(module_t mod __unused, int type, void *data __unused)
default: default:
error = EOPNOTSUPP; error = EOPNOTSUPP;
break; break;
} }
return (error); return (error);
} }

1
sys/dev/ath/ah_osdep_ar9300.c
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@ -64,7 +64,6 @@ ath_hal_ar9300_modevent(module_t mod __unused, int type, void *data __unused)
default: default:
error = EOPNOTSUPP; error = EOPNOTSUPP;
break; break;
} }
return (error); return (error);
} }

1
sys/dev/ath/ath_hal/ah.c
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@ -556,7 +556,6 @@ ath_hal_get_curmode(struct ath_hal *ah, const struct ieee80211_channel *chan)
return HAL_MODE_11NG_HT20; return HAL_MODE_11NG_HT20;
} }
typedef enum { typedef enum {
WIRELESS_MODE_11a = 0, WIRELESS_MODE_11a = 0,
WIRELESS_MODE_TURBO = 1, WIRELESS_MODE_TURBO = 1,

2
sys/dev/ath/ath_hal/ah.h
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@ -739,7 +739,6 @@ typedef enum {
HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
} HAL_HT_EXTPROTSPACING; } HAL_HT_EXTPROTSPACING;
typedef enum { typedef enum {
HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
@ -1053,7 +1052,6 @@ typedef enum {
HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */
} HAL_DFS_DOMAIN; } HAL_DFS_DOMAIN;
/* /*
* MFP decryption options for initializing the MAC. * MFP decryption options for initializing the MAC.
*/ */

1
sys/dev/ath/ath_hal/ah_eeprom_9287.c
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@ -234,7 +234,6 @@ fbin2freq(uint8_t fbin, HAL_BOOL is2GHz)
return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
} }
/* /*
* Copy EEPROM Conformance Testing Limits contents * Copy EEPROM Conformance Testing Limits contents
* into the allocated space * into the allocated space

1
sys/dev/ath/ath_hal/ah_eeprom_9287.h
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@ -166,5 +166,4 @@ typedef struct {
typedef struct modal_eep_ar9287_header MODAL_EEP_9287_HEADER; typedef struct modal_eep_ar9287_header MODAL_EEP_9287_HEADER;
typedef struct base_eep_ar9287_header BASE_EEP_9287_HEADER; typedef struct base_eep_ar9287_header BASE_EEP_9287_HEADER;
#endif /* __AH_EEPROM_9287_H__ */ #endif /* __AH_EEPROM_9287_H__ */

1
sys/dev/ath/ath_hal/ah_eeprom_v3.h
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@ -231,7 +231,6 @@ typedef struct cornerCalInfo {
#define NUM_TARGET_POWER_LOCATIONS_11B 4 #define NUM_TARGET_POWER_LOCATIONS_11B 4
#define NUM_TARGET_POWER_LOCATIONS_11G 6 #define NUM_TARGET_POWER_LOCATIONS_11G 6
typedef struct { typedef struct {
uint16_t xpd_gain; uint16_t xpd_gain;
uint16_t numPcdacs; uint16_t numPcdacs;

1
sys/dev/ath/ath_hal/ah_internal.h
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@ -849,7 +849,6 @@ typedef struct {
uint16_t ee_data; /* write data */ uint16_t ee_data; /* write data */
} HAL_DIAG_EEVAL; } HAL_DIAG_EEVAL;
typedef struct { typedef struct {
u_int offset; /* reg offset */ u_int offset; /* reg offset */
uint32_t val; /* reg value */ uint32_t val; /* reg value */

2
sys/dev/ath/ath_hal/ah_regdomain.c
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@ -953,7 +953,6 @@ ath_hal_getctl(struct ath_hal *ah, const struct ieee80211_channel *c)
return ctl; return ctl;
} }
/* /*
* Update the current dfsDomain setting based on the given * Update the current dfsDomain setting based on the given
* country code. * country code.
@ -979,7 +978,6 @@ ath_hal_update_dfsdomain(struct ath_hal *ah)
__func__, AH_PRIVATE(ah)->ah_dfsDomain); __func__, AH_PRIVATE(ah)->ah_dfsDomain);
} }
/* /*
* Return the max allowed antenna gain and apply any regulatory * Return the max allowed antenna gain and apply any regulatory
* domain specific changes. * domain specific changes.

1
sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h
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@ -64,7 +64,6 @@
W1(_fg) | W1(_fh) | W1(_fi) } W1(_fg) | W1(_fh) | W1(_fi) }
static REG_DOMAIN regDomains[] = { static REG_DOMAIN regDomains[] = {
{.regDmnEnum = DEBUG_REG_DMN, {.regDmnEnum = DEBUG_REG_DMN,
.conformanceTestLimit = FCC, .conformanceTestLimit = FCC,
.dfsMask = DFS_FCC3, .dfsMask = DFS_FCC3,

1
sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h
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@ -198,7 +198,6 @@ static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = {
#define W2_5825_5825 AFTER(W2_5180_5240) #define W2_5825_5825 AFTER(W2_5180_5240)
}; };
/* /*
* 5GHz Turbo (dynamic & static) tags * 5GHz Turbo (dynamic & static) tags
*/ */

1
sys/dev/ath/ath_hal/ar5210/ar5210_recv.c
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@ -50,7 +50,6 @@ ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)
OS_REG_WRITE(ah, AR_RXDP, rxdp); OS_REG_WRITE(ah, AR_RXDP, rxdp);
} }
/* /*
* Set Receive Enable bits. * Set Receive Enable bits.
*/ */

1
sys/dev/ath/ath_hal/ar5210/ar5210_reset.c
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@ -611,7 +611,6 @@ ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int delay)
return rt; return rt;
} }
/* /*
* Returns: the pcdac value * Returns: the pcdac value
*/ */

1
sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c
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@ -163,7 +163,6 @@ ar5211SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
if (k->kv_len <= 104 / NBBY) if (k->kv_len <= 104 / NBBY)
key4 &= 0xff; key4 &= 0xff;
/* /*
* Note: WEP key cache hardware requires that each double-word * Note: WEP key cache hardware requires that each double-word
* pair be written in even/odd order (since the destination is * pair be written in even/odd order (since the destination is

1
sys/dev/ath/ath_hal/ar5211/ar5211_misc.c
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@ -708,7 +708,6 @@ ar5211Get11nExtBusy(struct ath_hal *ah)
return (0); return (0);
} }
/* /*
* There's no channel survey support for the AR5211. * There's no channel survey support for the AR5211.
*/ */

1
sys/dev/ath/ath_hal/ar5211/ar5211_phy.c
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@ -81,7 +81,6 @@ HAL_RATE_TABLE ar5211_11b_table = {
#undef CCK #undef CCK
#undef TURBO #undef TURBO
const HAL_RATE_TABLE * const HAL_RATE_TABLE *
ar5211GetRateTable(struct ath_hal *ah, u_int mode) ar5211GetRateTable(struct ath_hal *ah, u_int mode)
{ {

1
sys/dev/ath/ath_hal/ar5211/ar5211_recv.c
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@ -51,7 +51,6 @@ ar5211SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)
HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
} }
/* /*
* Set Receive Enable bits. * Set Receive Enable bits.
*/ */

2
sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c
View File

@ -193,7 +193,6 @@ setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask); AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
} }
/* /*
* Free a tx DCU/QCU combination. * Free a tx DCU/QCU combination.
*/ */
@ -677,7 +676,6 @@ ar5211GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *
return AH_FALSE; return AH_FALSE;
} }
void void
ar5211SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link) ar5211SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link)
{ {

1
sys/dev/ath/ath_hal/ar5211/ar5211phy.h
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@ -48,7 +48,6 @@
#define AR_PHY_PLL_CTL_40 0x18 /* 40 MHz */ #define AR_PHY_PLL_CTL_40 0x18 /* 40 MHz */
#define AR_PHY_PLL_CTL_20 0x13 /* 20 MHz half rate 11a for emulation */ #define AR_PHY_PLL_CTL_20 0x13 /* 20 MHz half rate 11a for emulation */
#define AR_PHY_RX_DELAY 0x9914 /* PHY analog_power_on_time, in 100ns increments */ #define AR_PHY_RX_DELAY 0x9914 /* PHY analog_power_on_time, in 100ns increments */
#define AR_PHY_RX_DELAY_M 0x00003FFF /* Mask for delay from active assertion (wake up) */ #define AR_PHY_RX_DELAY_M 0x00003FFF /* Mask for delay from active assertion (wake up) */
/* to enable_receiver */ /* to enable_receiver */

1
sys/dev/ath/ath_hal/ar5211/ar5211reg.h
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@ -808,7 +808,6 @@
#define AR5211_USEC_RX_LAT_M 0x1F800000 /* Rx latency */ #define AR5211_USEC_RX_LAT_M 0x1F800000 /* Rx latency */
#define AR5211_USEC_RX_LAT_S 23 #define AR5211_USEC_RX_LAT_S 23
#define AR_BEACON_PERIOD 0x0000FFFF /* Beacon period in TU/msec */ #define AR_BEACON_PERIOD 0x0000FFFF /* Beacon period in TU/msec */
#define AR_BEACON_PERIOD_S 0 /* Byte offset of PERIOD start*/ #define AR_BEACON_PERIOD_S 0 /* Byte offset of PERIOD start*/
#define AR_BEACON_TIM 0x007F0000 /* Byte offset of TIM start */ #define AR_BEACON_TIM 0x007F0000 /* Byte offset of TIM start */

1
sys/dev/ath/ath_hal/ar5212/ar2425.c
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@ -492,7 +492,6 @@ ar2425getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
HALDEBUG(ah, HAL_DEBUG_RFPARAM, "<==%s\n", __func__); HALDEBUG(ah, HAL_DEBUG_RFPARAM, "<==%s\n", __func__);
} }
/* Same as 2413 set power table */ /* Same as 2413 set power table */
static HAL_BOOL static HAL_BOOL
ar2425SetPowerTable(struct ath_hal *ah, ar2425SetPowerTable(struct ath_hal *ah,

1
sys/dev/ath/ath_hal/ar5212/ar5111.c
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@ -336,7 +336,6 @@ ar5111SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
ar5212ModifyRfBuffer(rfReg, rfWaitS, 5, 19, 0); ar5212ModifyRfBuffer(rfReg, rfWaitS, 5, 19, 0);
ar5212ModifyRfBuffer(rfReg, rfWaitI, 5, 24, 0); ar5212ModifyRfBuffer(rfReg, rfWaitI, 5, 24, 0);
ar5212ModifyRfBuffer(rfReg, rfMaxTime, 2, 49, 0); ar5212ModifyRfBuffer(rfReg, rfMaxTime, 2, 49, 0);
} }
HAL_INI_WRITE_BANK(ah, ar5212Bank7_5111, rfReg, regWrites); HAL_INI_WRITE_BANK(ah, ar5212Bank7_5111, rfReg, regWrites);

1
sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c
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@ -27,7 +27,6 @@
#include "ar5212/ar5212reg.h" #include "ar5212/ar5212reg.h"
#include "ar5212/ar5212phy.h" #include "ar5212/ar5212phy.h"
/* /*
* Checks to see if an interrupt is pending on our NIC * Checks to see if an interrupt is pending on our NIC
* *

1
sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c
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@ -245,7 +245,6 @@ ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
(void) ar5212SetKeyCacheEntryMac(ah, entry, mac); (void) ar5212SetKeyCacheEntryMac(ah, entry, mac);
/* /*
* Write MIC entry according to new or old key layout. * Write MIC entry according to new or old key layout.
* The MISC_MODE register is assumed already set so * The MISC_MODE register is assumed already set so

1
sys/dev/ath/ath_hal/ar5212/ar5212_misc.c
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@ -1194,7 +1194,6 @@ ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
val &= ~ AR_PHY_RADAR_0_ENA; val &= ~ AR_PHY_RADAR_0_ENA;
if (IS_5413(ah)) { if (IS_5413(ah)) {
if (pe->pe_blockradar == 1) if (pe->pe_blockradar == 1)
OS_REG_SET_BIT(ah, AR_PHY_RADAR_2, OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_BLOCKOFDMWEAK); AR_PHY_RADAR_2_BLOCKOFDMWEAK);

1
sys/dev/ath/ath_hal/ar5212/ar5212_phy.c
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@ -129,7 +129,6 @@ HAL_RATE_TABLE ar5212_11b_table = {
}, },
}; };
/* Venice TODO: roundUpRate() is broken when the rate table does not represent rates /* Venice TODO: roundUpRate() is broken when the rate table does not represent rates
* in increasing order e.g. 5.5, 11, 6, 9. * in increasing order e.g. 5.5, 11, 6, 9.
* An average rate of 6 Mbps will currently map to 11 Mbps. * An average rate of 6 Mbps will currently map to 11 Mbps.

2
sys/dev/ath/ath_hal/ar5212/ar5212_reset.c
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@ -1192,7 +1192,6 @@ ar5212MacStop(struct ath_hal *ah)
return status; return status;
} }
/* /*
* Write the given reset bit mask into the reset register * Write the given reset bit mask into the reset register
*/ */
@ -1923,7 +1922,6 @@ ar5212SetSpurMitigation(struct ath_hal *ah,
#undef CHAN_TO_SPUR #undef CHAN_TO_SPUR
} }
/* /*
* Delta slope coefficient computation. * Delta slope coefficient computation.
* Required for OFDM operation. * Required for OFDM operation.

1
sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c
View File

@ -107,7 +107,6 @@ ar5212GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)
struct ath_hal_5212 *ahp = AH5212(ah); struct ath_hal_5212 *ahp = AH5212(ah);
HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
if (q >= pCap->halTotalQueues) { if (q >= pCap->halTotalQueues) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n", HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
__func__, q); __func__, q);

1
sys/dev/ath/ath_hal/ar5212/ar5212phy.h
View File

@ -78,7 +78,6 @@
#define AR_PHY_TSTDAC_CONST_Q_S 9 #define AR_PHY_TSTDAC_CONST_Q_S 9
#define AR_PHY_TSTDAC_CONST_I 0x000001FF #define AR_PHY_TSTDAC_CONST_I 0x000001FF
#define AR_PHY_SETTLING 0x9844 #define AR_PHY_SETTLING 0x9844
#define AR_PHY_SETTLING_AGC 0x0000007F #define AR_PHY_SETTLING_AGC 0x0000007F
#define AR_PHY_SETTLING_AGC_S 0 #define AR_PHY_SETTLING_AGC_S 0

1
sys/dev/ath/ath_hal/ar5212/ar5413.c
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@ -241,7 +241,6 @@ ar5413SetRfRegs(struct ath_hal *ah,
} else { } else {
ar5212ModifyRfBuffer(priv->Bank6Data, ob5GHz, 3, 247, 0); ar5212ModifyRfBuffer(priv->Bank6Data, ob5GHz, 3, 247, 0);
ar5212ModifyRfBuffer(priv->Bank6Data, db5GHz, 3, 244, 0); ar5212ModifyRfBuffer(priv->Bank6Data, db5GHz, 3, 244, 0);
} }
/* Bank 7 Setup */ /* Bank 7 Setup */

1
sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c
View File

@ -20,7 +20,6 @@
*/ */
#include "opt_ah.h" #include "opt_ah.h"
#ifdef AH_SUPPORT_AR5312 #ifdef AH_SUPPORT_AR5312
#include "ah.h" #include "ah.h"

1
sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c
View File

@ -129,5 +129,4 @@ ar5312GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
(void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO); (void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO);
} }
#endif /* AH_SUPPORT_AR5312 */ #endif /* AH_SUPPORT_AR5312 */

1
sys/dev/ath/ath_hal/ar5312/ar5312_interrupts.c
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@ -29,7 +29,6 @@
#include "ar5312/ar5312reg.h" #include "ar5312/ar5312reg.h"
#include "ar5312/ar5312phy.h" #include "ar5312/ar5312phy.h"
/* /*
* Checks to see if an interrupt is pending on our NIC * Checks to see if an interrupt is pending on our NIC
* *

2
sys/dev/ath/ath_hal/ar5312/ar5312_reset.c
View File

@ -827,12 +827,10 @@ ar5312MacReset(struct ath_hal *ah, unsigned int RCMask)
OS_REG_READ(ah, OS_REG_READ(ah,
(AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET)); (AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET));
} }
else else
#endif #endif
{ {
switch(wlanNum) { switch(wlanNum) {
case 0: case 0:
resetBB = AR5312_RC_BB0_CRES | AR5312_RC_WBB0_RES; resetBB = AR5312_RC_BB0_CRES | AR5312_RC_WBB0_RES;

2
sys/dev/ath/ath_hal/ar5312/ar5312reg.h
View File

@ -29,7 +29,6 @@
/* Register base addresses for modules which are not wmac modules */ /* Register base addresses for modules which are not wmac modules */
/* 531X has a fixed memory map */ /* 531X has a fixed memory map */
#define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val); #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val);
#define REG_READ(_reg) *((volatile uint32_t *)(_reg)) #define REG_READ(_reg) *((volatile uint32_t *)(_reg))
/* /*
@ -129,7 +128,6 @@
#define AR5312_RC_WMAC1_RES 0x00020000 /* Warm reset to WMAC1 */ #define AR5312_RC_WMAC1_RES 0x00020000 /* Warm reset to WMAC1 */
#define AR5312_RC_WBB1_RES 0x00040000 /* Warm reset to WBB */ #define AR5312_RC_WBB1_RES 0x00040000 /* Warm reset to WBB */
#define AR_RAD2112_SREV_MAJOR 0x40 /* 2112 Major Rev */ #define AR_RAD2112_SREV_MAJOR 0x40 /* 2112 Major Rev */
enum AR5312PowerMode { enum AR5312PowerMode {

1
sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c
View File

@ -128,5 +128,4 @@ ar5315GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
(void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO); (void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO);
} }
#endif /* AH_SUPPORT_2316 || AH_SUPPORT_2317 */ #endif /* AH_SUPPORT_2316 || AH_SUPPORT_2317 */

1
sys/dev/ath/ath_hal/ar5416/ar2133.c
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@ -473,7 +473,6 @@ ar2133GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
"NF calibrated [ctl] [chain 1] is %d\n", nf); "NF calibrated [ctl] [chain 1] is %d\n", nf);
nfarray[1] = nf; nfarray[1] = nf;
nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);

1
sys/dev/ath/ath_hal/ar5416/ar5416_ani.c
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@ -223,7 +223,6 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
return AH_FALSE; return AH_FALSE;
} }
switch (cmd) { switch (cmd) {
case HAL_ANI_NOISE_IMMUNITY_LEVEL: { case HAL_ANI_NOISE_IMMUNITY_LEVEL: {
u_int level = param; u_int level = param;

1
sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
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@ -721,7 +721,6 @@ ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
OS_REG_WRITE(ah, AR_PHY_TIMING11, new); OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
/* /*
* ============================================ * ============================================
* pilot mask 1 [31:0] = +6..-26, no 0 bin * pilot mask 1 [31:0] = +6..-26, no 0 bin

4
sys/dev/ath/ath_hal/ar5416/ar5416_cal.c
View File

@ -196,7 +196,6 @@ ar5416RunInitCals(struct ath_hal *ah, int init_cal_count)
} }
#endif #endif
/* /*
* AGC calibration for the AR5416, AR9130, AR9160, AR9280. * AGC calibration for the AR5416, AR9130, AR9160, AR9280.
*/ */
@ -623,7 +622,6 @@ ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan)
h = AH5416(ah)->ah_cal.nfCalHist; h = AH5416(ah)->ah_cal.nfCalHist;
HALDEBUG(ah, HAL_DEBUG_NFCAL, "CCA: "); HALDEBUG(ah, HAL_DEBUG_NFCAL, "CCA: ");
for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) { for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
/* Don't write to EXT radio CCA registers unless in HT/40 mode */ /* Don't write to EXT radio CCA registers unless in HT/40 mode */
/* XXX this check should really be cleaner! */ /* XXX this check should really be cleaner! */
if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan)) if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan))
@ -674,7 +672,6 @@ ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan)
* of next noise floor calibration the baseband does. * of next noise floor calibration the baseband does.
*/ */
for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) { for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
/* Don't write to EXT radio CCA registers unless in HT/40 mode */ /* Don't write to EXT radio CCA registers unless in HT/40 mode */
/* XXX this check should really be cleaner! */ /* XXX this check should really be cleaner! */
if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan)) if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan))
@ -781,7 +778,6 @@ ar5416SanitizeNF(struct ath_hal *ah, int16_t *nf)
} }
} }
/* /*
* Read the NF and check it against the noise floor threshold * Read the NF and check it against the noise floor threshold
* *

5
sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
View File

@ -386,7 +386,6 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
AR_PCU_MISC_MODE2_ENABLE_AGGWEP); AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
} }
/* /*
* disable seq number generation in hw * disable seq number generation in hw
*/ */
@ -1049,7 +1048,6 @@ ar5416WriteTxPowerRateRegisters(struct ath_hal *ah,
#undef POW_SM #undef POW_SM
} }
/************************************************************** /**************************************************************
* ar5416SetTransmitPower * ar5416SetTransmitPower
* *
@ -1657,7 +1655,6 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah))
ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i); ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i);
} }
if (AR_SREV_MERLIN_10_OR_LATER(ah)) { if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
@ -2804,7 +2801,6 @@ ar5416MarkPhyInactive(struct ath_hal *ah)
#define AR5416_HALF_RATE_USEC_44 21 /* ((44 / 2) - 1 ) */ #define AR5416_HALF_RATE_USEC_44 21 /* ((44 / 2) - 1 ) */
#define AR5416_QUARTER_RATE_USEC_44 10 /* ((44 / 4) - 1 ) */ #define AR5416_QUARTER_RATE_USEC_44 10 /* ((44 / 4) - 1 ) */
/* XXX What should these be for 40/44MHz clocks (and half/quarter) ? */ /* XXX What should these be for 40/44MHz clocks (and half/quarter) ? */
#define AR5416_RX_NON_FULL_RATE_LATENCY 63 #define AR5416_RX_NON_FULL_RATE_LATENCY 63
#define AR5416_TX_HALF_RATE_LATENCY 108 #define AR5416_TX_HALF_RATE_LATENCY 108
@ -2903,4 +2899,3 @@ ar5416SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan)
OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC, OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC,
AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec); AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec);
} }

1
sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c
View File

@ -243,4 +243,3 @@ ar5416RestoreSpectralConfig(struct ath_hal *ah, uint32_t restoreval)
} }
return; return;
} }

2
sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c
View File

@ -266,7 +266,6 @@ ar5416GetTxRatePower(struct ath_hal *ah, uint8_t rate, uint8_t tx_chainmask,
*/ */
if (AR_SREV_MERLIN_20_OR_LATER(ah) && if (AR_SREV_MERLIN_20_OR_LATER(ah) &&
ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
if (rate == 0x19 || rate == 0x1a || rate == 0x1b || if (rate == 0x19 || rate == 0x1a || rate == 0x1b ||
rate == (0x19 | 0x04) || rate == (0x1a | 0x04) || rate == (0x19 | 0x04) || rate == (0x1a | 0x04) ||
rate == (0x1b | 0x04)) { rate == (0x1b | 0x04)) {
@ -1114,7 +1113,6 @@ ar5416GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *
return AH_TRUE; return AH_TRUE;
} }
/* /*
* TX queue management routines - AR5416 and later chipsets * TX queue management routines - AR5416 and later chipsets
*/ */

1
sys/dev/ath/ath_hal/ar5416/ar5416desc.h
View File

@ -64,7 +64,6 @@ struct ar5416_rx_desc { /* rx desc has 2 control words + 9 status words */
uint32_t status8; uint32_t status8;
}; };
struct ar5416_desc { struct ar5416_desc {
uint32_t ds_link; /* link pointer */ uint32_t ds_link; /* link pointer */
uint32_t ds_data; /* data buffer pointer */ uint32_t ds_data; /* data buffer pointer */

2
sys/dev/ath/ath_hal/ar5416/ar5416reg.h
View File

@ -669,7 +669,6 @@
#define AR_XSREV_VERSION_OWL_PCI 0x0D #define AR_XSREV_VERSION_OWL_PCI 0x0D
#define AR_XSREV_VERSION_OWL_PCIE 0x0C #define AR_XSREV_VERSION_OWL_PCIE 0x0C
/* /*
* These are from ath9k/Atheros and assume an AR_SREV version mask * These are from ath9k/Atheros and assume an AR_SREV version mask
* of 0x07, rather than 0x0F which is being used in the FreeBSD HAL. * of 0x07, rather than 0x0F which is being used in the FreeBSD HAL.
@ -808,7 +807,6 @@
(AR_SREV_KIWI(_ah) && \ (AR_SREV_KIWI(_ah) && \
AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_13) AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_13)
/* Not yet implemented chips */ /* Not yet implemented chips */
#define AR_SREV_9271(_ah) 0 #define AR_SREV_9271(_ah) 0

1
sys/dev/ath/ath_hal/ar9001/ar9130_attach.c
View File

@ -243,7 +243,6 @@ ar9130Attach(uint16_t devid, HAL_SOFTC sc,
AH_PRIVATE(ah)->ah_currentRDext = AH_PRIVATE(ah)->ah_currentRDext =
ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL);
/* /*
* ah_miscMode is populated by ar5416FillCapabilityInfo() * ah_miscMode is populated by ar5416FillCapabilityInfo()
* starting from griffin. Set here to make sure that * starting from griffin. Set here to make sure that

1
sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
View File

@ -434,7 +434,6 @@ ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
OS_DELAY(1000); OS_DELAY(1000);
} }
/* /*
* Set PCIe workaround bits * Set PCIe workaround bits
* *

2
sys/dev/ath/ath_hal/ar9002/ar9280_olc.c
View File

@ -171,7 +171,6 @@ ar9280olcTemperatureCompensation(struct ath_hal *ah)
} }
} }
static int16_t static int16_t
ar9280ChangeGainBoundarySettings(struct ath_hal *ah, uint16_t *gb, ar9280ChangeGainBoundarySettings(struct ath_hal *ah, uint16_t *gb,
uint16_t numXpdGain, uint16_t pdGainOverlap_t2, int8_t pwr_table_offset, uint16_t numXpdGain, uint16_t pdGainOverlap_t2, int8_t pwr_table_offset,
@ -302,7 +301,6 @@ ar9280SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);
if (IS_EEP_MINOR_V2(ah)) { if (IS_EEP_MINOR_V2(ah)) {
pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap; pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap;
} else { } else {

1
sys/dev/ath/ath_hal/ar9002/ar9285.c
View File

@ -52,7 +52,6 @@ ar9285GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
"NF calibrated [ctl] [chain 0] is %d\n", nf); "NF calibrated [ctl] [chain 0] is %d\n", nf);
nfarray[0] = nf; nfarray[0] = nf;
nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);

2
sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c
View File

@ -150,5 +150,3 @@ ar9285BTCoexSetParameter(struct ath_hal *ah, u_int32_t type, u_int32_t value)
break; break;
} }
} }

1
sys/dev/ath/ath_hal/ar9002/ar9287_attach.c
View File

@ -146,7 +146,6 @@ ar9287Attach(uint16_t devid, HAL_SOFTC sc,
ah->ah_eepromdata = eepromdata; ah->ah_eepromdata = eepromdata;
} }
/* XXX override with 9280 specific state */ /* XXX override with 9280 specific state */
/* override 5416 methods for our needs */ /* override 5416 methods for our needs */
AH5416(ah)->ah_initPLL = ar9280InitPLL; AH5416(ah)->ah_initPLL = ar9280InitPLL;

1
sys/dev/ath/ath_hal/ar9002/ar9287_cal.c
View File

@ -41,7 +41,6 @@
#include "ar9002/ar9287_cal.h" #include "ar9002/ar9287_cal.h"
void void
ar9287PACal(struct ath_hal *ah, HAL_BOOL is_reset) ar9287PACal(struct ath_hal *ah, HAL_BOOL is_reset)
{ {

1
sys/dev/ath/ath_hal/ar9002/ar9287_reset.c
View File

@ -113,7 +113,6 @@ ar9287SetPowerCalTable(struct ath_hal *ah,
*pTxPowerIndexOffset = 0; *pTxPowerIndexOffset = 0;
} }
/* XXX hard-coded values? */ /* XXX hard-coded values? */
#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6

3
sys/dev/ath/ath_rate/amrr/amrr.c
View File

@ -145,7 +145,6 @@ ath_rate_getxtxrates(struct ath_softc *sc, struct ath_node *an,
rc[3].tries = amn->amn_tx_try3; rc[3].tries = amn->amn_tx_try3;
} }
void void
ath_rate_setupxtxdesc(struct ath_softc *sc, struct ath_node *an, ath_rate_setupxtxdesc(struct ath_softc *sc, struct ath_node *an,
struct ath_desc *ds, int shortPreamble, u_int8_t rix) struct ath_desc *ds, int shortPreamble, u_int8_t rix)
@ -217,7 +216,6 @@ node_reset(struct amrr_node *amn)
amn->amn_success_threshold = ath_rate_min_success_threshold; amn->amn_success_threshold = ath_rate_min_success_threshold;
} }
/** /**
* The code below assumes that we are dealing with hardware multi rate retry * The code below assumes that we are dealing with hardware multi rate retry
* I have no idea what will happen if you try to use this module with another * I have no idea what will happen if you try to use this module with another
@ -416,7 +414,6 @@ ath_rate_ctl(void *arg, struct ieee80211_node *ni)
} else { } else {
amn->amn_recovery = 0; amn->amn_recovery = 0;
} }
} }
if (is_enough (amn) || rix != amn->amn_rix) { if (is_enough (amn) || rix != amn->amn_rix) {
/* reset counters. */ /* reset counters. */

1
sys/dev/ath/ath_rate/onoe/onoe.c
View File

@ -197,7 +197,6 @@ ath_rate_update_rx_rssi(struct ath_softc *sc, struct ath_node *an, int rssi)
{ {
} }
static void static void
ath_rate_update(struct ath_softc *sc, struct ieee80211_node *ni, int rate) ath_rate_update(struct ath_softc *sc, struct ieee80211_node *ni, int rate)
{ {

2
sys/dev/ath/ath_rate/sample/sample.c
View File

@ -657,7 +657,6 @@ ath_rate_pick_seed_rate_ht(struct ath_softc *sc, struct ath_node *an,
#undef DOT11RATE #undef DOT11RATE
} }
void void
ath_rate_findrate(struct ath_softc *sc, struct ath_node *an, ath_rate_findrate(struct ath_softc *sc, struct ath_node *an,
int shortPreamble, size_t frameLen, int tid, int shortPreamble, size_t frameLen, int tid,
@ -1275,7 +1274,6 @@ ath_rate_update_rx_rssi(struct ath_softc *sc, struct ath_node *an, int rssi)
{ {
} }
static const struct txschedule *mrr_schedules[IEEE80211_MODE_MAX+2] = { static const struct txschedule *mrr_schedules[IEEE80211_MODE_MAX+2] = {
NULL, /* IEEE80211_MODE_AUTO */ NULL, /* IEEE80211_MODE_AUTO */
series_11a, /* IEEE80211_MODE_11A */ series_11a, /* IEEE80211_MODE_11A */

4
sys/dev/ath/if_ath.c
View File

@ -1221,7 +1221,6 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
IEEE80211_HTC_TXLDPC; IEEE80211_HTC_TXLDPC;
} }
device_printf(sc->sc_dev, device_printf(sc->sc_dev,
"[HT] %d RX streams; %d TX streams\n", rxs, txs); "[HT] %d RX streams; %d TX streams\n", rxs, txs);
} }
@ -4380,8 +4379,6 @@ ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq,
bf->bf_comp(sc, bf, 0); bf->bf_comp(sc, bf, 0);
} }
/* /*
* Process completed xmit descriptors from the specified queue. * Process completed xmit descriptors from the specified queue.
* Kick the packet scheduler if needed. This can occur from this * Kick the packet scheduler if needed. This can occur from this
@ -6103,7 +6100,6 @@ ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
taskqueue_unblock(sc->sc_tq); taskqueue_unblock(sc->sc_tq);
} else if (nstate == IEEE80211_S_INIT) { } else if (nstate == IEEE80211_S_INIT) {
/* Quiet time handling - ensure we resync */ /* Quiet time handling - ensure we resync */
memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));

1
sys/dev/ath/if_ath_ahb.c
View File

@ -336,7 +336,6 @@ static device_method_t ath_ahb_methods[] = {
DEVMETHOD(device_shutdown, ath_ahb_shutdown), DEVMETHOD(device_shutdown, ath_ahb_shutdown),
DEVMETHOD(device_suspend, ath_ahb_suspend), DEVMETHOD(device_suspend, ath_ahb_suspend),
DEVMETHOD(device_resume, ath_ahb_resume), DEVMETHOD(device_resume, ath_ahb_resume),
{ 0,0 } { 0,0 }
}; };
static driver_t ath_ahb_driver = { static driver_t ath_ahb_driver = {

1
sys/dev/ath/if_ath_beacon.c
View File

@ -777,7 +777,6 @@ ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap)
* insure cab frames are triggered by this beacon. * insure cab frames are triggered by this beacon.
*/ */
if (vap->iv_bcn_off.bo_tim[4] & 1) { if (vap->iv_bcn_off.bo_tim[4] & 1) {
/* NB: only at DTIM */ /* NB: only at DTIM */
ATH_TXQ_LOCK(&avp->av_mcastq); ATH_TXQ_LOCK(&avp->av_mcastq);
if (nmcastq) { if (nmcastq) {

1
sys/dev/ath/if_ath_beacon.h
View File

@ -53,4 +53,3 @@ extern void ath_beacon_proc(void *arg, int pending);
extern void ath_beacon_miss(struct ath_softc *sc); extern void ath_beacon_miss(struct ath_softc *sc);
#endif #endif

1
sys/dev/ath/if_ath_btcoex.c
View File

@ -481,4 +481,3 @@ bad:
free(outdata, M_TEMP); free(outdata, M_TEMP);
return (error); return (error);
} }

1
sys/dev/ath/if_ath_dfs.c
View File

@ -63,7 +63,6 @@ ath_dfs_modevent(module_t mod __unused, int type, void *data __unused)
default: default:
error = EOPNOTSUPP; error = EOPNOTSUPP;
break; break;
} }
return (error); return (error);
} }

1
sys/dev/ath/if_ath_drv.c
View File

@ -68,7 +68,6 @@ ath_modevent(module_t mod __unused, int type, void *data __unused)
default: default:
error = EOPNOTSUPP; error = EOPNOTSUPP;
break; break;
} }
return (error); return (error);
} }

2
sys/dev/ath/if_ath_ioctl.c
View File

@ -204,7 +204,6 @@ ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
} }
} }
ATH_LOCK(sc); ATH_LOCK(sc);
if (id != HAL_DIAG_REGS) if (id != HAL_DIAG_REGS)
ath_power_set_power_state(sc, HAL_PM_AWAKE); ath_power_set_power_state(sc, HAL_PM_AWAKE);
@ -306,4 +305,3 @@ ath_ioctl(struct ieee80211com *ic, u_long cmd, void *data)
return (ENOTTY); return (ENOTTY);
} }
} }

1
sys/dev/ath/if_ath_led.c
View File

@ -112,7 +112,6 @@ __FBSDID("$FreeBSD$");
* XXX TODO: move the LED sysctls here. * XXX TODO: move the LED sysctls here.
*/ */
/* /*
* Configure the hardware for software and LED blinking. * Configure the hardware for software and LED blinking.
* The user may choose to configure part of each, depending upon the * The user may choose to configure part of each, depending upon the

1
sys/dev/ath/if_ath_lna_div.c
View File

@ -1018,4 +1018,3 @@ div_comb_done:
antcomb->main_recv_cnt = 0; antcomb->main_recv_cnt = 0;
antcomb->alt_recv_cnt = 0; antcomb->alt_recv_cnt = 0;
} }

1
sys/dev/ath/if_ath_pci.c
View File

@ -383,7 +383,6 @@ static device_method_t ath_pci_methods[] = {
DEVMETHOD(device_shutdown, ath_pci_shutdown), DEVMETHOD(device_shutdown, ath_pci_shutdown),
DEVMETHOD(device_suspend, ath_pci_suspend), DEVMETHOD(device_suspend, ath_pci_suspend),
DEVMETHOD(device_resume, ath_pci_resume), DEVMETHOD(device_resume, ath_pci_resume),
{ 0,0 } { 0,0 }
}; };
static driver_t ath_pci_driver = { static driver_t ath_pci_driver = {

2
sys/dev/ath/if_ath_pci_devlist.h
View File

@ -663,7 +663,5 @@ static const struct pci_device_table ath_pci_id_table[] = {
/* PCI-E AR9565 (WB335) */ /* PCI-E AR9565 (WB335) */
{ PCI_VDEVICE(PCI_VENDOR_ID_ATHEROS, 0x0036), { PCI_VDEVICE(PCI_VENDOR_ID_ATHEROS, 0x0036),
.driver_data = ATH_PCI_BT_ANT_DIV }, .driver_data = ATH_PCI_BT_ANT_DIV },
{ 0 } { 0 }
}; };

1
sys/dev/ath/if_ath_rate.c
View File

@ -63,7 +63,6 @@ ath_rate_modevent(module_t mod __unused, int type, void *data __unused)
default: default:
error = EOPNOTSUPP; error = EOPNOTSUPP;
break; break;
} }
return (error); return (error);
} }

1
sys/dev/ath/if_ath_spectral.c
View File

@ -299,4 +299,3 @@ bad:
return (error); return (error);
} }

10
sys/dev/ath/if_ath_tx.c
View File

@ -1486,7 +1486,6 @@ ath_tx_should_swq_frame(struct ath_softc *sc, struct ath_node *an,
} }
} }
/* /*
* Transmit the given frame to the hardware. * Transmit the given frame to the hardware.
* *
@ -2519,7 +2518,6 @@ ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
sc->sc_txstart_cnt--; sc->sc_txstart_cnt--;
ATH_PCU_UNLOCK(sc); ATH_PCU_UNLOCK(sc);
/* Put the hardware back to sleep if required */ /* Put the hardware back to sleep if required */
ATH_LOCK(sc); ATH_LOCK(sc);
ath_power_restore_power_state(sc); ath_power_restore_power_state(sc);
@ -2713,7 +2711,6 @@ ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an,
tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head, tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head,
tid->baw_tail); tid->baw_tail);
#if 0 #if 0
assert(tid->tx_buf[cindex] == NULL); assert(tid->tx_buf[cindex] == NULL);
#endif #endif
@ -3225,7 +3222,6 @@ ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni,
*/ */
/* XXX TXQ locking */ /* XXX TXQ locking */
if (txq->axq_depth + txq->fifo.axq_depth == 0) { if (txq->axq_depth + txq->fifo.axq_depth == 0) {
bf = ATH_TID_FIRST(atid); bf = ATH_TID_FIRST(atid);
ATH_TID_REMOVE(atid, bf, bf_list); ATH_TID_REMOVE(atid, bf, bf_list);
@ -4312,7 +4308,6 @@ ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf)
ath_tx_default_comp(sc, bf, 0); ath_tx_default_comp(sc, bf, 0);
} }
/* /*
* This as it currently stands is a bit dumb. Ideally we'd just * This as it currently stands is a bit dumb. Ideally we'd just
* fail the frame the normal way and have it permanently fail * fail the frame the normal way and have it permanently fail
@ -5392,7 +5387,6 @@ ath_tx_tid_swq_depth_bytes(struct ath_softc *sc, struct ath_node *an,
* ever queue more than that in a single frame. * ever queue more than that in a single frame.
*/ */
TAILQ_FOREACH(bf, &tid->tid_q, bf_list) { TAILQ_FOREACH(bf, &tid->tid_q, bf_list) {
/* /*
* TODO: I'm not sure if we're going to hit cases where * TODO: I'm not sure if we're going to hit cases where
* no frames get sent because the list is empty. * no frames get sent because the list is empty.
@ -5612,7 +5606,6 @@ ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an,
* already points to the rest in the chain. * already points to the rest in the chain.
*/ */
ath_tx_setds_11n(sc, bf); ath_tx_setds_11n(sc, bf);
} }
queuepkt: queuepkt:
/* Set completion handler, multi-frame aggregate or not */ /* Set completion handler, multi-frame aggregate or not */
@ -5684,7 +5677,6 @@ ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an,
__func__, tid->tid); __func__, tid->tid);
for (;;) { for (;;) {
/* /*
* If the upper layers have paused the TID, don't * If the upper layers have paused the TID, don't
* queue any further packets. * queue any further packets.
@ -5916,7 +5908,6 @@ ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid)
* Is AMPDU-TX pending for the given TID? * Is AMPDU-TX pending for the given TID?
*/ */
/* /*
* Method to handle sending an ADDBA request. * Method to handle sending an ADDBA request.
* *
@ -6044,7 +6035,6 @@ ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
return r; return r;
} }
/* /*
* Stop ADDBA on a queue. * Stop ADDBA on a queue.
* *

1
sys/dev/ath/if_ath_tx.h
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@ -71,7 +71,6 @@
#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
/* extracting the seqno from buffer seqno */ /* extracting the seqno from buffer seqno */
#define SEQNO(_a) ((_a) >> IEEE80211_SEQ_SEQ_SHIFT) #define SEQNO(_a) ((_a) >> IEEE80211_SEQ_SEQ_SHIFT)

1
sys/dev/ath/if_ath_tx_edma.c
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@ -778,7 +778,6 @@ ath_edma_tx_proc(void *arg, int npending)
#endif #endif
ath_edma_tx_processq(sc, 1); ath_edma_tx_processq(sc, 1);
ATH_PCU_LOCK(sc); ATH_PCU_LOCK(sc);
sc->sc_txproc_cnt--; sc->sc_txproc_cnt--;
ATH_PCU_UNLOCK(sc); ATH_PCU_UNLOCK(sc);

1
sys/dev/ath/if_ath_tx_ht.c
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@ -1026,7 +1026,6 @@ ath_tx_form_aggr(struct ath_softc *sc, struct ath_node *an,
break; break;
} }
#endif #endif
} }
finish: finish:

1
sys/dev/ath/if_athioctl.h
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@ -193,7 +193,6 @@ struct ath_diag {
#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) #define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag) #define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag)
/* /*
* The rate control ioctl has to support multiple potential rate * The rate control ioctl has to support multiple potential rate
* control classes. For now, instead of trying to support an * control classes. For now, instead of trying to support an

1
sys/dev/ath/if_athvar.h
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@ -411,7 +411,6 @@ struct ath_txq {
#define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \ #define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \
MA_NOTOWNED) MA_NOTOWNED)
#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) #define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx)
#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) #define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx)
#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) #define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED)