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Remove unneeded type specifiers from 64-bit constants. The compiler

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infers their natural type from the constants' values.

Submitted by:	bde
MFC after:	3 days
This commit is contained in:
jhb 2010-03-22 15:08:26 +00:00
parent efc8278e10
commit 997a2351d1
2 changed files with 60 additions and 60 deletions
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60
sys/amd64/include/specialreg.h
View File

@ -321,16 +321,16 @@
#define MTRR_N64K 8 /* numbers of fixed-size entries */
#define MTRR_N16K 16
#define MTRR_N4K 64
#define MTRR_CAP_WC 0x0000000000000400UL
#define MTRR_CAP_FIXED 0x0000000000000100UL
#define MTRR_CAP_VCNT 0x00000000000000ffUL
#define MTRR_DEF_ENABLE 0x0000000000000800UL
#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL
#define MTRR_DEF_TYPE 0x00000000000000ffUL
#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL
#define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL
#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL
#define MTRR_PHYSMASK_VALID 0x0000000000000800UL
#define MTRR_CAP_WC 0x0000000000000400
#define MTRR_CAP_FIXED 0x0000000000000100
#define MTRR_CAP_VCNT 0x00000000000000ff
#define MTRR_DEF_ENABLE 0x0000000000000800
#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
#define MTRR_DEF_TYPE 0x00000000000000ff
#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
#define MTRR_PHYSBASE_TYPE 0x00000000000000ff
#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
#define MTRR_PHYSMASK_VALID 0x0000000000000800
/* Performance Control Register (5x86 only). */
#define PCR0 0x20
@ -360,31 +360,31 @@
#define MCG_STATUS_RIPV 0x00000001
#define MCG_STATUS_EIPV 0x00000002
#define MCG_STATUS_MCIP 0x00000004
#define MCG_CTL_ENABLE 0xffffffffffffffffUL
#define MCG_CTL_DISABLE 0x0000000000000000UL
#define MCG_CTL_ENABLE 0xffffffffffffffff
#define MCG_CTL_DISABLE 0x0000000000000000
#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
#define MC_STATUS_MCA_ERROR 0x000000000000ffffUL
#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL
#define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL
#define MC_STATUS_COR_COUNT 0x001fffc000000000UL /* If MCG_CAP_TES_P */
#define MC_STATUS_TES_STATUS 0x0060000000000000UL /* If MCG_CAP_TES_P */
#define MC_STATUS_AR 0x0080000000000000UL /* If MCG_CAP_CMCI_P */
#define MC_STATUS_S 0x0100000000000000UL /* If MCG_CAP_CMCI_P */
#define MC_STATUS_PCC 0x0200000000000000UL
#define MC_STATUS_ADDRV 0x0400000000000000UL
#define MC_STATUS_MISCV 0x0800000000000000UL
#define MC_STATUS_EN 0x1000000000000000UL
#define MC_STATUS_UC 0x2000000000000000UL
#define MC_STATUS_OVER 0x4000000000000000UL
#define MC_STATUS_VAL 0x8000000000000000UL
#define MC_MISC_RA_LSB 0x000000000000003fUL /* If MCG_CAP_SER_P */
#define MC_MISC_ADDRESS_MODE 0x00000000000001c0UL /* If MCG_CAP_SER_P */
#define MC_CTL2_THRESHOLD 0x0000000000003fffUL
#define MC_CTL2_CMCI_EN 0x0000000040000000UL
#define MC_STATUS_MCA_ERROR 0x000000000000ffff
#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
#define MC_STATUS_OTHER_INFO 0x01ffffff00000000
#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_TES_P */
#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_CMCI_P */
#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_CMCI_P */
#define MC_STATUS_PCC 0x0200000000000000
#define MC_STATUS_ADDRV 0x0400000000000000
#define MC_STATUS_MISCV 0x0800000000000000
#define MC_STATUS_EN 0x1000000000000000
#define MC_STATUS_UC 0x2000000000000000
#define MC_STATUS_OVER 0x4000000000000000
#define MC_STATUS_VAL 0x8000000000000000
#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
#define MC_CTL2_THRESHOLD 0x0000000000003fff
#define MC_CTL2_CMCI_EN 0x0000000040000000
/*
* The following four 3-byte registers control the non-cacheable regions.

60
sys/i386/include/specialreg.h
View File

@ -327,16 +327,16 @@
#define MTRR_N64K 8 /* numbers of fixed-size entries */
#define MTRR_N16K 16
#define MTRR_N4K 64
#define MTRR_CAP_WC 0x0000000000000400ULL
#define MTRR_CAP_FIXED 0x0000000000000100ULL
#define MTRR_CAP_VCNT 0x00000000000000ffULL
#define MTRR_DEF_ENABLE 0x0000000000000800ULL
#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400ULL
#define MTRR_DEF_TYPE 0x00000000000000ffULL
#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000ULL
#define MTRR_PHYSBASE_TYPE 0x00000000000000ffULL
#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000ULL
#define MTRR_PHYSMASK_VALID 0x0000000000000800ULL
#define MTRR_CAP_WC 0x0000000000000400
#define MTRR_CAP_FIXED 0x0000000000000100
#define MTRR_CAP_VCNT 0x00000000000000ff
#define MTRR_DEF_ENABLE 0x0000000000000800
#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
#define MTRR_DEF_TYPE 0x00000000000000ff
#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
#define MTRR_PHYSBASE_TYPE 0x00000000000000ff
#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
#define MTRR_PHYSMASK_VALID 0x0000000000000800
/*
* Cyrix configuration registers, accessible as IO ports.
@ -429,31 +429,31 @@
#define MCG_STATUS_RIPV 0x00000001
#define MCG_STATUS_EIPV 0x00000002
#define MCG_STATUS_MCIP 0x00000004
#define MCG_CTL_ENABLE 0xffffffffffffffffULL
#define MCG_CTL_DISABLE 0x0000000000000000ULL
#define MCG_CTL_ENABLE 0xffffffffffffffff
#define MCG_CTL_DISABLE 0x0000000000000000
#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
#define MC_STATUS_MCA_ERROR 0x000000000000ffffULL
#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000ULL
#define MC_STATUS_OTHER_INFO 0x01ffffff00000000ULL
#define MC_STATUS_COR_COUNT 0x001fffc000000000ULL /* If MCG_CAP_TES_P */
#define MC_STATUS_TES_STATUS 0x0060000000000000ULL /* If MCG_CAP_TES_P */
#define MC_STATUS_AR 0x0080000000000000ULL /* If MCG_CAP_CMCI_P */
#define MC_STATUS_S 0x0100000000000000ULL /* If MCG_CAP_CMCI_P */
#define MC_STATUS_PCC 0x0200000000000000ULL
#define MC_STATUS_ADDRV 0x0400000000000000ULL
#define MC_STATUS_MISCV 0x0800000000000000ULL
#define MC_STATUS_EN 0x1000000000000000ULL
#define MC_STATUS_UC 0x2000000000000000ULL
#define MC_STATUS_OVER 0x4000000000000000ULL
#define MC_STATUS_VAL 0x8000000000000000ULL
#define MC_MISC_RA_LSB 0x000000000000003fULL /* If MCG_CAP_SER_P */
#define MC_MISC_ADDRESS_MODE 0x00000000000001c0ULL /* If MCG_CAP_SER_P */
#define MC_CTL2_THRESHOLD 0x0000000000003fffULL
#define MC_CTL2_CMCI_EN 0x0000000040000000ULL
#define MC_STATUS_MCA_ERROR 0x000000000000ffff
#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
#define MC_STATUS_OTHER_INFO 0x01ffffff00000000
#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_TES_P */
#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_CMCI_P */
#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_CMCI_P */
#define MC_STATUS_PCC 0x0200000000000000
#define MC_STATUS_ADDRV 0x0400000000000000
#define MC_STATUS_MISCV 0x0800000000000000
#define MC_STATUS_EN 0x1000000000000000
#define MC_STATUS_UC 0x2000000000000000
#define MC_STATUS_OVER 0x4000000000000000
#define MC_STATUS_VAL 0x8000000000000000
#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
#define MC_CTL2_THRESHOLD 0x0000000000003fff
#define MC_CTL2_CMCI_EN 0x0000000040000000
/*
* The following four 3-byte registers control the non-cacheable regions.