- Fix a wrong R92C_USTIME_TSF register definition

- Fix intitial transmit rate to an 11g rate for the RTL8188EU
- Add a comment about response rate settings
This commit is contained in:
Kevin Lo 2015-05-08 09:01:00 +00:00
parent cf82d8112e
commit 997d8c7a89
2 changed files with 7 additions and 22 deletions

View File

@ -1195,7 +1195,7 @@ urtwn_efuse_read(struct urtwn_softc *sc)
uint8_t *rom = (uint8_t *)&sc->rom;
uint16_t addr = 0;
uint32_t reg;
uint8_t off, msk, vol;
uint8_t off, msk;
int i;
urtwn_efuse_switch_power(sc);
@ -1228,18 +1228,15 @@ urtwn_efuse_read(struct urtwn_softc *sc)
printf("\n");
}
#endif
/* Disable LDO 2.5V. */
vol = urtwn_read_1(sc, R92C_EFUSE_TEST + 3);
urtwn_write_1(sc, R92C_EFUSE_TEST + 3, vol & ~(0x80));
urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF);
}
static void
urtwn_efuse_switch_power(struct urtwn_softc *sc)
{
uint32_t reg;
if (sc->chip & URTWN_CHIP_88E)
urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON);
urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON);
reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
@ -1257,16 +1254,6 @@ urtwn_efuse_switch_power(struct urtwn_softc *sc)
urtwn_write_2(sc, R92C_SYS_CLKR,
reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
}
if (!(sc->chip & URTWN_CHIP_88E)) {
uint8_t vol;
/* Enable LDO 2.5V. */
vol = urtwn_read_1(sc, R92C_EFUSE_TEST + 3);
vol &= 0x0f;
vol |= 0x30;
urtwn_write_1(sc, R92C_EFUSE_TEST + 3, (vol | 0x80));
}
}
static int
@ -1905,10 +1892,7 @@ urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni,
txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8));
txd->txdw5 |= htole32(0x0001ff00);
/* Send data at OFDM54. */
if (sc->chip & URTWN_CHIP_88E)
txd->txdw5 |= htole32(0x13 & 0x3f);
else
txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
} else {
txd->txdw1 |= htole32(
SM(R92C_TXDW1_MACID, 0) |
@ -3364,6 +3348,7 @@ urtwn_init_locked(void *arg)
urtwn_rxfilter_init(sc);
/* Set response rate. */
reg = urtwn_read_4(sc, R92C_RRSR);
reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M);
urtwn_write_4(sc, R92C_RRSR, reg);

View File

@ -177,13 +177,13 @@
#define R92C_RD_NAV_NXT 0x544
#define R92C_NAV_PROT_LEN 0x546
#define R92C_BCN_CTRL 0x550
#define R92C_USTIME_TSF 0x551
#define R92C_MBID_NUM 0x552
#define R92C_DUAL_TSF_RST 0x553
#define R92C_BCN_INTERVAL 0x554
#define R92C_DRVERLYINT 0x558
#define R92C_BCNDMATIM 0x559
#define R92C_ATIMWND 0x55a
#define R92C_USTIME_TSF 0x55c
#define R92C_BCN_MAX_ERR 0x55d
#define R92C_RXTSF_OFFSET_CCK 0x55e
#define R92C_RXTSF_OFFSET_OFDM 0x55f