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loader: rewrite vidc_install_font

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Instead of trying to set reasonable register values, save significant
register values, then prepare for font upload and then restore
registers from saved data.

This seems to fix text mode for most cases where text mode breakage
was reported.
This commit is contained in:
Toomas Soome 2021-01-06 00:09:30 +02:00
parent deabdc6868
commit 99870c70ba
1 changed files with 34 additions and 32 deletions
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66
stand/i386/libi386/vidconsole.c
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@ -772,7 +772,7 @@ vga_cp437_to_uni(uint8_t c)
static void
vidc_install_font(void)
{
static uint8_t fsreg[8] = {0x0, 0x30, 0x5, 0x35, 0xa, 0x3a, 0xf, 0x3f};
uint8_t reg[7];
const uint8_t *from;
uint8_t volatile *to;
uint16_t c;
@ -788,34 +788,48 @@ vidc_install_font(void)
return;
/* Sync-reset the sequencer registers */
vga_set_seq(VGA_REG_BASE, 0x00, 0x01);
vga_set_seq(VGA_REG_BASE, VGA_SEQ_RESET, VGA_SEQ_RST_NAR);
reg[0] = vga_get_seq(VGA_REG_BASE, VGA_SEQ_MAP_MASK);
reg[1] = vga_get_seq(VGA_REG_BASE, VGA_SEQ_CLOCKING_MODE);
reg[2] = vga_get_seq(VGA_REG_BASE, VGA_SEQ_MEMORY_MODE);
reg[3] = vga_get_grc(VGA_REG_BASE, VGA_GC_READ_MAP_SELECT);
reg[4] = vga_get_grc(VGA_REG_BASE, VGA_GC_MODE);
reg[5] = vga_get_grc(VGA_REG_BASE, VGA_GC_MISCELLANEOUS);
reg[6] = vga_get_atr(VGA_REG_BASE, VGA_AC_MODE_CONTROL);
/* Screen off */
vga_set_seq(VGA_REG_BASE, VGA_SEQ_CLOCKING_MODE,
reg[1] | VGA_SEQ_CM_SO);
/*
* enable write to plane2, since fonts
* could only be loaded into plane2
*/
vga_set_seq(VGA_REG_BASE, 0x02, 0x04);
vga_set_seq(VGA_REG_BASE, VGA_SEQ_MAP_MASK, VGA_SEQ_MM_EM2);
/*
* sequentially access data in the bit map being
* selected by MapMask register (index 0x02)
*/
vga_set_seq(VGA_REG_BASE, 0x04, 0x07);
vga_set_seq(VGA_REG_BASE, VGA_SEQ_MEMORY_MODE, 0x07);
/* Sync-reset ended, and allow the sequencer to operate */
vga_set_seq(VGA_REG_BASE, 0x00, 0x03);
vga_set_seq(VGA_REG_BASE, VGA_SEQ_RESET,
VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR);
/*
* select plane 2 on Read Mode 0
*/
vga_set_grc(VGA_REG_BASE, 0x04, 0x02);
vga_set_grc(VGA_REG_BASE, VGA_GC_READ_MAP_SELECT, 0x02);
/*
* system addresses sequentially access data, follow
* Memory Mode register bit 2 in the sequencer
*/
vga_set_grc(VGA_REG_BASE, 0x05, 0x00);
vga_set_grc(VGA_REG_BASE, VGA_GC_MODE, 0x00);
/*
* set range of host memory addresses decoded by VGA
* hardware -- A0000h-BFFFFh (128K region)
*/
vga_set_grc(VGA_REG_BASE, 0x06, 0x00);
vga_set_grc(VGA_REG_BASE, VGA_GC_MISCELLANEOUS, 0x00);
/*
* This assumes 8x16 characters, which yield the traditional 80x25
@ -833,35 +847,23 @@ vidc_install_font(void)
*to++ = *from++;
}
vga_set_atr(VGA_REG_BASE, VGA_AC_MODE_CONTROL, reg[6]);
/* Sync-reset the sequencer registers */
vga_set_seq(VGA_REG_BASE, 0x00, 0x01);
/* enable write to plane 0 and 1 */
vga_set_seq(VGA_REG_BASE, 0x02, 0x03);
/*
* enable character map selection
* and odd/even addressing
*/
vga_set_seq(VGA_REG_BASE, 0x04, 0x03);
/*
* select font map
*/
vga_set_seq(VGA_REG_BASE, 0x03, fsreg[s]);
vga_set_seq(VGA_REG_BASE, VGA_SEQ_RESET, VGA_SEQ_RST_NAR);
vga_set_seq(VGA_REG_BASE, VGA_SEQ_MAP_MASK, reg[0]);
vga_set_seq(VGA_REG_BASE, VGA_SEQ_MEMORY_MODE, reg[2]);
/* Sync-reset ended, and allow the sequencer to operate */
vga_set_seq(VGA_REG_BASE, 0x00, 0x03);
vga_set_seq(VGA_REG_BASE, VGA_SEQ_RESET,
VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR);
/* restore graphic registers */
vga_set_grc(VGA_REG_BASE, VGA_GC_READ_MAP_SELECT, reg[3]);
vga_set_grc(VGA_REG_BASE, VGA_GC_MODE, reg[4]);
vga_set_grc(VGA_REG_BASE, VGA_GC_MISCELLANEOUS, (reg[5] & 0x03) | 0x0c);
/* select plane 0 */
vga_set_grc(VGA_REG_BASE, 0x04, 0x00);
/* enable odd/even addressing mode */
vga_set_grc(VGA_REG_BASE, 0x05, 0x10);
/*
* range of host memory addresses decoded by VGA
* hardware -- B8000h-BFFFFh (32K region)
*/
vga_set_grc(VGA_REG_BASE, 0x06, 0x0e);
/* enable all color plane */
vga_set_atr(VGA_REG_BASE, 0x12, 0x0f);
/* Screen on */
vga_set_seq(VGA_REG_BASE, VGA_SEQ_CLOCKING_MODE, reg[1] & 0xdf);
}
bool