Add support for ePWM submodule of PWMSS
ePWM is controlled by sysctl nodes dev.am335x_pwm.N.period, dev.am335x_pwm.N.dutyA and dev.am335x_pwm.N.dutyB that controls PWM period and duty cycles for channels A and B respectively. Period and duty cycle are measured in clock ticks. Default clock frequency for AM335x PWM subsystem is 100MHz
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@ -36,6 +36,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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@ -50,6 +51,9 @@ __FBSDID("$FreeBSD$");
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#include "am335x_pwm.h"
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#include "am335x_scm.h"
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/* In ticks */
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#define DEFAULT_PWM_PERIOD 1000
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#define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \
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@ -96,15 +100,24 @@ static struct resource_spec am335x_pwm_mem_spec[] = {
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#define ECCTL2_TSCTRSTOP_FREERUN (1 << 4)
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#define EPWM_TBCTL 0x00
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#define TBCTL_FREERUN (2 << 14)
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#define TBCTL_PHDIR_UP (1 << 13)
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#define TBCTL_PHDIR_DOWN (0 << 13)
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#define TBCTL_CLKDIV(x) ((x) << 10)
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#define TBCTL_CLKDIV_MASK (3 << 10)
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#define TBCTL_HSPCLKDIV(x) ((x) << 7)
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#define TBCTL_HSPCLKDIV_MASK (3 << 7)
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#define TBCTL_SYNCOSEL_DISABLED (3 << 4)
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#define TBCTL_PRDLD_SHADOW (0 << 3)
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#define TBCTL_PRDLD_IMMEDIATE (0 << 3)
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#define TBCTL_PHSEN_ENABLED (1 << 2)
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#define TBCTL_PHSEN_DISABLED (0 << 2)
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#define TBCTL_CTRMODE_MASK (3)
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#define TBCTL_CTRMODE_UP (0 << 0)
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#define TBCTL_CTRMODE_DOWN (1 << 0)
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#define TBCTL_CTRMODE_UPDOWN (2 << 0)
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#define TBCTL_CTRMODE_FREEZE (3 << 0)
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#define EPWM_TBSTS 0x02
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#define EPWM_TBPHSHR 0x04
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#define EPWM_TBPHS 0x06
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@ -130,10 +143,14 @@ static struct resource_spec am335x_pwm_mem_spec[] = {
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/* CMPCTL_LOADAMODE_ZERO */
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#define EPWM_AQCTLA 0x16
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#define EPWM_AQCTLB 0x18
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#define AQCTL_CAU_NONE (0 << 0)
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#define AQCTL_CAU_CLEAR (1 << 0)
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#define AQCTL_CAU_SET (2 << 0)
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#define AQCTL_CAU_TOGGLE (3 << 0)
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#define AQCTL_CBU_NONE (0 << 8)
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#define AQCTL_CBU_CLEAR (1 << 8)
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#define AQCTL_CBU_SET (2 << 8)
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#define AQCTL_CBU_TOGGLE (3 << 8)
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#define AQCTL_CAU_NONE (0 << 4)
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#define AQCTL_CAU_CLEAR (1 << 4)
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#define AQCTL_CAU_SET (2 << 4)
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#define AQCTL_CAU_TOGGLE (3 << 4)
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#define AQCTL_ZRO_NONE (0 << 0)
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#define AQCTL_ZRO_CLEAR (1 << 0)
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#define AQCTL_ZRO_SET (2 << 0)
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@ -141,6 +158,15 @@ static struct resource_spec am335x_pwm_mem_spec[] = {
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#define EPWM_AQSFRC 0x1a
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#define EPWM_AQCSFRC 0x1c
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/* Trip-Zone module */
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#define EPWM_TZCTL 0x28
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#define EPWM_TZFLG 0x2C
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/* High-Resolution PWM */
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#define EPWM_HRCTL 0x40
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#define HRCTL_DELMODE_BOTH 3
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#define HRCTL_DELMODE_FALL 2
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#define HRCTL_DELMODE_RISE 1
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static device_probe_t am335x_pwm_probe;
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static device_attach_t am335x_pwm_attach;
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static device_detach_t am335x_pwm_detach;
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@ -150,6 +176,13 @@ struct am335x_pwm_softc {
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struct mtx sc_mtx;
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struct resource *sc_mem_res[4];
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int sc_id;
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/* sysctl for configuration */
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struct sysctl_oid *sc_period_oid;
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struct sysctl_oid *sc_chanA_oid;
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struct sysctl_oid *sc_chanB_oid;
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uint32_t sc_pwm_period;
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uint32_t sc_pwm_dutyA;
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uint32_t sc_pwm_dutyB;
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};
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static device_method_t am335x_pwm_methods[] = {
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@ -208,6 +241,71 @@ am335x_pwm_config_ecas(int unit, int period, int duty)
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return (0);
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}
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static int
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am335x_pwm_sysctl_duty(SYSCTL_HANDLER_ARGS)
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{
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struct am335x_pwm_softc *sc = (struct am335x_pwm_softc*)arg1;
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int error;
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uint32_t duty;
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if (oidp == sc->sc_chanA_oid)
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duty = sc->sc_pwm_dutyA;
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else
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duty = sc->sc_pwm_dutyB;
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error = sysctl_handle_int(oidp, &duty, 0, req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (duty > sc->sc_pwm_period) {
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device_printf(sc->sc_dev, "Duty cycle can't be greater then period\n");
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return (EINVAL);
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}
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PWM_LOCK(sc);
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if (oidp == sc->sc_chanA_oid) {
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sc->sc_pwm_dutyA = duty;
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EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
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}
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else {
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sc->sc_pwm_dutyB = duty;
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EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
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}
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PWM_UNLOCK(sc);
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return (error);
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}
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static int
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am335x_pwm_sysctl_period(SYSCTL_HANDLER_ARGS)
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{
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struct am335x_pwm_softc *sc = (struct am335x_pwm_softc*)arg1;
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int error;
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uint32_t period;
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period = sc->sc_pwm_period;
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error = sysctl_handle_int(oidp, &period, 0, req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (period < 1)
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return (EINVAL);
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if ((period < sc->sc_pwm_dutyA) || (period < sc->sc_pwm_dutyB)) {
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device_printf(sc->sc_dev, "Period can't be less then duty cycle\n");
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return (EINVAL);
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}
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PWM_LOCK(sc);
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sc->sc_pwm_period = period;
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EPWM_WRITE2(sc, EPWM_TBPRD, period - 1);
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PWM_UNLOCK(sc);
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return (error);
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}
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static int
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am335x_pwm_probe(device_t dev)
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{
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@ -227,6 +325,8 @@ am335x_pwm_attach(device_t dev)
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uint32_t reg;
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phandle_t node;
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pcell_t did;
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struct sysctl_ctx_list *ctx;
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struct sysctl_oid *tree;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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@ -252,6 +352,47 @@ am335x_pwm_attach(device_t dev)
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reg |= (1 << sc->sc_id);
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ti_scm_reg_write_4(SCM_PWMSS_CTRL, reg);
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/* Init backlight interface */
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ctx = device_get_sysctl_ctx(sc->sc_dev);
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tree = device_get_sysctl_tree(sc->sc_dev);
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sc->sc_period_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"period", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
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am335x_pwm_sysctl_period, "I", "PWM period");
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sc->sc_chanA_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"dutyA", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
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am335x_pwm_sysctl_duty, "I", "Channel A duty cycles");
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sc->sc_chanB_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"dutyB", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
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am335x_pwm_sysctl_duty, "I", "Channel B duty cycles");
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/* CONFIGURE EPWM1 */
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reg = EPWM_READ2(sc, EPWM_TBCTL);
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reg &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK);
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EPWM_WRITE2(sc, EPWM_TBCTL, reg);
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sc->sc_pwm_period = DEFAULT_PWM_PERIOD;
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sc->sc_pwm_dutyA = 0;
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sc->sc_pwm_dutyB = 0;
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EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1);
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EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
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EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
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EPWM_WRITE2(sc, EPWM_AQCTLA, (AQCTL_ZRO_SET | AQCTL_CAU_CLEAR));
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EPWM_WRITE2(sc, EPWM_AQCTLB, (AQCTL_ZRO_SET | AQCTL_CBU_CLEAR));
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/* START EPWM */
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reg &= ~TBCTL_CTRMODE_MASK;
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reg |= TBCTL_CTRMODE_UP | TBCTL_FREERUN;
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EPWM_WRITE2(sc, EPWM_TBCTL, reg);
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EPWM_WRITE2(sc, EPWM_TZCTL, 0xf);
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reg = EPWM_READ2(sc, EPWM_TZFLG);
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return (0);
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fail:
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PWM_LOCK_DESTROY(sc);
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