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Don't use AR_PHY_MODE to setup half/quarter rate.

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I'm not sure where in the deep, distant past I found the AR_PHY_MODE
registers for half/quarter rate mode, but unfortunately that doesn't
seem to work "right" for non-AR9280 chips.

Specifically:

* don't touch AR_PHY_MODE
* set the PLL bits when configuring half/quarter rate

I've verified this on the AR9280 (5ghz fast clock) and the AR5416.

The AR9280 works in both half/quarter rate; the AR5416 unfortunately
only currently works at half rate.  It fails to calibrate on quarter rate.
This commit is contained in:
Adrian Chadd 2012-09-13 18:24:13 +00:00
parent 2ab4fdc460
commit 9b967f5d12
2 changed files with 4 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
View File

@ -746,19 +746,6 @@ ar5416SetRfMode(struct ath_hal *ah, const struct ieee80211_channel *chan)
AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
}
/*
* Set half/quarter mode flags if required.
*
* This doesn't change the IFS timings at all; that needs to
* be done as part of the MAC setup. Similarly, the PLL
* configuration also needs some changes for the half/quarter
* rate clock.
*/
if (IEEE80211_IS_CHAN_HALF(chan))
rfMode |= AR_PHY_MODE_HALF;
else if (IEEE80211_IS_CHAN_QUARTER(chan))
rfMode |= AR_PHY_MODE_QUARTER;
OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
}

4
sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
View File

@ -114,6 +114,10 @@ ar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
* Else, set PLL to 0x2850 to prevent reset-to-reset variation
*/
pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850;
if (IEEE80211_IS_CHAN_HALF(chan))
pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
else if (IEEE80211_IS_CHAN_QUARTER(chan))
pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
} else if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
if (chan != AH_NULL) {