diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
index 525de4b90a55..51ac0a1a2da5 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
@@ -746,19 +746,6 @@ ar5416SetRfMode(struct ath_hal *ah, const struct ieee80211_channel *chan)
 			AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
 	}
 
-	/*
-	 * Set half/quarter mode flags if required.
-	 *
-	 * This doesn't change the IFS timings at all; that needs to
-	 * be done as part of the MAC setup.  Similarly, the PLL
-	 * configuration also needs some changes for the half/quarter
-	 * rate clock.
-	 */
-	if (IEEE80211_IS_CHAN_HALF(chan))
-		rfMode |= AR_PHY_MODE_HALF;
-	else if (IEEE80211_IS_CHAN_QUARTER(chan))
-		rfMode |= AR_PHY_MODE_QUARTER;
-
 	OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
 }
 
diff --git a/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c b/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
index 36205d4eb610..6d550e90efb6 100644
--- a/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
+++ b/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
@@ -114,6 +114,10 @@ ar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
 		 * Else, set PLL to 0x2850 to prevent reset-to-reset variation 
 		 */
 		pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850;
+		if (IEEE80211_IS_CHAN_HALF(chan))
+			pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
+		else if (IEEE80211_IS_CHAN_QUARTER(chan))
+			pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
 	} else if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
 		pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
 		if (chan != AH_NULL) {