Convert U+00AD soft hyphen to - in Cavium Octeon SDK
Linux's copy of the Cavium SDK does not have these non-ASCII characters and this reduces noise in diffs when comparing the two. Sponsored by: The FreeBSD Foundation
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emaste
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9d8469f598
@ -87,7 +87,7 @@ typedef union
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PCIe memory space pointers in the LAST POINTERS block in the
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OUTBOUND, INBOUND, and EXTERNAL-ONLY cases. Must be zero in the
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INTERNAL-ONLY case. Must be zero on chips with PCI */
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cvmx_dma_engine_transfer_t type : 2; /**< Type A given PCI DMA transfer is either OUTBOUND (read from L2/DRAM,
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cvmx_dma_engine_transfer_t type : 2; /**< Type - A given PCI DMA transfer is either OUTBOUND (read from L2/DRAM,
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write into PCI / PCIe memory space), INBOUND (read from PCI / PCIe memory space, write
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into L2/DRAM), INTERNAL-ONLY (read from L2/DRAM, write into L2/DRAM), or
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EXTERNAL-ONLY (read from PCIe memory space, write into PCIe memory space). */
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@ -95,14 +95,14 @@ typedef union
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work-queue entry that is submitted by the hardware after completing the DMA;
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when WQP = 0, PTR (if non-zero) is a pointer to a byte in local memory that
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is written to 0 by the hardware after completing the DMA. */
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uint64_t c : 1; /**< C Counter. 1 = use counter 1, 0 = use counter 0.
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uint64_t c : 1; /**< C - Counter. 1 = use counter 1, 0 = use counter 0.
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The C bit selects between the two counters (NPEI_DMA_CNTS[DMA0,DMA1])
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that can optionally be updated after an OUTBOUND or EXTERNAL-ONLY
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transfer, and also selects between the two forced-interrupt bits
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(NPEI_INT_SUMn[DMA0_FI, DMA1_FI]) that can optionally be set after an
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OUTBOUND or EXTERNAL-ONLY transfer. C must be zero for INBOUND or
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INTERNAL-ONLY transfers. */
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uint64_t ca : 1; /**< CA Counter add.
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uint64_t ca : 1; /**< CA - Counter add.
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When CA = 1, the hardware updates the selected counter after it completes the
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PCI DMA OUTBOUND or EXTERNAL-ONLY Instruction.
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- If C = 0, PCIE_DMA_CNT0 is updated
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@ -117,13 +117,13 @@ typedef union
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When CA = 0, the hardware does not update any counters.
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For an INBOUND or INTERNAL-ONLY PCI DMA transfer, CA must never be
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set, and the hardware never adds to the counters. */
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uint64_t fi : 1; /**< FI Force interrupt.
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uint64_t fi : 1; /**< FI - Force interrupt.
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When FI is set for an OUTBOUND or EXTERNAL-ONLY transfer, the hardware
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sets a forced interrupt bit after it completes the PCI DMA Instruction. If C = 0,
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NPEI_INT_SUMn[DMA0_FI] is set, else NPEI_INT_SUMn[DMA1_FI] is set. For
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an INBOUND or INTERNAL-ONLY PCI DMA operation, FI must never be set,
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and the hardware never generates interrupts. */
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uint64_t ii : 1; /**< II Ignore the I bit (i.e. the I bit of the PCI DMA instruction local pointer).
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uint64_t ii : 1; /**< II- Ignore the I bit (i.e. the I bit of the PCI DMA instruction local pointer).
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For OUTBOUND transfers when II = 1, ignore the I bit and the FL bit in the
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DMA HDR alone determines whether the hardware frees any/all of the local
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buffers in the FIRST POINTERS area:
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@ -134,7 +134,7 @@ typedef union
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- when (FL I) is true, the hardware frees the local buffer when II=0.
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For INBOUND, INTERNAL-ONLY, and EXTERNAL-ONLY PCI DMA transfers,
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II must never be set, and local buffers are never freed. */
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uint64_t fl : 1; /**< FL Free local buffer.
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uint64_t fl : 1; /**< FL - Free local buffer.
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When FL = 1, for an OUTBOUND operation, it indicates that the local buffers in
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the FIRST BUFFERS area should be freed.
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If II = 1, the FL bit alone indicates whether the local buffer should be freed:
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@ -145,7 +145,7 @@ typedef union
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- when (FL I) is true, the hardware frees the local buffer when II=0.
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For an INBOUND, INTERNAL-ONLY, or EXTERNAL-ONLY PCI DMA transfer,
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FL must never be set, and local buffers are never freed. */
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uint64_t nlst : 4; /**< NLST Number Last pointers.
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uint64_t nlst : 4; /**< NLST - Number Last pointers.
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The number of pointers in the LAST POINTERS area.
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In the INBOUND, OUTBOUND, and EXTERNAL-ONLY cases, the LAST
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POINTERS area contains PCI components, and the number of 64-bit words
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@ -156,7 +156,7 @@ typedef union
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- HDR.NLST
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Note that the sum of the number of 64-bit words in the LAST POINTERS and
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FIRST POINTERS area must never exceed 31. */
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uint64_t nfst : 4; /**< NFST Number First pointers.
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uint64_t nfst : 4; /**< NFST - Number First pointers.
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The number of pointers in the FIRST POINTERS area.
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In the INBOUND, OUTBOUND, and INTERNAL-ONLY cases, the FIRST
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POINTERS area contains local pointers, and the number of 64-bit words required
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@ -166,7 +166,7 @@ typedef union
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components, and the number of 64-bit words required in the FIRST POINTERS
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area is:
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- HDR.NFST + ((HDR.NFST + 3)/4) where the division removes the fraction. */
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uint64_t addr : 40; /**< PTR Pointer, either a work-queue-entry pointer (when WQP = 1) or a local
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uint64_t addr : 40; /**< PTR - Pointer, either a work-queue-entry pointer (when WQP = 1) or a local
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memory pointer (WQP = 0).
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When WQP = 1 and PTR 0x0, the hardware inserts the work-queue entry
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indicated by PTR into a POW input queue after the PCI DMA operation is
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@ -186,12 +186,12 @@ typedef union
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uint64_t u64;
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struct
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{
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uint64_t i : 1; /**< I Invert free.
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uint64_t i : 1; /**< I - Invert free.
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This bit gives the software the ability to free buffers independently for an
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OUTBOUND PCI DMA transfer. I is not used by the hardware when II is set. I
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must not be set, and buffers are never freed, for INBOUND, INTERNAL-ONLY,
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and EXTERNAL-ONLY PCI DMA transfers. */
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uint64_t back : 4; /**< Back Backup amount.
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uint64_t back : 4; /**< Back - Backup amount.
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Allows the start of a buffer that is to be freed during an OUTBOUND transfer to
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be different from the ptr value. Back specifies the amount to subtract from the
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pointer to reach the start when freeing a buffer.
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@ -200,13 +200,13 @@ typedef union
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Back is only used by the hardware when the buffer corresponding to ptr is freed.
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Back must be 0x0, and buffers are never freed, for INBOUND, INTERNAL-ONLY,
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and EXTERNAL-ONLY PCI DMA transfers. */
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uint64_t pool : 3; /**< Pool Free pool.
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uint64_t pool : 3; /**< Pool - Free pool.
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Specifies which pool (of the eight hardware-managed FPA free pools) receives the
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buffer associated with ptr when freed during an OUTBOUND transfer.
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Pool is only used when the buffer corresponding to ptr is freed. Pool must be 0x0,
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and buffers are never freed, for INBOUND, INTERNAL-ONLY, and EXTERNAL-ONLY
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PCI DMA transfers. */
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uint64_t f : 1; /**< F Full-block writes are allowed.
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uint64_t f : 1; /**< F - Full-block writes are allowed.
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When set, the hardware is permitted to write all the bytes in the cache blocks
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covered by ptr, ptr + Size - 1. This can improve memory system performance
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when the write misses in the L2 cache.
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@ -218,12 +218,12 @@ typedef union
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F must not be set for local pointers that are not written to:
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- The local pointers in the FIRST POINTERS area for OUTBOUND and
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INTERNAL-ONLY transfers. */
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uint64_t a : 1; /**< A Allocate L2.
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uint64_t a : 1; /**< A - Allocate L2.
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This is a hint to the hardware that the cache blocks should be allocated in the L2
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cache (if they were not already). */
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uint64_t l : 1; /**< L Little-endian.
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uint64_t l : 1; /**< L - Little-endian.
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When L is set, the data at ptr is in little-endian format rather than big-endian. */
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uint64_t size : 13; /**< Size Size in bytes of the contiguous space specified by ptr. A Size value of 0 is
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uint64_t size : 13; /**< Size - Size in bytes of the contiguous space specified by ptr. A Size value of 0 is
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illegal. Note that the sum of the sizes in the FIRST POINTERS area must always
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exactly equal the sum of the sizes/lengths in the LAST POINTERS area:
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- In the OUTBOUND and INBOUND cases, the HDR.NFST size fields in the
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@ -120,11 +120,11 @@ typedef struct
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multicast (unknown L2 multicast and IPMC) packets. This field is used
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when OPCODE is 011 or 100 Semantics of PFM bits are as follows;
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For registered L2 multicast packets:
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PFM= 0 Flood to VLAN
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PFM= 1 or 2 Send to group members in the L2MC table
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PFM= 0 - Flood to VLAN
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PFM= 1 or 2 - Send to group members in the L2MC table
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For unregistered L2 multicast packets:
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PFM= 0 or 1 Flood to VLAN
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PFM= 2 Drop the packet */
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PFM= 0 or 1 - Flood to VLAN
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PFM= 2 - Drop the packet */
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uint32_t src_port_tgid : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed
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on, else it represents the physical port the packet ingressed on. */
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uint32_t dst_port : 5; /**< Port number of destination port on which the packet needs to egress. */
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@ -138,10 +138,10 @@ typedef struct
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uint32_t cng_low : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following
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encodings are to make it backward compatible:
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[CNG_HIGH, CNG_LOW] - COLOR
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[0, 0] Packet is green
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[0, 1] Packet is red
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[1, 1] Packet is yellow
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[1, 0] Undefined */
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[0, 0] - Packet is green
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[0, 1] - Packet is red
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[1, 1] - Packet is yellow
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[1, 0] - Undefined */
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uint32_t dst_modid_low : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */
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} s;
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} dw1;
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@ -273,11 +273,11 @@ typedef struct
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multicast (unknown L2 multicast and IPMC) packets. This field is used
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when OPCODE is 011 or 100 Semantics of PFM bits are as follows;
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For registered L2 multicast packets:
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PFM= 0 Flood to VLAN
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PFM= 1 or 2 Send to group members in the L2MC table
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PFM= 0 - Flood to VLAN
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PFM= 1 or 2 - Send to group members in the L2MC table
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For unregistered L2 multicast packets:
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PFM= 0 or 1 Flood to VLAN
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PFM= 2 Drop the packet */
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PFM= 0 or 1 - Flood to VLAN
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PFM= 2 - Drop the packet */
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uint32_t src_t : 1; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed
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on, else it represents the physical port the packet ingressed on. */
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uint32_t reserved_11_12 : 2;
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@ -722,8 +722,8 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
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/* Setup BAR2 attributes */
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/* Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM]) */
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/* PTLP_RO,CTLP_RO should normally be set (except for debug). */
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/* WAIT_COM=0 will likely work for all applications. */
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/* - PTLP_RO,CTLP_RO should normally be set (except for debug). */
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/* - WAIT_COM=0 will likely work for all applications. */
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/* Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]) */
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if (pcie_port)
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{
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@ -1139,8 +1139,8 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
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/* Setup BAR2 attributes */
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/* Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM]) */
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/* PTLP_RO,CTLP_RO should normally be set (except for debug). */
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/* WAIT_COM=0 will likely work for all applications. */
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/* - PTLP_RO,CTLP_RO should normally be set (except for debug). */
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/* - WAIT_COM=0 will likely work for all applications. */
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/* Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]) */
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pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));
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pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1*/
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@ -125,7 +125,7 @@ typedef union
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{
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uint64_t reserved_58_63 : 6; /**< Must be zero */
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uint64_t fw : 1; /**< When set, indicates that RAD can modify any byte in any (128B) cache line touched
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by L2/DRAM addresses OWORD[PTR] through OWORD[PTR]+CWORD[SIZE]1.
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by L2/DRAM addresses OWORD[PTR] through OWORD[PTR]+CWORD[SIZE]-1.
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Setting OWORD[FW] can improve hardware performance, as some DRAM loads can
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be avoided on L2 cache misses. The Q OWORD[FW] must not be set when
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CWORD[Q_CMP] is set, and the P OWORD[FW] must not be set when
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