From 9d9c9630befaea330c98a1be884688a09efd0547 Mon Sep 17 00:00:00 2001 From: ian Date: Fri, 1 Aug 2014 23:06:38 +0000 Subject: [PATCH] Use atomic_load/store_64() in the arm implementation of counter(9), and remove the XXX comments about non-atomic access to the counters. --- sys/arm/include/counter.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/sys/arm/include/counter.h b/sys/arm/include/counter.h index a6dfa8ef875b..c4da91f7a14b 100644 --- a/sys/arm/include/counter.h +++ b/sys/arm/include/counter.h @@ -30,6 +30,7 @@ #define __MACHINE_COUNTER_H__ #include +#include #ifdef INVARIANTS #include #endif @@ -38,12 +39,13 @@ #define counter_exit() critical_exit() #ifdef IN_SUBR_COUNTER_C -/* XXXKIB non-atomic 64bit read */ + static inline uint64_t counter_u64_read_one(uint64_t *p, int cpu) { - return (*(uint64_t *)((char *)p + sizeof(struct pcpu) * cpu)); + return (atomic_load_64((uint64_t *)((char *)p + sizeof(struct pcpu) * + cpu))); } static inline uint64_t @@ -59,13 +61,12 @@ counter_u64_fetch_inline(uint64_t *p) return (r); } -/* XXXKIB non-atomic 64bit store, might interrupt increment */ static void counter_u64_zero_one_cpu(void *arg) { - *((uint64_t *)((char *)arg + sizeof(struct pcpu) * - PCPU_GET(cpuid))) = 0; + atomic_store_64((uint64_t *)((char *)arg + sizeof(struct pcpu) * + PCPU_GET(cpuid)), 0); } static inline void @@ -79,7 +80,7 @@ counter_u64_zero_inline(counter_u64_t c) #define counter_u64_add_protected(c, inc) do { \ CRITICAL_ASSERT(curthread); \ - *(uint64_t *)zpcpu_get(c) += (inc); \ + atomic_add_64((uint64_t *)zpcpu_get(c), (inc)); \ } while (0) static inline void