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Add Dual LVD bus (1280) support

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This commit is contained in:
mjacob 1999-12-16 05:42:02 +00:00
parent 263f5e1e45
commit 9e5f68a92b
7 changed files with 257 additions and 159 deletions
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107
sys/dev/isp/isp.c
View File

@ -155,7 +155,7 @@ isp_reset(isp)
DISABLE_INTS(isp);
/*
* Put the board into PAUSE mode.
* Put the board into PAUSE mode (so we can read the SXP registers).
*/
ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
@ -171,37 +171,68 @@ isp_reset(isp)
default:
break;
}
} else if (IS_12X0(isp)) {
revname = "12X0";
} else if (IS_1240(isp)) {
sdparam *sdp = isp->isp_param;
revname = "1240";
isp->isp_clock = 60;
} else if (IS_1080(isp)) {
sdp->isp_ultramode = 1;
sdp++;
sdp->isp_ultramode = 1;
/*
* XXX: Should probably do some bus sensing.
*/
} else if (IS_ULTRA2(isp)) {
static char *m = "%s: bus %d is in %s Mode\n";
u_int16_t l;
sdparam *sdp = isp->isp_param;
revname = "1080";
isp->isp_clock = 100;
revname = "1080";
l = ISP_READ(isp, SXP_PINS_DIFF) & ISP1080_MODE_MASK;
switch (l) {
case ISP1080_LVD_MODE:
sdp->isp_lvdmode = 1;
PRINTF("%s: LVD Mode\n", isp->isp_name);
CFGPRINTF(m, isp->isp_name, 0, "LVD");
break;
case ISP1080_HVD_MODE:
sdp->isp_diffmode = 1;
CFGPRINTF("%s: Differential Mode\n", isp->isp_name);
CFGPRINTF(m, isp->isp_name, 0, "Differential");
break;
case ISP1080_SE_MODE:
sdp->isp_ultramode = 1;
CFGPRINTF("%s: Single-Ended Mode\n", isp->isp_name);
CFGPRINTF(m, isp->isp_name, 0, "Single-Ended");
break;
default:
/*
* Hmm. Up in a wierd mode. This means all SCSI I/O
* buffer lines are tristated, so we're in a lot of
* trouble if we don't set things up right.
*/
PRINTF("%s: Illegal Mode 0x%x\n", isp->isp_name, l);
CFGPRINTF("%s: unknown mode on bus %d (0x%x)\n",
isp->isp_name, 0, l);
break;
}
if (IS_1280(isp)) {
sdp++;
revname[1] = '2';
l = ISP_READ(isp, SXP_PINS_DIFF|SXP_BANK1_SELECT);
l &= ISP1080_MODE_MASK;
switch(l) {
case ISP1080_LVD_MODE:
sdp->isp_lvdmode = 1;
CFGPRINTF(m, isp->isp_name, 1, "LVD");
break;
case ISP1080_HVD_MODE:
sdp->isp_diffmode = 1;
CFGPRINTF(m, isp->isp_name, 1, "Differential");
break;
case ISP1080_SE_MODE:
sdp->isp_ultramode = 1;
CFGPRINTF(m, isp->isp_name, 1, "Single-Ended");
break;
default:
CFGPRINTF("%s: unknown mode on bus %d (0x%x)\n",
isp->isp_name, 1, l);
break;
}
}
} else {
sdparam *sdp = isp->isp_param;
i = ISP_READ(isp, BIU_CONF0) & BIU_CONF0_HW_MASK;
@ -241,7 +272,7 @@ isp_reset(isp)
isp->isp_clock = 60;
break;
case 6:
revname = "1040C(?)";
revname = "1040C";
isp->isp_type = ISP_HA_SCSI_1040C;
isp->isp_clock = 60;
break;
@ -609,7 +640,7 @@ isp_init(isp)
* Must do this first to get defaults established.
*/
isp_setdfltparm(isp, 0);
if (IS_12X0(isp)) {
if (IS_DUALBUS(isp)) {
isp_setdfltparm(isp, 1);
}
@ -629,7 +660,7 @@ isp_scsi_init(isp)
sdp_chan0 = isp->isp_param;
sdp_chan1 = sdp_chan0;
if (IS_12X0(isp)) {
if (IS_DUALBUS(isp)) {
sdp_chan1++;
}
@ -724,7 +755,7 @@ isp_scsi_init(isp)
/* now do per-channel settings */
isp_scsi_channel_init(isp, 0);
if (IS_12X0(isp))
if (IS_DUALBUS(isp))
isp_scsi_channel_init(isp, 1);
/*
@ -761,7 +792,7 @@ isp_scsi_init(isp)
* Turn on Fast Posting, LVD transitions
*/
if (IS_1080(isp) ||
if (IS_ULTRA2(isp) ||
ISP_FW_REVX(isp->isp_fwrev) >= ISP_FW_REV(7, 55, 0)) {
mbs.param[0] = MBOX_SET_FW_FEATURES;
#ifndef ISP_NO_FASTPOST_SCSI
@ -769,7 +800,7 @@ isp_scsi_init(isp)
#else
mbs.param[1] = 0;
#endif
if (IS_1080(isp))
if (IS_ULTRA2(isp))
mbs.param[1] |= FW_FEATURE_LVD_NOTIFY;
if (mbs.param[1] != 0) {
isp_mboxcmd(isp, &mbs);
@ -827,7 +858,7 @@ isp_scsi_channel_init(isp, channel)
* If we're in LVD mode, then we pretty much should
* only disable tagged queuing.
*/
if (IS_1080(isp) && sdp->isp_lvdmode) {
if (IS_ULTRA2(isp) && sdp->isp_lvdmode) {
sdf = DPARM_DEFAULT & ~DPARM_TQING;
} else {
sdf = DPARM_SAFE_DFLT;
@ -1920,7 +1951,7 @@ ispscsicmd(xs)
* than which we got here to send a command to.
*/
if (isp->isp_sendmarker) {
u_int8_t n = (IS_12X0(isp)? 2: 1);
u_int8_t n = (IS_DUALBUS(isp)? 2: 1);
/*
* Check ports to send markers for...
*/
@ -2446,12 +2477,7 @@ isp_parse_async(isp, mbox)
int bus;
u_int32_t fast_post_handle = 0;
/*
* It is not documented anywhere that bus is always in OUTMAILBOX6
* for dual bus cards- and we don't have the h/w to prove it either,
* So we'll just assume......
*/
if (IS_1080(isp) || IS_12X0(isp)) {
if (IS_DUALBUS(isp)) {
bus = ISP_READ(isp, OUTMAILBOX6);
} else {
bus = 0;
@ -2705,8 +2731,9 @@ isp_parse_status(isp, sp, xs)
break;
case RQCS_RESET_OCCURRED:
IDPRINTF(2, ("%s: bus reset destroyed command for target %d "
"lun %d\n", isp->isp_name, XS_TGT(xs), XS_LUN(xs)));
IDPRINTF(2, ("%s: bus %d reset destroyed command for target %d "
"lun %d\n", isp->isp_name, XS_CHANNEL(xs), XS_TGT(xs),
XS_LUN(xs)));
/*
* XXX: Get port number for bus
*/
@ -3214,7 +3241,7 @@ isp_mboxcmd(isp, mbp)
* XXX Eventually will be fixed by converting register write/read
* XXX counts to bitmasks.
*/
if (IS_12X0(isp)) {
if (IS_DUALBUS(isp)) {
switch (opcode) {
case MBOX_GET_RETRY_COUNT:
case MBOX_SET_RETRY_COUNT:
@ -3339,7 +3366,7 @@ isp_mboxcmd(isp, mbp)
* Pick up output parameters. Special case some of the readbacks
* for the dual port SCSI cards.
*/
if (IS_12X0(isp)) {
if (IS_DUALBUS(isp)) {
switch (opcode) {
case MBOX_GET_RETRY_COUNT:
case MBOX_SET_RETRY_COUNT:
@ -3514,7 +3541,7 @@ isp_dumpregs(isp, msg)
PRINTF(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
ISP_READ(isp, SXP_INTERRUPT),
ISP_READ(isp, SXP_GROSS_ERR),
ISP_READ(isp, SXP_PINS_CONTROL));
ISP_READ(isp, SXP_PINS_CTRL));
ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
}
PRINTF(" mbox regs: %x %x %x %x %x\n",
@ -3755,14 +3782,14 @@ isp_setdfltparm(isp, channel)
IDPRINTF(2, ("could not GET ACT NEG STATE\n"));
sdp_chan0->isp_req_ack_active_neg = 1;
sdp_chan0->isp_data_line_active_neg = 1;
if (IS_12X0(isp)) {
if (IS_DUALBUS(isp)) {
sdp_chan1->isp_req_ack_active_neg = 1;
sdp_chan1->isp_data_line_active_neg = 1;
}
} else {
sdp_chan0->isp_req_ack_active_neg = (mbs.param[1] >> 4) & 0x1;
sdp_chan0->isp_data_line_active_neg = (mbs.param[1] >> 5) & 0x1;
if (IS_12X0(isp)) {
if (IS_DUALBUS(isp)) {
sdp_chan1->isp_req_ack_active_neg =
(mbs.param[2] >> 4) & 0x1;
sdp_chan1->isp_data_line_active_neg =
@ -3787,7 +3814,7 @@ isp_setdfltparm(isp, channel)
ISP_10M_SYNCPARMS >> 8;
sdp->isp_devparam[tgt].sync_period =
ISP_10M_SYNCPARMS & 0xff;
} else if (IS_1080(isp)) {
} else if (IS_ULTRA2(isp)) {
sdp->isp_devparam[tgt].sync_offset =
ISP_40M_SYNCPARMS >> 8;
sdp->isp_devparam[tgt].sync_period =
@ -3941,7 +3968,7 @@ isp_read_nvram(isp)
if (IS_FC(isp)) {
amt = ISP2100_NVRAM_SIZE;
minversion = 1;
} else if (IS_1080(isp) || IS_12X0(isp)) {
} else if (IS_ULTRA2(isp)) {
amt = ISP1080_NVRAM_SIZE;
minversion = 0;
} else {
@ -3981,10 +4008,10 @@ isp_read_nvram(isp)
return (-1);
}
if (IS_1080(isp) || IS_12X0(isp)) {
if (IS_ULTRA2(isp)) {
int bus;
sdparam *sdp = (sdparam *) isp->isp_param;
for (bus = 0; bus < (IS_1080(isp)? 1 : 2); bus++, sdp++) {
for (bus = 0; bus < (IS_DUALBUS(isp)? 2 : 1); bus++, sdp++) {
sdp->isp_fifo_threshold =
ISP1080_NVRAM_FIFO_THRESHOLD(nvram_data);
@ -4344,7 +4371,7 @@ isp_rdnvram_word(isp, wo, rp)
wo &= ((ISP2100_NVRAM_SIZE >> 1) - 1);
rqst = (ISP_NVRAM_READ << 8) | wo;
cbits = 10;
} else if (IS_1080(isp) || IS_12X0(isp)) {
} else if (IS_ULTRA2(isp)) {
wo &= ((ISP1080_NVRAM_SIZE >> 1) - 1);
rqst = (ISP_NVRAM_READ << 8) | wo;
cbits = 10;

6
sys/dev/isp/isp_freebsd.c
View File

@ -40,7 +40,9 @@ static void isp_action(struct cam_sim *, union ccb *);
static void isp_relsim(void *);
/* #define ISP_LUN0_ONLY 1 */
#ifdef CAMDEBUG
#ifdef DEBUG
int isp_debug = 2;
#elif defined(CAMDEBUG) || defined(DIAGNOSTIC)
int isp_debug = 1;
#else
int isp_debug = 0;
@ -103,7 +105,7 @@ isp_attach(struct ispsoftc *isp)
/*
* If we have a second channel, construct SIM entry for that.
*/
if (IS_12X0(isp)) {
if (IS_DUALBUS(isp)) {
sim = cam_sim_alloc(isp_action, isp_poll, "isp", isp,
isp->isp_unit, 1, isp->isp_maxcmds, devq);
if (sim == NULL) {

2
sys/dev/isp/isp_freebsd.h
View File

@ -212,7 +212,7 @@ extern void isp_uninit(struct ispsoftc *);
#define IDPRINTF(lev, x) if (isp->isp_dblev >= (u_int8_t) lev) printf x
#define PRINTF printf
#define CFGPRINTF if (bootverbose || DFLT_DBLEVEL > 0) printf
#define CFGPRINTF if (bootverbose || DFLT_DBLEVEL > 1) printf
#define SYS_DELAY(x) DELAY(x)

53
sys/dev/isp/isp_pci.c
View File

@ -204,6 +204,10 @@ static struct ispmdvec mdvec_2200 = {
#define PCI_PRODUCT_QLOGIC_ISP1240 0x1240
#endif
#ifndef PCI_PRODUCT_QLOGIC_ISP1280
#define PCI_PRODUCT_QLOGIC_ISP1280 0x1280
#endif
#ifndef PCI_PRODUCT_QLOGIC_ISP2100
#define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
#endif
@ -220,6 +224,9 @@ static struct ispmdvec mdvec_2200 = {
#define PCI_QLOGIC_ISP1240 \
((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
#define PCI_QLOGIC_ISP1280 \
((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
#define PCI_QLOGIC_ISP2100 \
((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
@ -287,6 +294,9 @@ isp_pci_probe(pcici_t tag, pcidi_t type)
case PCI_QLOGIC_ISP1240:
x = "Qlogic ISP 1240 PCI SCSI Adapter";
break;
case PCI_QLOGIC_ISP1280:
x = "Qlogic ISP 1280 PCI SCSI Adapter";
break;
#endif
#ifndef ISP_DISABLE_2100_SUPPORT
case PCI_QLOGIC_ISP2100:
@ -443,7 +453,14 @@ isp_pci_attach(pcici_t cfid, int unit)
}
if (data == PCI_QLOGIC_ISP1240) {
mdvp = &mdvec_1080;
basetype = ISP_HA_SCSI_12X0;
basetype = ISP_HA_SCSI_1240;
psize = 2 * sizeof (sdparam);
pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
ISP1080_DMA_REGS_OFF;
}
if (data == PCI_QLOGIC_ISP1280) {
mdvp = &mdvec_1080;
basetype = ISP_HA_SCSI_1280;
psize = 2 * sizeof (sdparam);
pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
ISP1080_DMA_REGS_OFF;
@ -709,16 +726,23 @@ isp_pci_rd_reg_1080(isp, regoff)
struct ispsoftc *isp;
int regoff;
{
u_int16_t rv;
u_int16_t rv, oc = 0;
struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
int offset, oc = 0;
int offset;
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
(regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
u_int16_t tc;
/*
* We will assume that someone has paused the RISC processor.
*/
oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_SXP);
tc = oc & ~BIU_PCI1080_CONF1_DMA;
if (regoff & SXP_BANK1_SELECT)
tc |= BIU_PCI1080_CONF1_SXP1;
else
tc |= BIU_PCI1080_CONF1_SXP0;
isp_pci_wr_reg(isp, BIU_CONF1, tc);
} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA);
@ -726,8 +750,7 @@ isp_pci_rd_reg_1080(isp, regoff)
offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
offset += (regoff & 0xff);
rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset);
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
((regoff & _BLK_REG_MASK) == DMA_BLOCK)) {
if (oc) {
isp_pci_wr_reg(isp, BIU_CONF1, oc);
}
return (rv);
@ -742,12 +765,19 @@ isp_pci_wr_reg_1080(isp, regoff, val)
struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
int offset, oc = 0;
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
(regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
u_int16_t tc;
/*
* We will assume that someone has paused the RISC processor.
*/
oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_SXP);
tc = oc & ~BIU_PCI1080_CONF1_DMA;
if (regoff & SXP_BANK1_SELECT)
tc |= BIU_PCI1080_CONF1_SXP1;
else
tc |= BIU_PCI1080_CONF1_SXP0;
isp_pci_wr_reg(isp, BIU_CONF1, tc);
} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA);
@ -755,8 +785,7 @@ isp_pci_wr_reg_1080(isp, regoff, val)
offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
offset += (regoff & 0xff);
bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val);
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
((regoff & _BLK_REG_MASK) == DMA_BLOCK)) {
if (oc) {
isp_pci_wr_reg(isp, BIU_CONF1, oc);
}
}
@ -839,7 +868,7 @@ isp_pci_mbxdma(struct ispsoftc *isp)
return (1);
}
if (IS_FC(isp) || IS_1080(isp) || IS_12X0(isp))
if (IS_FC(isp) || IS_ULTRA2(isp))
lim = BUS_SPACE_MAXADDR + 1;
else
lim = BUS_SPACE_MAXADDR_24BIT + 1;

182
sys/dev/isp/ispreg.h
View File

@ -97,47 +97,47 @@
* Bus Interface Block Register Offsets
*/
#define BIU_ID_LO BIU_BLOCK+0x0 /* R : Bus ID, Low */
#define BIU2100_FLASH_ADDR BIU_BLOCK+0x0
#define BIU_ID_HI BIU_BLOCK+0x2 /* R : Bus ID, High */
#define BIU2100_FLASH_DATA BIU_BLOCK+0x2
#define BIU_CONF0 BIU_BLOCK+0x4 /* R : Bus Configuration #0 */
#define BIU_CONF1 BIU_BLOCK+0x6 /* R : Bus Configuration #1 */
#define BIU2100_CSR BIU_BLOCK+0x6
#define BIU_ICR BIU_BLOCK+0x8 /* RW : Bus Interface Ctrl */
#define BIU_ISR BIU_BLOCK+0xA /* R : Bus Interface Status */
#define BIU_SEMA BIU_BLOCK+0xC /* RW : Bus Semaphore */
#define BIU_NVRAM BIU_BLOCK+0xE /* RW : Bus NVRAM */
#define DFIFO_COMMAND BIU_BLOCK+0x60 /* RW : Command FIFO Port */
#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */
#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0)
#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */
#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2)
#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */
#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */
#define BIU2100_CSR (BIU_BLOCK+0x6)
#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */
#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */
#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */
#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */
#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */
#define RDMA2100_CONTROL DFIFO_COMMAND
#define DFIFO_DATA BIU_BLOCK+0x62 /* RW : Data FIFO Port */
#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */
/*
* Putzed DMA register layouts.
*/
#define CDMA_CONF DMA_BLOCK+0x20 /* RW*: DMA Configuration */
#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */
#define CDMA2100_CONTROL CDMA_CONF
#define CDMA_CONTROL DMA_BLOCK+0x22 /* RW*: DMA Control */
#define CDMA_STATUS DMA_BLOCK+0x24 /* R : DMA Status */
#define CDMA_FIFO_STS DMA_BLOCK+0x26 /* R : DMA FIFO Status */
#define CDMA_COUNT DMA_BLOCK+0x28 /* RW*: DMA Transfer Count */
#define CDMA_ADDR0 DMA_BLOCK+0x2C /* RW*: DMA Address, Word 0 */
#define CDMA_ADDR1 DMA_BLOCK+0x2E /* RW*: DMA Address, Word 1 */
#define CDMA_ADDR2 DMA_BLOCK+0x30 /* RW*: DMA Address, Word 2 */
#define CDMA_ADDR3 DMA_BLOCK+0x32 /* RW*: DMA Address, Word 3 */
#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */
#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */
#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */
#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */
#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */
#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */
#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */
#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */
#define DDMA_CONF DMA_BLOCK+0x40 /* RW*: DMA Configuration */
#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */
#define TDMA2100_CONTROL DDMA_CONF
#define DDMA_CONTROL DMA_BLOCK+0x42 /* RW*: DMA Control */
#define DDMA_STATUS DMA_BLOCK+0x44 /* R : DMA Status */
#define DDMA_FIFO_STS DMA_BLOCK+0x46 /* R : DMA FIFO Status */
#define DDMA_COUNT_LO DMA_BLOCK+0x48 /* RW*: DMA Xfer Count, Low */
#define DDMA_COUNT_HI DMA_BLOCK+0x4A /* RW*: DMA Xfer Count, High */
#define DDMA_ADDR0 DMA_BLOCK+0x4C /* RW*: DMA Address, Word 0 */
#define DDMA_ADDR1 DMA_BLOCK+0x4E /* RW*: DMA Address, Word 1 */
#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */
#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */
#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */
#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */
#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */
#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */
#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */
/* these are for the 1040A cards */
#define DDMA_ADDR2 DMA_BLOCK+0x50 /* RW*: DMA Address, Word 2 */
#define DDMA_ADDR3 DMA_BLOCK+0x52 /* RW*: DMA Address, Word 3 */
#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */
#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */
/*
@ -162,7 +162,8 @@
#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */
#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */
#define BIU_PCI1080_CONF1_SXP 0x0100 /* SXP bank select */
#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */
#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */
#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */
/* ISP2100 Bus Control/Status Register */
@ -318,23 +319,23 @@
* Mailbox Block Register Offsets
*/
#define INMAILBOX0 MBOX_BLOCK+0x0
#define INMAILBOX1 MBOX_BLOCK+0x2
#define INMAILBOX2 MBOX_BLOCK+0x4
#define INMAILBOX3 MBOX_BLOCK+0x6
#define INMAILBOX4 MBOX_BLOCK+0x8
#define INMAILBOX5 MBOX_BLOCK+0xA
#define INMAILBOX6 MBOX_BLOCK+0xC
#define INMAILBOX7 MBOX_BLOCK+0xE
#define INMAILBOX0 (MBOX_BLOCK+0x0)
#define INMAILBOX1 (MBOX_BLOCK+0x2)
#define INMAILBOX2 (MBOX_BLOCK+0x4)
#define INMAILBOX3 (MBOX_BLOCK+0x6)
#define INMAILBOX4 (MBOX_BLOCK+0x8)
#define INMAILBOX5 (MBOX_BLOCK+0xA)
#define INMAILBOX6 (MBOX_BLOCK+0xC)
#define INMAILBOX7 (MBOX_BLOCK+0xE)
#define OUTMAILBOX0 MBOX_BLOCK+0x0
#define OUTMAILBOX1 MBOX_BLOCK+0x2
#define OUTMAILBOX2 MBOX_BLOCK+0x4
#define OUTMAILBOX3 MBOX_BLOCK+0x6
#define OUTMAILBOX4 MBOX_BLOCK+0x8
#define OUTMAILBOX5 MBOX_BLOCK+0xA
#define OUTMAILBOX6 MBOX_BLOCK+0xC
#define OUTMAILBOX7 MBOX_BLOCK+0xE
#define OUTMAILBOX0 (MBOX_BLOCK+0x0)
#define OUTMAILBOX1 (MBOX_BLOCK+0x2)
#define OUTMAILBOX2 (MBOX_BLOCK+0x4)
#define OUTMAILBOX3 (MBOX_BLOCK+0x6)
#define OUTMAILBOX4 (MBOX_BLOCK+0x8)
#define OUTMAILBOX5 (MBOX_BLOCK+0xA)
#define OUTMAILBOX6 (MBOX_BLOCK+0xC)
#define OUTMAILBOX7 (MBOX_BLOCK+0xE)
#define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2))
#define NMBOX(isp) \
@ -344,45 +345,48 @@
/*
* SXP Block Register Offsets
*/
#define SXP_PART_ID SXP_BLOCK+0x0 /* R : Part ID Code */
#define SXP_CONFIG1 SXP_BLOCK+0x2 /* RW*: Configuration Reg #1 */
#define SXP_CONFIG2 SXP_BLOCK+0x4 /* RW*: Configuration Reg #2 */
#define SXP_CONFIG3 SXP_BLOCK+0x6 /* RW*: Configuration Reg #2 */
#define SXP_INSTRUCTION SXP_BLOCK+0xC /* RW*: Instruction Pointer */
#define SXP_RETURN_ADDR SXP_BLOCK+0x10 /* RW*: Return Address */
#define SXP_COMMAND SXP_BLOCK+0x14 /* RW*: Command */
#define SXP_INTERRUPT SXP_BLOCK+0x18 /* R : Interrupt */
#define SXP_SEQUENCE SXP_BLOCK+0x1C /* RW*: Sequence */
#define SXP_GROSS_ERR SXP_BLOCK+0x1E /* R : Gross Error */
#define SXP_EXCEPTION SXP_BLOCK+0x20 /* RW*: Exception Enable */
#define SXP_OVERRIDE SXP_BLOCK+0x24 /* RW*: Override */
#define SXP_LITERAL_BASE SXP_BLOCK+0x28 /* RW*: Literal Base */
#define SXP_USER_FLAGS SXP_BLOCK+0x2C /* RW*: User Flags */
#define SXP_USER_EXCEPT SXP_BLOCK+0x30 /* RW*: User Exception */
#define SXP_BREAKPOINT SXP_BLOCK+0x34 /* RW*: Breakpoint */
#define SXP_SCSI_ID SXP_BLOCK+0x40 /* RW*: SCSI ID */
#define SXP_DEV_CONFIG1 SXP_BLOCK+0x42 /* RW*: Device Config Reg #1 */
#define SXP_DEV_CONFIG2 SXP_BLOCK+0x44 /* RW*: Device Config Reg #2 */
#define SXP_PHASE_POINTER SXP_BLOCK+0x48 /* RW*: SCSI Phase Pointer */
#define SXP_BUF_POINTER SXP_BLOCK+0x4C /* RW*: SCSI Buffer Pointer */
#define SXP_BUF_COUNTER SXP_BLOCK+0x50 /* RW*: SCSI Buffer Counter */
#define SXP_BUFFER SXP_BLOCK+0x52 /* RW*: SCSI Buffer */
#define SXP_BUF_BYTE SXP_BLOCK+0x54 /* RW*: SCSI Buffer Byte */
#define SXP_BUF_WORD SXP_BLOCK+0x56 /* RW*: SCSI Buffer Word */
#define SXP_BUF_WORD_TRAN SXP_BLOCK+0x58 /* RW*: SCSI Buffer Wd xlate */
#define SXP_FIFO SXP_BLOCK+0x5A /* RW*: SCSI FIFO */
#define SXP_FIFO_STATUS SXP_BLOCK+0x5C /* RW*: SCSI FIFO Status */
#define SXP_FIFO_TOP SXP_BLOCK+0x5E /* RW*: SCSI FIFO Top Resid */
#define SXP_FIFO_BOTTOM SXP_BLOCK+0x60 /* RW*: SCSI FIFO Bot Resid */
#define SXP_TRAN_REG SXP_BLOCK+0x64 /* RW*: SCSI Transferr Reg */
#define SXP_TRAN_COUNT_LO SXP_BLOCK+0x68 /* RW*: SCSI Trans Count */
#define SXP_TRAN_COUNT_HI SXP_BLOCK+0x6A /* RW*: SCSI Trans Count */
#define SXP_TRAN_COUNTER_LO SXP_BLOCK+0x6C /* RW*: SCSI Trans Counter */
#define SXP_TRAN_COUNTER_HI SXP_BLOCK+0x6E /* RW*: SCSI Trans Counter */
#define SXP_ARB_DATA SXP_BLOCK+0x70 /* R : SCSI Arb Data */
#define SXP_PINS_CONTROL SXP_BLOCK+0x72 /* RW*: SCSI Control Pins */
#define SXP_PINS_DATA SXP_BLOCK+0x74 /* RW*: SCSI Data Pins */
#define SXP_PINS_DIFF SXP_BLOCK+0x76 /* RW*: SCSI Diff Pins */
#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */
#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */
#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */
#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */
#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */
#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */
#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */
#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */
#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */
#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */
#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */
#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */
#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */
#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */
#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */
#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */
#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */
#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */
#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */
#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */
#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */
#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */
#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */
#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */
#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */
#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */
#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */
#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */
#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */
#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */
#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */
#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */
#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */
#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */
#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */
#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */
#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */
#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */
#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */
/* for 1080/1280/1240 only */
#define SXP_BANK1_SELECT 0x100
/* SXP CONF1 REGISTER */
@ -511,7 +515,7 @@
#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */
#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */
/* 1080 only */
/* Ultra2 only */
#define SXP_PINS_LVD_MODE 0x1000
#define SXP_PINS_HVD_MODE 0x0800
#define SXP_PINS_SE_MODE 0x0400

13
sys/dev/isp/ispvar.h
View File

@ -390,15 +390,22 @@ struct ispsoftc {
#define ISP_HA_SCSI_1040A 0x5
#define ISP_HA_SCSI_1040B 0x6
#define ISP_HA_SCSI_1040C 0x7
#define ISP_HA_SCSI_1080 0xd
#define ISP_HA_SCSI_12X0 0xe
#define ISP_HA_SCSI_1240 0x8
#define ISP_HA_SCSI_1080 0x9
#define ISP_HA_SCSI_1280 0xa
#define ISP_HA_FC 0xf0
#define ISP_HA_FC_2100 0x10
#define ISP_HA_FC_2200 0x20
#define IS_SCSI(isp) (isp->isp_type & ISP_HA_SCSI)
#define IS_1240(isp) (isp->isp_type == ISP_HA_SCSI_1240)
#define IS_1080(isp) (isp->isp_type == ISP_HA_SCSI_1080)
#define IS_12X0(isp) (isp->isp_type == ISP_HA_SCSI_12X0)
#define IS_1280(isp) (isp->isp_type == ISP_HA_SCSI_1280)
#define IS_12X0(isp) \
(isp->isp_type == ISP_HA_SCSI_1240 || isp->isp_type == ISP_HA_SCSI_1280)
#define IS_DUALBUS(isp) IS_12X0(isp)
#define IS_ULTRA2(isp) \
(isp->isp_type == ISP_HA_SCSI_1080 || isp->isp_type == ISP_HA_SCSI_1280)
#define IS_FC(isp) (isp->isp_type & ISP_HA_FC)
/*

53
sys/pci/isp_pci.c
View File

@ -204,6 +204,10 @@ static struct ispmdvec mdvec_2200 = {
#define PCI_PRODUCT_QLOGIC_ISP1240 0x1240
#endif
#ifndef PCI_PRODUCT_QLOGIC_ISP1280
#define PCI_PRODUCT_QLOGIC_ISP1280 0x1280
#endif
#ifndef PCI_PRODUCT_QLOGIC_ISP2100
#define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
#endif
@ -220,6 +224,9 @@ static struct ispmdvec mdvec_2200 = {
#define PCI_QLOGIC_ISP1240 \
((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
#define PCI_QLOGIC_ISP1280 \
((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
#define PCI_QLOGIC_ISP2100 \
((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
@ -287,6 +294,9 @@ isp_pci_probe(pcici_t tag, pcidi_t type)
case PCI_QLOGIC_ISP1240:
x = "Qlogic ISP 1240 PCI SCSI Adapter";
break;
case PCI_QLOGIC_ISP1280:
x = "Qlogic ISP 1280 PCI SCSI Adapter";
break;
#endif
#ifndef ISP_DISABLE_2100_SUPPORT
case PCI_QLOGIC_ISP2100:
@ -443,7 +453,14 @@ isp_pci_attach(pcici_t cfid, int unit)
}
if (data == PCI_QLOGIC_ISP1240) {
mdvp = &mdvec_1080;
basetype = ISP_HA_SCSI_12X0;
basetype = ISP_HA_SCSI_1240;
psize = 2 * sizeof (sdparam);
pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
ISP1080_DMA_REGS_OFF;
}
if (data == PCI_QLOGIC_ISP1280) {
mdvp = &mdvec_1080;
basetype = ISP_HA_SCSI_1280;
psize = 2 * sizeof (sdparam);
pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
ISP1080_DMA_REGS_OFF;
@ -709,16 +726,23 @@ isp_pci_rd_reg_1080(isp, regoff)
struct ispsoftc *isp;
int regoff;
{
u_int16_t rv;
u_int16_t rv, oc = 0;
struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
int offset, oc = 0;
int offset;
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
(regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
u_int16_t tc;
/*
* We will assume that someone has paused the RISC processor.
*/
oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_SXP);
tc = oc & ~BIU_PCI1080_CONF1_DMA;
if (regoff & SXP_BANK1_SELECT)
tc |= BIU_PCI1080_CONF1_SXP1;
else
tc |= BIU_PCI1080_CONF1_SXP0;
isp_pci_wr_reg(isp, BIU_CONF1, tc);
} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA);
@ -726,8 +750,7 @@ isp_pci_rd_reg_1080(isp, regoff)
offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
offset += (regoff & 0xff);
rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset);
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
((regoff & _BLK_REG_MASK) == DMA_BLOCK)) {
if (oc) {
isp_pci_wr_reg(isp, BIU_CONF1, oc);
}
return (rv);
@ -742,12 +765,19 @@ isp_pci_wr_reg_1080(isp, regoff, val)
struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
int offset, oc = 0;
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
(regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
u_int16_t tc;
/*
* We will assume that someone has paused the RISC processor.
*/
oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_SXP);
tc = oc & ~BIU_PCI1080_CONF1_DMA;
if (regoff & SXP_BANK1_SELECT)
tc |= BIU_PCI1080_CONF1_SXP1;
else
tc |= BIU_PCI1080_CONF1_SXP0;
isp_pci_wr_reg(isp, BIU_CONF1, tc);
} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA);
@ -755,8 +785,7 @@ isp_pci_wr_reg_1080(isp, regoff, val)
offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
offset += (regoff & 0xff);
bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val);
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
((regoff & _BLK_REG_MASK) == DMA_BLOCK)) {
if (oc) {
isp_pci_wr_reg(isp, BIU_CONF1, oc);
}
}
@ -839,7 +868,7 @@ isp_pci_mbxdma(struct ispsoftc *isp)
return (1);
}
if (IS_FC(isp) || IS_1080(isp) || IS_12X0(isp))
if (IS_FC(isp) || IS_ULTRA2(isp))
lim = BUS_SPACE_MAXADDR + 1;
else
lim = BUS_SPACE_MAXADDR_24BIT + 1;