Consolitate all the AP core startup stuff under a single #ifdef SMP block.
Remove some other ifdefs that came in with a copy/paste that mean basically "if this processor supports multicore stuff", because if you're starting up an AP core... it does.
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@ -308,11 +308,6 @@ Lreal_start:
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Lend:
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.word _edata
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#ifdef SMP
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Lstartup_pagetable_secondary:
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.word temp_pagetable
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#endif
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.Lstart:
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.word _edata
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.word _ebss
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@ -320,10 +315,6 @@ Lstartup_pagetable_secondary:
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.Lvirt_done:
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.word virt_done
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#if defined(SMP)
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.Lmpvirt_done:
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.word mpvirt_done
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#endif
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.Lmainreturned:
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.asciz "main() returned"
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@ -350,6 +341,11 @@ pagetable:
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#if defined(SMP)
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.Lmpvirt_done:
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.word mpvirt_done
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Lstartup_pagetable_secondary:
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.word temp_pagetable
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ASENTRY_NP(mpentry)
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/* Make sure interrupts are disabled. */
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@ -379,26 +375,20 @@ Ltag:
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bic r0, r0, #0xf0000000
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orr r0, r0, #PHYSADDR
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ldr r0, [r0]
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#if defined(SMP)
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orr r0, r0, #2 /* Set TTB shared memory flag */
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#endif
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mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
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mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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mov r0, #0
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mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
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#endif
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/* Set the Domain Access register. Very important! */
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mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
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mcr p15, 0, r0, c3, c0, 0
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/* Enable MMU */
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mrc p15, 0, r0, c1, c0, 0
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
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orr r0, r0, #CPU_CONTROL_AF_ENABLE
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#endif
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orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
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mcr p15, 0, r0, c1, c0, 0
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nop
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@ -426,7 +416,7 @@ mpvirt_done:
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/* NOTREACHED */
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.Lmpreturned:
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.asciz "main() returned"
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.asciz "init_secondary() returned"
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.align 0
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END(mpentry)
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#endif
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