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Whitespace cleanup.

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This commit is contained in:
sos 2006-01-18 13:10:17 +00:00
parent aae482441a
commit 9fb5b6a7cc
8 changed files with 134 additions and 128 deletions
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6
sys/dev/ata/ata-all.c
View File

@ -219,11 +219,11 @@ ata_reinit(device_t dev)
if (ch->running && ch->running->dev == children[i]) {
callout_stop(&ch->running->callout);
request = ch->running;
ch->running = NULL;
ch->running = NULL;
}
else
request = NULL;
mtx_unlock(&ch->state_mtx);
mtx_unlock(&ch->state_mtx);
if (request) {
request->result = ENXIO;
@ -233,7 +233,7 @@ ata_reinit(device_t dev)
/* if not timeout finish request here */
if (!(request->flags & ATA_R_TIMEOUT))
ata_finish(request);
}
}
device_delete_child(dev, children[i]);
}
}

6
sys/dev/ata/ata-all.h
View File

@ -321,7 +321,7 @@ struct atapi_sense {
};
/* structure used for composite atomic operations */
#define MAX_COMPOSITES 32 /* u_int32_t bits */
#define MAX_COMPOSITES 32 /* u_int32_t bits */
struct ata_composite {
struct mtx lock; /* control lock */
u_int32_t rd_needed; /* needed read subdisks */
@ -330,7 +330,7 @@ struct ata_composite {
u_int32_t wr_depend; /* write depends on subdisks */
u_int32_t wr_done; /* done write subdisks */
struct ata_request *request[MAX_COMPOSITES];
u_int32_t residual; /* bytes still to transfer */
u_int32_t residual; /* bytes still to transfer */
caddr_t data_1;
caddr_t data_2;
};
@ -496,7 +496,7 @@ struct ata_channel {
#define ATA_USE_16BIT 0x02
#define ATA_ATAPI_DMA_RO 0x04
#define ATA_NO_48BIT_DMA 0x08
#define ATA_ALWAYS_DMASTAT 0x10
#define ATA_ALWAYS_DMASTAT 0x10
int devices; /* what is present */
#define ATA_ATA_MASTER 0x01

70
sys/dev/ata/ata-chipset.c
View File

@ -338,7 +338,7 @@ ata_sata_setmode(device_t dev, int mode)
*/
if (atadev->param.satacapabilities != 0x0000 &&
atadev->param.satacapabilities != 0xffff) {
struct ata_channel *ch = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(device_get_parent(dev));
int status;
/* on some drives we need to set the transfer mode */
@ -500,7 +500,7 @@ ata_ahci_status(device_t dev)
/* clear interrupt */
ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action);
/* do we have any device action ? */
/* do we have any device action ? */
if (!(issued & (1 << tag)))
return 1;
}
@ -1587,7 +1587,7 @@ ata_intel_ident(device_t dev)
{ ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
{ ATA_I82801GB_M, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
{ ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
{ ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
{ ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
{ 0, 0, 0, 0, 0, 0}};
char buffer[64];
@ -1621,9 +1621,9 @@ ata_intel_chipinit(device_t dev)
ctlr->r_type2 = SYS_RES_MEMORY;
ctlr->r_rid2 = PCIR_BAR(0);
if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
&ctlr->r_rid2,
&ctlr->r_rid2,
RF_ACTIVE)))
return ENXIO;
return ENXIO;
ctlr->channels = 4;
ctlr->allocate = ata_intel_31244_allocate;
ctlr->reset = ata_intel_31244_reset;
@ -2048,10 +2048,10 @@ ata_ite_setmode(device_t dev, int mode)
((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
struct ata_marvell_response {
u_int16_t tag;
u_int8_t edma_status;
u_int8_t dev_status;
u_int32_t timestamp;
u_int16_t tag;
u_int8_t edma_status;
u_int8_t dev_status;
u_int32_t timestamp;
};
struct ata_marvell_dma_prdentry {
@ -2290,8 +2290,8 @@ ata_marvell_begin_transaction(struct ata_request *request)
if (request->u.ata.command != ATA_READ_DMA &&
request->u.ata.command != ATA_WRITE_DMA) {
/* disable the EDMA machinery */
if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
/* disable the EDMA machinery */
if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
return ata_begin_transaction(request);
}
@ -2301,11 +2301,11 @@ ata_marvell_begin_transaction(struct ata_request *request)
/* check sanity, setup SG list and DMA engine */
if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
request->flags & ATA_R_READ, ch->dma->sg,
&dummy))) {
device_printf(request->dev, "setting up DMA failed\n");
request->result = error;
return ATA_OP_FINISHED;
request->flags & ATA_R_READ, ch->dma->sg,
&dummy))) {
device_printf(request->dev, "setting up DMA failed\n");
request->result = error;
return ATA_OP_FINISHED;
}
/* get next free request queue slot */
@ -2389,7 +2389,7 @@ ata_marvell_end_transaction(struct ata_request *request)
/* get response ptr's */
rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
rsp_out &= 0xffffff00;
rsp_out += (slot << 3);
@ -2401,7 +2401,7 @@ ata_marvell_end_transaction(struct ata_request *request)
request->error = 0;
/* ack response */
ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
/* update progress */
if (!(request->status & ATA_S_ERROR) &&
@ -2473,7 +2473,7 @@ ata_marvell_dmainit(device_t dev)
ata_dmainit(dev);
if (ch->dma) {
/* note start and stop are not used here */
ch->dma->setprd = ata_marvell_dmasetprd;
ch->dma->setprd = ata_marvell_dmasetprd;
}
}
@ -2781,7 +2781,8 @@ ata_promise_ident(device_t dev)
{ ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
{ ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
{ ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
{ ATA_PDC20580, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20580" },
{ ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
{ ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
{ ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
{ ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
{ ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
@ -2792,6 +2793,7 @@ ata_promise_ident(device_t dev)
{ ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
{ ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
{ ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
{ ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
{ 0, 0, 0, 0, 0, 0}};
char buffer[64];
uintptr_t devid = 0;
@ -2883,11 +2885,11 @@ ata_promise_chipinit(device_t dev)
u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
ata_promise_sx4_intr, ctlr, &ctlr->handle)) {
device_printf(dev, "unable to setup interrupt\n");
goto failnfree;
}
bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
ata_promise_sx4_intr, ctlr, &ctlr->handle)) {
device_printf(dev, "unable to setup interrupt\n");
goto failnfree;
}
/* print info about cache memory */
device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
@ -2923,11 +2925,11 @@ ata_promise_chipinit(device_t dev)
* status register they have.
*/
if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
ata_promise_mio_intr, ctlr, &ctlr->handle)) {
device_printf(dev, "unable to setup interrupt\n");
goto failnfree;
}
bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
ata_promise_mio_intr, ctlr, &ctlr->handle)) {
device_printf(dev, "unable to setup interrupt\n");
goto failnfree;
}
/* prime fake interrupt register */
ATA_OUTL(ctlr->r_res2, 0x060, 0xffffffff);
break;
@ -3224,8 +3226,8 @@ ata_promise_mio_intr(void *data)
ATA_OUTL(ctlr->r_res2, 0x060, ATA_INL(ctlr->r_res2, 0x040));
for (unit = 0; unit < ctlr->channels; unit++) {
if ((ch = ctlr->interrupt[unit].argument))
ctlr->interrupt[unit].function(ch);
if ((ch = ctlr->interrupt[unit].argument))
ctlr->interrupt[unit].function(ch);
}
ATA_OUTL(ctlr->r_res2, 0x060, 0xffffffff);
}
@ -4518,7 +4520,7 @@ ata_via_allocate(device_t dev)
rid = PCIR_BAR(ch->unit);
if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
SYS_RES_IOPORT,
SYS_RES_IOPORT,
&rid, RF_ACTIVE)))
return ENXIO;
@ -4538,7 +4540,7 @@ ata_via_allocate(device_t dev)
}
else {
/* setup the usual register normal pci style */
if (ata_pci_allocate(dev))
if (ata_pci_allocate(dev))
return ENXIO;
}

10
sys/dev/ata/ata-pci.c
View File

@ -56,7 +56,7 @@ static MALLOC_DEFINE(M_ATAPCI, "ata_pci", "ATA driver PCI");
/* misc defines */
#define IOMASK 0xfffffffc
#define ATA_PROBE_OK -10
#define ATA_PROBE_OK -10
/* prototypes */
static void ata_pci_dmainit(device_t);
@ -443,16 +443,16 @@ ata_pci_status(device_t dev)
(ch->dma->flags & ATA_DMA_ACTIVE))) {
int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
ATA_BMSTAT_INTERRUPT)
return 0;
ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
DELAY(1);
}
if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
DELAY(100);
if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
return 0;
DELAY(100);
if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
return 0;
}
return 1;
}

26
sys/dev/ata/ata-pci.h
View File

@ -88,20 +88,20 @@ struct ata_connect_task {
#define ATA_AMD8111 0x74691022
#define ATA_ACER_LABS_ID 0x10b9
#define ATA_ALI_1533 0x153310b9
#define ATA_ALI_1533 0x153310b9
#define ATA_ALI_5229 0x522910b9
#define ATA_ALI_5281 0x528110b9
#define ATA_ALI_5287 0x528710b9
#define ATA_ALI_5288 0x528810b9
#define ATA_ALI_5289 0x528910b9
#define ATA_ATI_ID 0x1002
#define ATA_ATI_IXP200 0x43491002
#define ATA_ATI_IXP300 0x43691002
#define ATA_ATI_IXP400 0x43761002
#define ATA_ATI_IXP300_S1 0x436e1002
#define ATA_ATI_IXP400_S1 0x43791002
#define ATA_ATI_IXP400_S2 0x437a1002
#define ATA_ATI_ID 0x1002
#define ATA_ATI_IXP200 0x43491002
#define ATA_ATI_IXP300 0x43691002
#define ATA_ATI_IXP400 0x43761002
#define ATA_ATI_IXP300_S1 0x436e1002
#define ATA_ATI_IXP400_S1 0x43791002
#define ATA_ATI_IXP400_S2 0x437a1002
#define ATA_CENATEK_ID 0x16ca
#define ATA_CENATEK_ROCKET 0x000116ca
@ -153,7 +153,7 @@ struct ata_connect_task {
#define ATA_I82801GB_R1 0x27c38086
#define ATA_I82801GB_AH 0x27c18086
#define ATA_I82801GB_M 0x27c58086
#define ATA_I31244 0x32008086
#define ATA_I31244 0x32008086
#define ATA_ITE_ID 0x1283
#define ATA_IT8211F 0x82111283
@ -220,17 +220,21 @@ struct ata_connect_task {
#define ATA_PDC20571 0x3571105a
#define ATA_PDC20575 0x3d75105a
#define ATA_PDC20579 0x3574105a
#define ATA_PDC20580 0x3570105a
#define ATA_PDC20771 0x3570105a
#define ATA_PDC40518 0x3d18105a
#define ATA_PDC40519 0x3519105a
#define ATA_PDC40718 0x3d17105a
#define ATA_PDC40719 0x3515105a
#define ATA_PDC40775 0x3d73105a
#define ATA_PDC40779 0x3577105a
#define ATA_PDC20617 0x6617105a
#define ATA_PDC20618 0x6626105a
#define ATA_PDC20619 0x6629105a
#define ATA_PDC20620 0x6620105a
#define ATA_PDC20621 0x6621105a
#define ATA_PDC20622 0x6622105a
#define ATA_PDC20624 0x6624105a
#define ATA_PDC81518 0x8002105a
#define ATA_SERVERWORKS_ID 0x1166
#define ATA_ROSB4_ISA 0x02001166
@ -319,7 +323,7 @@ struct ata_connect_task {
#define ATA_VIA6421 0x32491106
/* chipset setup related defines */
#define AHCI 1
#define AHCI 1
#define ATPOLD 1
#define ALIOLD 0x01

6
sys/dev/ata/ata-queue.c
View File

@ -205,9 +205,9 @@ ata_start(device_t dev)
mtx_unlock(&ch->state_mtx);
mtx_unlock(&ch->queue_mtx);
while (!ata_interrupt(ch))
DELAY(10);
DELAY(10);
return;
}
}
}
mtx_unlock(&ch->state_mtx);
}
@ -449,7 +449,7 @@ ata_completed(void *context, int dummy)
for (bit = 0; bit < MAX_COMPOSITES; bit++) {
if (index & (1 << bit))
ata_start(device_get_parent(composite->request[bit]->dev));
ata_start(device_get_parent(composite->request[bit]->dev));
}
}
}

20
sys/dev/ata/ata-raid.c
View File

@ -1394,7 +1394,7 @@ ata_raid_wipe_metadata(struct ar_softc *rdp)
lba = HPTV2_LBA(rdp->disks[disk].dev);
size = sizeof(struct hptv2_raid_conf);
break;
case AR_F_HPTV3_RAID:
lba = HPTV3_LBA(rdp->disks[disk].dev);
size = sizeof(struct hptv3_raid_conf);
@ -1402,7 +1402,7 @@ ata_raid_wipe_metadata(struct ar_softc *rdp)
case AR_F_INTEL_RAID:
lba = INTEL_LBA(rdp->disks[disk].dev);
size = 3 * 512; /* XXX SOS */
size = 3 * 512; /* XXX SOS */
break;
case AR_F_ITE_RAID:
@ -2180,12 +2180,12 @@ ata_raid_intel_write_meta(struct ar_softc *rdp)
meta->config_id = timestamp.tv_sec;
meta->generation = rdp->generation;
meta->total_disks = rdp->total_disks;
meta->total_volumes = 1; /* XXX SOS */
meta->total_volumes = 1; /* XXX SOS */
for (disk = 0; disk < rdp->total_disks; disk++) {
if (rdp->disks[disk].dev) {
struct ata_channel *ch =
struct ata_channel *ch =
device_get_softc(device_get_parent(rdp->disks[disk].dev));
struct ata_device *atadev =
struct ata_device *atadev =
device_get_softc(rdp->disks[disk].dev);
bcopy(atadev->param.serial, meta->disk[disk].serial,
@ -2211,12 +2211,12 @@ ata_raid_intel_write_meta(struct ar_softc *rdp)
bcopy(rdp->name, map->name, sizeof(rdp->name));
map->total_sectors = rdp->total_sectors;
map->state = 12; /* XXX SOS */
map->state = 12; /* XXX SOS */
map->offset = rdp->offset_sectors;
map->stripe_count = rdp->total_sectors / (rdp->interleave*rdp->total_disks);
map->stripe_sectors = rdp->interleave;
map->disk_sectors = rdp->total_sectors / rdp->width;
map->status = INTEL_S_READY; /* XXX SOS */
map->status = INTEL_S_READY; /* XXX SOS */
switch (rdp->type) {
case AR_T_RAID0:
map->type = INTEL_T_RAID0;
@ -3442,7 +3442,7 @@ ata_raid_sis_write_meta(struct ar_softc *rdp)
pci_get_device(GRANDPARENT(rdp->disks[disk].dev));
bcopy(atadev->param.model, meta->model, sizeof(meta->model));
/* XXX SOS if total_disks > 2 this may not float */
/* XXX SOS if total_disks > 2 this may not float */
meta->disk_number = 1 + ATA_DEV(atadev->unit) + (ch->unit << 1);
if (testing || bootverbose)
@ -3649,7 +3649,7 @@ ata_raid_via_write_meta(struct ar_softc *rdp)
free(meta, M_AR);
return ENODEV;
}
meta->type |= VIA_T_BOOTABLE; /* XXX SOS */
meta->type |= VIA_T_BOOTABLE; /* XXX SOS */
meta->disk_sectors =
rdp->total_sectors / (rdp->width - (rdp->type == AR_RAID5));
for (disk = 0; disk < rdp->total_disks; disk++)
@ -4256,7 +4256,7 @@ ata_raid_intel_print_meta(struct intel_raid_conf *meta)
for (i = 0; i < map->total_disks; i++ ) {
printf(" disk %d at disk_idx 0x%08x\n", i, map->disk_idx[i]);
}
map = (struct intel_raid_mapping *)&map->disk_idx[map->total_disks];
map = (struct intel_raid_mapping *)&map->disk_idx[map->total_disks];
}
printf("=================================================\n");
}

118
sys/dev/ata/ata-raid.h
View File

@ -43,7 +43,7 @@ struct ata_raid_subdisk {
struct ar_softc {
int lun;
u_int8_t name[32];
int volume;
int volume;
u_int64_t magic_0;
u_int64_t magic_1;
int type;
@ -662,41 +662,41 @@ struct promise_raid_conf {
( ((struct ad_softc *)device_get_ivars(dev))->total_secs - 1)
struct sii_raid_conf {
u_int16_t ata_params_00_53[54];
u_int64_t total_sectors;
u_int16_t ata_params_58_79[70];
u_int16_t dummy_0;
u_int16_t dummy_1;
u_int32_t controller_pci_id;
u_int16_t version_minor;
u_int16_t version_major;
u_int8_t timestamp[6];
u_int16_t stripe_sectors;
u_int16_t dummy_2;
u_int8_t disk_number;
u_int8_t type;
u_int16_t ata_params_00_53[54];
u_int64_t total_sectors;
u_int16_t ata_params_58_79[70];
u_int16_t dummy_0;
u_int16_t dummy_1;
u_int32_t controller_pci_id;
u_int16_t version_minor;
u_int16_t version_major;
u_int8_t timestamp[6];
u_int16_t stripe_sectors;
u_int16_t dummy_2;
u_int8_t disk_number;
u_int8_t type;
#define SII_T_RAID0 0x00
#define SII_T_RAID1 0x01
#define SII_T_RAID01 0x02
#define SII_T_SPARE 0x03
u_int8_t raid0_disks;
u_int8_t raid0_ident;
u_int8_t raid1_disks;
u_int8_t raid1_ident;
u_int64_t rebuild_lba;
u_int32_t generation;
u_int8_t status;
u_int8_t raid0_disks;
u_int8_t raid0_ident;
u_int8_t raid1_disks;
u_int8_t raid1_ident;
u_int64_t rebuild_lba;
u_int32_t generation;
u_int8_t status;
#define SII_S_READY 0x01
u_int8_t base_raid1_position;
u_int8_t base_raid0_position;
u_int8_t position;
u_int16_t dummy_3;
u_int8_t name[16];
u_int16_t checksum_0;
int8_t filler1[190];
u_int16_t checksum_1;
u_int8_t base_raid1_position;
u_int8_t base_raid0_position;
u_int8_t position;
u_int16_t dummy_3;
u_int8_t name[16];
u_int16_t checksum_0;
int8_t filler1[190];
u_int16_t checksum_1;
} __packed;
@ -705,29 +705,29 @@ struct sii_raid_conf {
( ((struct ad_softc *)device_get_ivars(dev))->total_secs - 16)
struct sis_raid_conf {
u_int16_t magic;
u_int16_t magic;
#define SIS_MAGIC 0x0010
u_int8_t disks;
#define SIS_D_MASTER 0xf0
#define SIS_D_MIRROR 0x0f
u_int8_t disks;
#define SIS_D_MASTER 0xf0
#define SIS_D_MIRROR 0x0f
u_int8_t type_total_disks;
#define SIS_D_MASK 0x0f
u_int8_t type_total_disks;
#define SIS_D_MASK 0x0f
#define SIS_T_MASK 0xf0
#define SIS_T_JBOD 0x10
#define SIS_T_RAID0 0x20
#define SIS_T_RAID0 0x20
#define SIS_T_RAID1 0x30
u_int32_t dummy_0;
u_int32_t controller_pci_id;
u_int16_t stripe_sectors;
u_int16_t dummy_1;
u_int32_t timestamp;
u_int8_t model[40];
u_int8_t disk_number;
u_int8_t dummy_2[3];
int8_t filler1[448];
u_int32_t dummy_0;
u_int32_t controller_pci_id;
u_int16_t stripe_sectors;
u_int16_t dummy_1;
u_int32_t timestamp;
u_int8_t model[40];
u_int8_t disk_number;
u_int8_t dummy_2[3];
int8_t filler1[448];
} __packed;
@ -736,11 +736,11 @@ struct sis_raid_conf {
( ((struct ad_softc *)device_get_ivars(dev))->total_secs - 1)
struct via_raid_conf {
u_int16_t magic;
u_int16_t magic;
#define VIA_MAGIC 0xaa55
u_int8_t dummy_0;
u_int8_t type;
u_int8_t dummy_0;
u_int8_t type;
#define VIA_T_MASK 0x7e
#define VIA_T_BOOTABLE 0x01
#define VIA_T_RAID0 0x04
@ -750,19 +750,19 @@ struct via_raid_conf {
#define VIA_T_SPAN 0x44
#define VIA_T_UNKNOWN 0x80
u_int8_t disk_index;
#define VIA_D_MASK 0x0f
#define VIA_D_DEGRADED 0x10
#define VIA_D_HIGH_IDX 0x20
u_int8_t disk_index;
#define VIA_D_MASK 0x0f
#define VIA_D_DEGRADED 0x10
#define VIA_D_HIGH_IDX 0x20
u_int8_t stripe_layout;
u_int8_t stripe_layout;
#define VIA_L_DISKS 0x07
#define VIA_L_MASK 0xf0
#define VIA_L_SHIFT 4
#define VIA_L_SHIFT 4
u_int64_t disk_sectors;
u_int32_t disk_id;
u_int32_t disks[8];
u_int8_t checksum;
u_int8_t filler_1[461];
u_int64_t disk_sectors;
u_int32_t disk_id;
u_int32_t disks[8];
u_int8_t checksum;
u_int8_t filler_1[461];
} __packed;