allwinner: mmc: Multiple improvement
- Add a per compatible configuration struct
- Not all SoC uses the same size for DMA transfert, add this into the
configuration data
- Use new timing mode for some SoC (A64 mmc)
- Auto calibrate clock for A64 mmc/emmc
- A64 mmc controller need masking of data0
- Add support for vmmc/vqmmc regulator
- Add more capabilities, r/w speed is better for eMMC
- MMC_CAP_SIGNALING_180 gives weird result so do not enable it for now.
- Add new register documented in H3/A64 user manual
Tested-On: Pine64-LTS (A64), eMMC still doesn't work
Tested-On: A64-Olinuxino (A64), sd and eMMC are working
Tested-On: NanoPi Neo Plus2 (H5), sd and eMMC are working
Tested-On: OrangePi PC2 (H5), sd only (no eMMC)
Tested-On: OrangePi One (H3), sd only (no eMMC)
Tested-On: BananaPi M2 (A31s), sd only (no eMMC)
This commit is contained in:
manu
parent
1c4853adf6
commit
a09fcfef11
@ -50,22 +50,50 @@ __FBSDID("$FreeBSD$");
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#include <arm/allwinner/aw_mmc.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/regulator/regulator.h>
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#define AW_MMC_MEMRES 0
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#define AW_MMC_IRQRES 1
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#define AW_MMC_RESSZ 2
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#define AW_MMC_DMA_SEGS ((MAXPHYS / PAGE_SIZE) + 1)
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#define AW_MMC_DMA_MAX_SIZE 0x2000
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#define AW_MMC_DMA_FTRGLEVEL 0x20070008
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#define AW_MMC_RESET_RETRY 1000
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#define CARD_ID_FREQUENCY 400000
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struct aw_mmc_conf {
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uint32_t dma_xferlen;
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bool mask_data0;
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bool can_calibrate;
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bool new_timing;
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};
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static const struct aw_mmc_conf a10_mmc_conf = {
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.dma_xferlen = 0x2000,
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};
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static const struct aw_mmc_conf a13_mmc_conf = {
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.dma_xferlen = 0x10000,
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};
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static const struct aw_mmc_conf a64_mmc_conf = {
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.dma_xferlen = 0x10000,
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.mask_data0 = true,
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.can_calibrate = true,
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.new_timing = true,
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};
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static const struct aw_mmc_conf a64_emmc_conf = {
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.dma_xferlen = 0x2000,
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.can_calibrate = true,
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};
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static struct ofw_compat_data compat_data[] = {
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{"allwinner,sun4i-a10-mmc", 1},
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{"allwinner,sun5i-a13-mmc", 1},
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{"allwinner,sun7i-a20-mmc", 1},
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{"allwinner,sun50i-a64-mmc", 1},
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{"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf},
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{"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf},
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{"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf},
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{"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf},
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{"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf},
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{NULL, 0}
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};
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@ -82,9 +110,13 @@ struct aw_mmc_softc {
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struct mmc_request * aw_req;
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struct mtx aw_mtx;
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struct resource * aw_res[AW_MMC_RESSZ];
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struct aw_mmc_conf * aw_mmc_conf;
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uint32_t aw_intr;
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uint32_t aw_intr_wait;
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void * aw_intrhand;
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int32_t aw_vdd;
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regulator_t aw_reg_vmmc;
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regulator_t aw_reg_vqmmc;
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/* Fields required for DMA access. */
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bus_addr_t aw_dma_desc_phys;
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@ -151,6 +183,9 @@ aw_mmc_attach(device_t dev)
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node = ofw_bus_get_node(dev);
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sc = device_get_softc(dev);
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sc->aw_dev = dev;
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sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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sc->aw_req = NULL;
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if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) {
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device_printf(dev, "cannot allocate device resources\n");
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@ -230,11 +265,22 @@ aw_mmc_attach(device_t dev)
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if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0)
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bus_width = 4;
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if (regulator_get_by_ofw_property(dev, 0, "vmmc-supply",
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&sc->aw_reg_vmmc) == 0 && bootverbose)
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device_printf(dev, "vmmc-supply regulator found\n");
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if (regulator_get_by_ofw_property(dev, 0, "vqmmc-supply",
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&sc->aw_reg_vqmmc) == 0 && bootverbose)
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device_printf(dev, "vqmmc-supply regulator found\n");
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sc->aw_host.f_min = 400000;
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sc->aw_host.f_max = 52000000;
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sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
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sc->aw_host.mode = mode_sd;
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sc->aw_host.caps = MMC_CAP_HSPEED;
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sc->aw_host.caps = MMC_CAP_HSPEED | MMC_CAP_UHS_SDR12 |
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MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
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MMC_CAP_UHS_DDR50 | MMC_CAP_MMC_DDR52;
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sc->aw_host.caps |= MMC_CAP_SIGNALING_330 /* | MMC_CAP_SIGNALING_180 */;
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if (bus_width >= 4)
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sc->aw_host.caps |= MMC_CAP_4_BIT_DATA;
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if (bus_width >= 8)
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@ -311,8 +357,8 @@ aw_mmc_setup_dma(struct aw_mmc_softc *sc)
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error = bus_dma_tag_create(bus_get_dma_tag(sc->aw_dev),
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AW_MMC_DMA_ALIGN, 0,
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BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
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AW_MMC_DMA_MAX_SIZE * AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS,
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AW_MMC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL,
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sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS,
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sc->aw_mmc_conf->dma_xferlen, BUS_DMA_ALLOCNOW, NULL, NULL,
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&sc->aw_dma_buf_tag);
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if (error)
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return (error);
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@ -366,7 +412,7 @@ aw_mmc_prepare_dma(struct aw_mmc_softc *sc)
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uint32_t val;
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cmd = sc->aw_req->cmd;
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if (cmd->data->len > AW_MMC_DMA_MAX_SIZE * AW_MMC_DMA_SEGS)
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if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS))
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return (EFBIG);
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error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
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cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0);
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@ -562,7 +608,8 @@ aw_mmc_intr(void *arg)
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goto end;
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}
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if (rint & AW_MMC_INT_ERR_BIT) {
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device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint);
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if (bootverbose)
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device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint);
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if (rint & AW_MMC_INT_RESP_TIMEOUT)
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sc->aw_req->cmd->error = MMC_ERR_TIMEOUT;
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else
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@ -704,6 +751,9 @@ aw_mmc_read_ivar(device_t bus, device_t child, int which,
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case MMCBR_IVAR_CAPS:
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*(int *)result = sc->aw_host.caps;
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break;
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case MMCBR_IVAR_TIMING:
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*(int *)result = sc->aw_host.ios.timing;
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break;
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case MMCBR_IVAR_MAX_DATA:
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*(int *)result = 65535;
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break;
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@ -746,6 +796,9 @@ aw_mmc_write_ivar(device_t bus, device_t child, int which,
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case MMCBR_IVAR_VDD:
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sc->aw_host.ios.vdd = value;
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break;
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case MMCBR_IVAR_TIMING:
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sc->aw_host.ios.timing = value;
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break;
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/* These are read-only */
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case MMCBR_IVAR_CAPS:
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case MMCBR_IVAR_HOST_OCR:
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@ -761,33 +814,83 @@ aw_mmc_write_ivar(device_t bus, device_t child, int which,
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static int
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aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon)
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{
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uint32_t cmdreg;
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uint32_t reg;
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int retry;
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uint32_t ckcr;
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ckcr = AW_MMC_READ_4(sc, AW_MMC_CKCR);
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ckcr &= ~(AW_MMC_CKCR_CCLK_ENB | AW_MMC_CKCR_CCLK_CTRL);
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reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
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reg &= ~(AW_MMC_CKCR_CCLK_ENB | AW_MMC_CKCR_CCLK_CTRL |
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AW_MMC_CKCR_CCLK_MASK_DATA0);
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if (clkon)
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ckcr |= AW_MMC_CKCR_CCLK_ENB;
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reg |= AW_MMC_CKCR_CCLK_ENB;
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if (sc->aw_mmc_conf->mask_data0)
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reg |= AW_MMC_CKCR_CCLK_MASK_DATA0;
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AW_MMC_WRITE_4(sc, AW_MMC_CKCR, ckcr);
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AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
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cmdreg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK |
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reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK |
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AW_MMC_CMDR_WAIT_PRE_OVER;
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AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg);
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AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg);
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retry = 0xfffff;
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while (--retry > 0) {
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if ((AW_MMC_READ_4(sc, AW_MMC_CMDR) & AW_MMC_CMDR_LOAD) == 0) {
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AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
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return (0);
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}
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while (reg & AW_MMC_CMDR_LOAD && --retry > 0) {
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reg = AW_MMC_READ_4(sc, AW_MMC_CMDR);
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DELAY(10);
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}
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AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
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device_printf(sc->aw_dev, "timeout updating clock\n");
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return (ETIMEDOUT);
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if (reg & AW_MMC_CMDR_LOAD) {
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device_printf(sc->aw_dev, "timeout updating clock\n");
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return (ETIMEDOUT);
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}
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if (sc->aw_mmc_conf->mask_data0) {
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reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
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reg &= ~AW_MMC_CKCR_CCLK_MASK_DATA0;
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AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
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}
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return (0);
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}
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static void
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aw_mmc_set_power(struct aw_mmc_softc *sc, int32_t vdd)
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{
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int min_uvolt, max_uvolt;
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sc->aw_vdd = vdd;
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if (sc->aw_reg_vmmc == NULL && sc->aw_reg_vqmmc == NULL)
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return;
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switch (1 << vdd) {
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case MMC_OCR_LOW_VOLTAGE:
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min_uvolt = max_uvolt = 1800000;
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break;
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case MMC_OCR_320_330:
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min_uvolt = 3200000;
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max_uvolt = 3300000;
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break;
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case MMC_OCR_330_340:
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min_uvolt = 3300000;
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max_uvolt = 3400000;
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break;
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}
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if (sc->aw_reg_vmmc)
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if (regulator_set_voltage(sc->aw_reg_vmmc,
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min_uvolt, max_uvolt) != 0)
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device_printf(sc->aw_dev,
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"Cannot set vmmc to %d<->%d\n",
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min_uvolt,
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max_uvolt);
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if (sc->aw_reg_vqmmc)
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if (regulator_set_voltage(sc->aw_reg_vqmmc,
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min_uvolt, max_uvolt) != 0)
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device_printf(sc->aw_dev,
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"Cannot set vqmmc to %d<->%d\n",
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min_uvolt,
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max_uvolt);
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}
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static int
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@ -796,7 +899,8 @@ aw_mmc_update_ios(device_t bus, device_t child)
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int error;
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struct aw_mmc_softc *sc;
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struct mmc_ios *ios;
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uint32_t ckcr;
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unsigned int clock;
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uint32_t reg, div = 1;
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sc = device_get_softc(bus);
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@ -815,28 +919,67 @@ aw_mmc_update_ios(device_t bus, device_t child)
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break;
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}
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/* Set the voltage */
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if (ios->power_mode == power_off) {
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if (bootverbose)
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device_printf(sc->aw_dev, "Powering down sd/mmc\n");
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if (sc->aw_reg_vmmc)
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regulator_disable(sc->aw_reg_vmmc);
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if (sc->aw_reg_vqmmc)
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regulator_disable(sc->aw_reg_vqmmc);
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} else if (sc->aw_vdd != ios->vdd)
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aw_mmc_set_power(sc, ios->vdd);
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/* Enable ddr mode if needed */
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reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
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if (ios->timing == bus_timing_uhs_ddr50 ||
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ios->timing == bus_timing_mmc_ddr52)
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reg |= AW_MMC_CTRL_DDR_MOD_SEL;
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else
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reg &= ~AW_MMC_CTRL_DDR_MOD_SEL;
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AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
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if (ios->clock) {
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clock = ios->clock;
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/* Disable clock */
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error = aw_mmc_update_clock(sc, 0);
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if (error != 0)
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return (error);
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if (ios->timing == bus_timing_mmc_ddr52 &&
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(sc->aw_mmc_conf->new_timing ||
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ios->bus_width == bus_width_8)) {
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div = 2;
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clock <<= 1;
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}
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/* Reset the divider. */
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ckcr = AW_MMC_READ_4(sc, AW_MMC_CKCR);
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ckcr &= ~AW_MMC_CKCR_CCLK_DIV;
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AW_MMC_WRITE_4(sc, AW_MMC_CKCR, ckcr);
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reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
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reg &= ~AW_MMC_CKCR_CCLK_DIV;
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reg |= div - 1;
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AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
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/* New timing mode if needed */
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if (sc->aw_mmc_conf->new_timing) {
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reg = AW_MMC_READ_4(sc, AW_MMC_NTSR);
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reg |= AW_MMC_NTSR_MODE_SELECT;
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AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg);
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}
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/* Set the MMC clock. */
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error = clk_set_freq(sc->aw_clk_mmc, ios->clock,
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error = clk_set_freq(sc->aw_clk_mmc, clock,
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CLK_SET_ROUND_DOWN);
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if (error != 0) {
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device_printf(sc->aw_dev,
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"failed to set frequency to %u Hz: %d\n",
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ios->clock, error);
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clock, error);
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return (error);
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}
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if (sc->aw_mmc_conf->can_calibrate)
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AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN);
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/* Enable clock. */
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error = aw_mmc_update_clock(sc, 1);
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if (error != 0)
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@ -47,13 +47,22 @@
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#define AW_MMC_STAR 0x3C /* Status Register */
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#define AW_MMC_FWLR 0x40 /* FIFO Threshold Watermark Register */
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#define AW_MMC_FUNS 0x44 /* Function Select Register */
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#define AW_MMC_HWRST 0x78 /* Hardware reset (not documented) */
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#define AW_MMC_CSDC 0x54 /* CRC status detect controler register (A64 smhc2 only) */
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#define AW_MMC_A12A 0x58 /* Auto command 12 argument register */
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#define AW_MMC_NTSR 0x5C /* SD new timing register (H3, A64 smhc0/1 only) */
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#define AW_MMC_HWRST 0x78 /* Hardware reset */
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#define AW_MMC_DMAC 0x80 /* IDMAC Control Register */
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#define AW_MMC_DLBA 0x84 /* IDMAC Desc List Base Address Reg */
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#define AW_MMC_IDST 0x88 /* IDMAC Status Register */
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#define AW_MMC_IDIE 0x8C /* IDMAC Interrupt Enable Register */
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#define AW_MMC_FIFO 0x100 /* FIFO Access Address (A10/A20) */
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#define A31_MMC_FIFO 0x200 /* FIFO Access Address (A31) */
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#define AW_MMC_DDR_SBIT_DET 0x10C /* eMMC4.5 DDR Start Bit Detection control register */
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#define AW_MMC_DRV_DL 0x140 /* Drive Delay control register */
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#define AW_MMC_SAMP_DL 0x144 /* Sample Delay controle register */
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#define AW_MMC_DS_DL 0x148 /* Data strobe delay control register */
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#define AW_MMC_FIFO 0x100 /* FIFO Access Address (A10/A20) */
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#define A31_MMC_FIFO 0x200 /* FIFO Access Address (A31) */
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/* AW_MMC_GCTL */
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#define AW_MMC_CTRL_SOFT_RST (1U << 0)
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@ -70,6 +79,7 @@
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/* AW_MMC_CKCR */
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#define AW_MMC_CKCR_CCLK_ENB (1U << 16)
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#define AW_MMC_CKCR_CCLK_CTRL (1U << 17)
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#define AW_MMC_CKCR_CCLK_MASK_DATA0 (1U << 31)
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#define AW_MMC_CKCR_CCLK_DIV 0xff
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/* AW_MMC_TMOR */
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@ -153,6 +163,9 @@
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#define AW_MMC_SEND_AUTOSTOP_CC_SD (1U << 9)
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#define AW_MMC_CE_ATA_DEV_INT_ENB (1U << 10)
|
||||
|
||||
/* AW_MMC_NTSR */
|
||||
#define AW_MMC_NTSR_MODE_SELECT (1U << 31)
|
||||
|
||||
/* IDMA CONTROLLER BUS MOD BIT FIELD */
|
||||
#define AW_MMC_DMAC_IDMAC_SOFT_RST (1U << 0)
|
||||
#define AW_MMC_DMAC_IDMAC_FIX_BURST (1U << 1)
|
||||
@ -184,6 +197,12 @@
|
||||
#define AW_MMC_IDST_COMPLETE \
|
||||
(AW_MMC_IDST_TX_INT | AW_MMC_IDST_RX_INT)
|
||||
|
||||
/* AW_MMC_DDR_SBIT_DET */
|
||||
#define AW_MMC_DDR_SBIT_HS_MD_EN (1U << 31)
|
||||
|
||||
/* AW_MMC_SAMP */
|
||||
#define AW_MMC_SAMP_DL_SW_EN (1U << 7)
|
||||
|
||||
/* The DMA descriptor table. */
|
||||
struct aw_mmc_dma_desc {
|
||||
uint32_t config;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user