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Add SCTLR bits added in ARMv8.1 and ARMv8.2 and start to use them in the

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early boot code.

Sponsored by:	DARPA, AFRL
This commit is contained in:
andrew 2017-04-13 11:56:27 +00:00
parent 5df4d29ac9
commit a19f569aad
2 changed files with 10 additions and 5 deletions
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7
sys/arm64/arm64/locore.S
View File

@ -626,12 +626,13 @@ tcr:
TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
sctlr_set:
/* Bits to set */
.quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
.quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \
SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | SCTLR_M)
sctlr_clear:
/* Bits to clear */
.quad (SCTLR_EE | SCTLR_EOE | SCTLR_WXN | SCTLR_UMA | SCTLR_ITD | \
SCTLR_THEE | SCTLR_CP15BEN | SCTLR_A)
.quad (SCTLR_EE | SCTLR_EOE | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \
SCTLR_ITD | SCTLR_THEE | SCTLR_CP15BEN | SCTLR_A)
.globl abort
abort:

8
sys/arm64/include/armreg.h
View File

@ -384,8 +384,8 @@
#define PAR_S_MASK (0x1 << PAR_S_SHIFT)
/* SCTLR_EL1 - System Control Register */
#define SCTLR_RES0 0xc8222400 /* Reserved, write 0 */
#define SCTLR_RES1 0x30d00800 /* Reserved, write 1 */
#define SCTLR_RES0 0xc8222400 /* Reserved ARMv8.0, write 0 */
#define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */
#define SCTLR_M 0x00000001
#define SCTLR_A 0x00000002
@ -403,9 +403,13 @@
#define SCTLR_nTWI 0x00010000
#define SCTLR_nTWE 0x00040000
#define SCTLR_WXN 0x00080000
#define SCTLR_IESB 0x00200000
#define SCTLR_SPAN 0x00800000
#define SCTLR_EOE 0x01000000
#define SCTLR_EE 0x02000000
#define SCTLR_UCI 0x04000000
#define SCTLR_nTLSMD 0x10000000
#define SCTLR_LSMAOE 0x20000000
/* SPSR_EL1 */
/*