Add support for Enhanced Allocation in pciconf
* Modified pciconf to print EA capability structure * Added register description to pcireg.h Obtained from: Semihalf Sponsored by: Cavium Approved by: cognet (mentor) Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D5440
This commit is contained in:
Wojciech Macek
parent
de867427d8
commit
a2862b1169
@ -146,6 +146,7 @@
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#define PCIY_MSIX 0x11 /* MSI-X */
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#define PCIY_SATA 0x12 /* SATA */
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#define PCIY_PCIAF 0x13 /* PCI Advanced Features */
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#define PCIY_EA 0x14 /* PCI Extended Allocation */
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/* Extended Capability Register Fields */
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@ -586,6 +587,52 @@
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#define PCIR_MSI_MASK 0x10
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#define PCIR_MSI_PENDING 0x14
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/* PCI Enhanced Allocation registers */
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#define PCIR_EA_NUM_ENT 2 /* Number of Capability Entries */
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#define PCIM_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */
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#define PCIR_EA_FIRST_ENT 4 /* First EA Entry in List */
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#define PCIR_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */
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#define PCIM_EA_ES 0x00000007 /* Entry Size */
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#define PCIM_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
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#define PCIM_EA_BEI_OFFSET 4
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/* 0-5 map to BARs 0-5 respectively */
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#define PCIM_EA_BEI_BAR_0 0
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#define PCIM_EA_BEI_BAR_5 5
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#define PCIM_EA_BEI_BAR(x) (((x) >> PCIM_EA_BEI_OFFSET) & 0xf)
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#define PCIM_EA_BEI_BRIDGE 0x6 /* Resource behind bridge */
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#define PCIM_EA_BEI_ENI 0x7 /* Equivalent Not Indicated */
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#define PCIM_EA_BEI_ROM 0x8 /* Expansion ROM */
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/* 9-14 map to VF BARs 0-5 respectively */
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#define PCIM_EA_BEI_VF_BAR_0 9
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#define PCIM_EA_BEI_VF_BAR_5 14
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#define PCIM_EA_BEI_RESERVED 0xf /* Reserved - Treat like ENI */
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#define PCIM_EA_PP 0x0000ff00 /* Primary Properties */
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#define PCIM_EA_PP_OFFSET 8
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#define PCIM_EA_SP_OFFSET 16
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#define PCIM_EA_SP 0x00ff0000 /* Secondary Properties */
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#define PCIM_EA_P_MEM 0x00 /* Non-Prefetch Memory */
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#define PCIM_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */
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#define PCIM_EA_P_IO 0x02 /* I/O Space */
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#define PCIM_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */
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#define PCIM_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */
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#define PCIM_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */
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#define PCIM_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */
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#define PCIM_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */
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/* 0x08-0xfc reserved */
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#define PCIM_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */
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#define PCIM_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */
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#define PCIM_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */
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#define PCIM_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */
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#define PCIM_EA_ENABLE 0x80000000 /* Enable for this entry */
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#define PCIM_EA_BASE 4 /* Base Address Offset */
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#define PCIM_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */
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/* bit 0 is reserved */
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#define PCIM_EA_IS_64 0x00000002 /* 64-bit field flag */
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#define PCIM_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
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/* Bridge config register */
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#define PCIM_EA_SEC_NR(reg) ((reg) & 0xff)
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#define PCIM_EA_SUB_NR(reg) (((reg) >> 8) & 0xff)
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/* PCI-X definitions */
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/* For header type 0 devices */
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@ -534,6 +534,141 @@ cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr)
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cap & PCIM_PCIAFCAP_TP ? " TP" : "");
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}
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static const char *
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ea_bei_to_name(uint8_t bei)
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{
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static const char *barstr[] = {
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"BAR0", "BAR1", "BAR2", "BAR3", "BAR4", "BAR5"
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};
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static const char *vfbarstr[] = {
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"VFBAR0", "VFBAR1", "VFBAR2", "VFBAR3", "VFBAR4", "VFBAR5"
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};
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if ((bei >= PCIM_EA_BEI_BAR_0) && (bei <= PCIM_EA_BEI_BAR_5))
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return (barstr[bei - PCIM_EA_BEI_BAR_0]);
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if ((bei >= PCIM_EA_BEI_VF_BAR_0) && (bei <= PCIM_EA_BEI_VF_BAR_5))
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return (vfbarstr[bei - PCIM_EA_BEI_VF_BAR_0]);
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switch (bei) {
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case PCIM_EA_BEI_BRIDGE:
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return "BRIDGE";
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case PCIM_EA_BEI_ENI:
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return "ENI";
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case PCIM_EA_BEI_ROM:
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return "ROM";
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case PCIM_EA_BEI_RESERVED:
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default:
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return "RSVD";
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}
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}
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static const char *
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ea_prop_to_name(uint8_t prop)
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{
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switch (prop) {
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case PCIM_EA_P_MEM:
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return "Non-Prefetchable Memory";
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case PCIM_EA_P_MEM_PREFETCH:
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return "Prefetchable Memory";
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case PCIM_EA_P_IO:
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return "I/O Space";
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case PCIM_EA_P_VF_MEM_PREFETCH:
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return "VF Prefetchable Memory";
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case PCIM_EA_P_VF_MEM:
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return "VF Non-Prefetchable Memory";
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case PCIM_EA_P_BRIDGE_MEM:
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return "Bridge Non-Prefetchable Memory";
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case PCIM_EA_P_BRIDGE_MEM_PREFETCH:
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return "Bridge Prefetchable Memory";
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case PCIM_EA_P_BRIDGE_IO:
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return "Bridge I/O Space";
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case PCIM_EA_P_MEM_RESERVED:
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return "Reserved Memory";
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case PCIM_EA_P_IO_RESERVED:
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return "Reserved I/O Space";
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case PCIM_EA_P_UNAVAILABLE:
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return "Unavailable";
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default:
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return "Reserved";
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}
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}
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static void
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cap_ea(int fd, struct pci_conf *p, uint8_t ptr)
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{
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int num_ent;
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int a, b;
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uint32_t bei;
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uint32_t val;
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int ent_size;
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uint32_t dw[4];
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uint32_t flags, flags_pp, flags_sp;
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uint64_t base, max_offset;
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uint8_t fixed_sub_bus_nr, fixed_sec_bus_nr;
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/* Determine the number of entries */
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num_ent = read_config(fd, &p->pc_sel, ptr + PCIR_EA_NUM_ENT, 2);
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num_ent &= PCIM_EA_NUM_ENT_MASK;
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printf("PCI Enhanced Allocation (%d entries)", num_ent);
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/* Find the first entry to care of */
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ptr += PCIR_EA_FIRST_ENT;
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/* Print BUS numbers for bridges */
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if ((p->pc_hdr & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) {
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val = read_config(fd, &p->pc_sel, ptr, 4);
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fixed_sec_bus_nr = PCIM_EA_SEC_NR(val);
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fixed_sub_bus_nr = PCIM_EA_SUB_NR(val);
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printf("\n\t\t BRIDGE, sec bus [%d], sub bus [%d]",
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fixed_sec_bus_nr, fixed_sub_bus_nr);
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ptr += 4;
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}
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for (a = 0; a < num_ent; a++) {
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/* Read a number of dwords in the entry */
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val = read_config(fd, &p->pc_sel, ptr, 4);
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ptr += 4;
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ent_size = (val & PCIM_EA_ES);
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for (b = 0; b < ent_size; b++) {
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dw[b] = read_config(fd, &p->pc_sel, ptr, 4);
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ptr += 4;
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}
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flags = val;
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flags_pp = (flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET;
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flags_sp = (flags & PCIM_EA_SP) >> PCIM_EA_SP_OFFSET;
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bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET;
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base = dw[0] & PCIM_EA_FIELD_MASK;
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max_offset = dw[1] | ~PCIM_EA_FIELD_MASK;
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b = 2;
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if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) {
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base |= (uint64_t)dw[b] << 32UL;
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b++;
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}
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if (((dw[1] & PCIM_EA_IS_64) != 0)
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&& (b < ent_size)) {
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max_offset |= (uint64_t)dw[b] << 32UL;
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b++;
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}
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printf("\n\t\t [%d] %s, %s, %s, base [0x%lx], size [0x%lx]"
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"\n\t\t\tPrimary properties [0x%x] (%s)"
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"\n\t\t\tSecondary properties [0x%x] (%s)",
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bei, ea_bei_to_name(bei),
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(flags & PCIM_EA_ENABLE ? "Enabled" : "Disabled"),
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(flags & PCIM_EA_WRITABLE ? "Writable" : "Read-only"),
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base, max_offset + 1,
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flags_pp, ea_prop_to_name(flags_pp),
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flags_sp, ea_prop_to_name(flags_sp));
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}
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}
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void
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list_caps(int fd, struct pci_conf *p)
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{
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@ -605,6 +740,9 @@ list_caps(int fd, struct pci_conf *p)
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case PCIY_PCIAF:
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cap_pciaf(fd, p, ptr);
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break;
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case PCIY_EA:
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cap_ea(fd, p, ptr);
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break;
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default:
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printf("unknown");
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break;
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