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Fix for use of the XHCI driver on Cortex-A72 by adding a missing cache

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flush operation before writing to the XHCI_ERSTBA_LO/HI register(s).

PR:		237666
Discussed with:	Mark Millard <marklmi@yahoo.com>
MFC after:	1 week
Sponsored by:	Mellanox Technologies // Nvidia
This commit is contained in:
Hans Petter Selasky 2020-09-19 22:37:45 +00:00
parent 68d7185b64
commit a29c0348f0
1 changed files with 13 additions and 0 deletions
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13
sys/dev/usb/controller/xhci.c
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@ -432,6 +432,19 @@ xhci_start_controller(struct xhci_softc *sc)
phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
/*
* PR 237666:
*
* According to the XHCI specification, the XWRITE4's to
* XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the
* qwEvrsTablePtr and dwEvrsTableSize values above at that
* time, as the XHCI initializes its event ring support. This
* is before the event ring starts to pay attention to the
* RUN/STOP bit. Thus, make sure the values are observable to
* the XHCI before that point.
*/
usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);