Add device driver support for the VIA Networking Technologies
VT6122 gigabit ethernet chip and integrated 10/100/1000 copper PHY. The vge driver has been added to GENERIC for i386, pc98 and amd64, but not to sparc or ia64 since I don't have the ability to test it there. The vge(4) driver supports VLANs, checksum offload and jumbo frames. Also added the lge(4) and nge(4) drivers to GENERIC for i386 and pc98 since I was in the neighborhood. There's no reason to leave them out anymore.
This commit is contained in:
wpaul
parent
0dc3b359ff
commit
a2f7a53a34
@ -20,7 +20,8 @@ options {
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set ethernet-nic-regex
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"(an|ar|ath|aue|awi|axe|bfe|bge|cm|cnw|cs|cue|dc|de|ed|el|em|\
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ep|ex|fe|fxp|gem|gx|hme|ie|kue|lge|lnc|my|nge|pcn|ray|re|rl|\
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rue|sf|sis|sk|sn|snc|ste|ti|tl|tx|txp|vr|vx|wb|wi|xe|xl)[0-9]+";
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rue|sf|sis|sk|sn|snc|ste|ti|tl|tx|txp|vge|vr|vx|wb|wi|xe|\
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xl)[0-9]+";
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set scsi-controller-regex
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"(adv|advw|aic|aha|ahb|ahc|ahd|bt|ct|iir|isp|mly|mpt|ncv|nsp|\
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stg|sym|wds)[0-9]+";
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@ -184,6 +184,8 @@ device bfe # Broadcom BCM440x 10/100 Ethernet
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device bge # Broadcom BCM570xx Gigabit Ethernet
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device dc # DEC/Intel 21143 and various workalikes
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device fxp # Intel EtherExpress PRO/100B (82557, 82558)
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device lge # Level 1 LXT1001 gigabit ethernet
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device nge # NatSemi DP83820 gigabit ethernet
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device pcn # AMD Am79C97x PCI 10/100 (precedence over 'lnc')
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device re # RealTek 8139C+/8169/8169S/8110S
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device rl # RealTek 8129/8139
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@ -194,6 +196,7 @@ device ste # Sundance ST201 (D-Link DFE-550TX)
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device ti # Alteon Networks Tigon I/II gigabit Ethernet
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device tl # Texas Instruments ThunderLAN
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device tx # SMC EtherPower II (83c170 ``EPIC'')
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device vge # VIA VT612x gigabit ethernet
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device vr # VIA Rhine, Rhine II
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device wb # Winbond W89C840F
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device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
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@ -549,6 +549,7 @@ dev/mem/memdev.c optional mem
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dev/mii/amphy.c optional miibus
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dev/mii/bmtphy.c optional miibus
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dev/mii/brgphy.c optional miibus
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dev/mii/ciphy.c optional miibus
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dev/mii/dcphy.c optional miibus pci
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dev/mii/e1000phy.c optional miibus
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dev/mii/exphy.c optional miibus
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@ -842,6 +843,7 @@ dev/vinum/vinumrequest.c optional vinum
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dev/vinum/vinumrevive.c optional vinum
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dev/vinum/vinumstate.c optional vinum
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dev/vinum/vinumutil.c optional vinum
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dev/vge/if_vge.c optional vge
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dev/vx/if_vx.c optional vx
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dev/vx/if_vx_eisa.c optional vx eisa
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dev/vx/if_vx_pci.c optional vx pci
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433
sys/dev/mii/ciphy.c
Normal file
433
sys/dev/mii/ciphy.c
Normal file
@ -0,0 +1,433 @@
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/*
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* Copyright (c) 2004
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Driver for the Cicada CS8201 10/100/1000 copper PHY.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <machine/clock.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include <dev/mii/ciphyreg.h>
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#include "miibus_if.h"
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#include <machine/bus.h>
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/*
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#include <dev/vge/if_vgereg.h>
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*/
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static int ciphy_probe(device_t);
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static int ciphy_attach(device_t);
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static device_method_t ciphy_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, ciphy_probe),
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DEVMETHOD(device_attach, ciphy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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{ 0, 0 }
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};
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static devclass_t ciphy_devclass;
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static driver_t ciphy_driver = {
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"ciphy",
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ciphy_methods,
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sizeof(struct mii_softc)
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};
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DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
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static int ciphy_service(struct mii_softc *, struct mii_data *, int);
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static void ciphy_status(struct mii_softc *);
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static void ciphy_reset(struct mii_softc *);
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static void ciphy_fixup(struct mii_softc *);
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static int
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ciphy_probe(dev)
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device_t dev;
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{
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struct mii_attach_args *ma;
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ma = device_get_ivars(dev);
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if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
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MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201) {
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device_set_desc(dev, MII_STR_CICADA_CS8201);
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return(0);
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}
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if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
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MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201A) {
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device_set_desc(dev, MII_STR_CICADA_CS8201A);
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return(0);
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}
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if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
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MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201B) {
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device_set_desc(dev, MII_STR_CICADA_CS8201B);
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return(0);
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}
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return(ENXIO);
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}
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static int
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ciphy_attach(dev)
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device_t dev;
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{
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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struct mii_data *mii;
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sc = device_get_softc(dev);
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ma = device_get_ivars(dev);
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sc->mii_dev = device_get_parent(dev);
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mii = device_get_softc(sc->mii_dev);
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LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_service = ciphy_service;
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sc->mii_pdata = mii;
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sc->mii_flags |= MIIF_NOISOLATE;
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mii->mii_instance++;
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ciphy_reset(sc);
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sc->mii_capabilities =
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PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
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device_printf(dev, " ");
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mii_phy_add_media(sc);
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printf("\n");
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return(0);
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}
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static int
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ciphy_service(sc, mii, cmd)
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struct mii_softc *sc;
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struct mii_data *mii;
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int cmd;
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int reg, speed, gig;
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switch (cmd) {
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case MII_POLLSTAT:
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/*
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* If we're not polling our PHY instance, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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reg = PHY_READ(sc, MII_BMCR);
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PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
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return (0);
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}
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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ciphy_fixup(sc); /* XXX hardware bug work-around */
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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#ifdef foo
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/*
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* If we're already in auto mode, just return.
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*/
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if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
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return (0);
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#endif
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(void) mii_phy_auto(sc);
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break;
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case IFM_1000_T:
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speed = CIPHY_S1000;
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goto setit;
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case IFM_100_TX:
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speed = CIPHY_S100;
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goto setit;
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case IFM_10_T:
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speed = CIPHY_S10;
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setit:
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
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speed |= CIPHY_BMCR_FDX;
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gig = CIPHY_1000CTL_AFD;
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} else {
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gig = CIPHY_1000CTL_AHD;
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}
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PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
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PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
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PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
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break;
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PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
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PHY_WRITE(sc, CIPHY_MII_BMCR,
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speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
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/*
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* When setting the link manually, one side must
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* be the master and the other the slave. However
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* ifmedia doesn't give us a good way to specify
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* this, so we fake it by using one of the LINK
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* flags. If LINK0 is set, we program the PHY to
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* be a master, otherwise it's a slave.
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*/
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if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
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PHY_WRITE(sc, CIPHY_MII_1000CTL,
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gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
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} else {
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PHY_WRITE(sc, CIPHY_MII_1000CTL,
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gig|CIPHY_1000CTL_MSE);
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}
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break;
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case IFM_NONE:
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PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
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break;
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case IFM_100_T4:
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default:
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return (EINVAL);
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}
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break;
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case MII_TICK:
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/*
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* If we're not currently selected, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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/*
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* Is the interface even up?
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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/*
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* Only used for autonegotiation.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
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break;
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/*
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* Check to see if we have link. If we do, we don't
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* need to restart the autonegotiation process. Read
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* the BMSR twice in case it's latched.
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*/
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reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
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if (reg & BMSR_LINK)
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break;
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/*
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* Only retry autonegotiation every 5 seconds.
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*/
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if (++sc->mii_ticks <= 5/*10*/)
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break;
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sc->mii_ticks = 0;
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mii_phy_auto(sc);
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return (0);
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}
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/* Update the media status. */
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ciphy_status(sc);
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/*
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* Callback if something changed. Note that we need to poke
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* apply fixups for certain PHY revs.
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*/
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if (sc->mii_media_active != mii->mii_media_active ||
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sc->mii_media_status != mii->mii_media_status ||
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cmd == MII_MEDIACHG) {
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ciphy_fixup(sc);
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}
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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ciphy_status(sc)
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struct mii_softc *sc;
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{
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struct mii_data *mii = sc->mii_pdata;
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int bmsr, bmcr;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
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if (bmsr & BMSR_LINK)
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mii->mii_media_status |= IFM_ACTIVE;
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bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
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if (bmcr & CIPHY_BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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if (bmcr & CIPHY_BMCR_AUTOEN) {
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if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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}
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bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
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switch (bmsr & CIPHY_AUXCSR_SPEED) {
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case CIPHY_SPEED10:
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mii->mii_media_active |= IFM_10_T;
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break;
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case CIPHY_SPEED100:
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mii->mii_media_active |= IFM_100_TX;
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break;
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case CIPHY_SPEED1000:
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mii->mii_media_active |= IFM_1000_T;
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break;
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default:
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device_printf(sc->mii_dev, "unknown PHY speed %x\n",
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bmsr & CIPHY_AUXCSR_SPEED);
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break;
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}
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if (bmsr & CIPHY_AUXCSR_FDX)
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mii->mii_media_active |= IFM_FDX;
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return;
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}
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static void
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ciphy_reset(struct mii_softc *sc)
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{
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mii_phy_reset(sc);
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DELAY(1000);
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return;
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}
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#define PHY_SETBIT(x, y, z) \
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PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
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#define PHY_CLRBIT(x, y, z) \
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PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
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static void
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ciphy_fixup(struct mii_softc *sc)
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{
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uint16_t model;
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uint16_t status, speed;
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model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
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status = PHY_READ(sc, CIPHY_MII_AUXCSR);
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speed = status & CIPHY_AUXCSR_SPEED;
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switch (model) {
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case MII_MODEL_CICADA_CS8201:
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/* Turn off "aux mode" (whatever that means) */
|
||||
PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
|
||||
|
||||
/*
|
||||
* Work around speed polling bug in VT3119/VT3216
|
||||
* when using MII in full duplex mode.
|
||||
*/
|
||||
if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
|
||||
(status & CIPHY_AUXCSR_FDX)) {
|
||||
PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
|
||||
} else {
|
||||
PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
|
||||
}
|
||||
|
||||
/* Enable link/activity LED blink. */
|
||||
PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
|
||||
|
||||
break;
|
||||
|
||||
case MII_MODEL_CICADA_CS8201A:
|
||||
case MII_MODEL_CICADA_CS8201B:
|
||||
|
||||
/*
|
||||
* Work around speed polling bug in VT3119/VT3216
|
||||
* when using MII in full duplex mode.
|
||||
*/
|
||||
if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
|
||||
(status & CIPHY_AUXCSR_FDX)) {
|
||||
PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
|
||||
} else {
|
||||
PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
|
||||
model);
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
351
sys/dev/mii/ciphyreg.h
Normal file
351
sys/dev/mii/ciphyreg.h
Normal file
@ -0,0 +1,351 @@
|
||||
/*
|
||||
* Copyright (c) 2004
|
||||
* Bill Paul <wpaul@windriver.com>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _DEV_MII_CIPHYREG_H_
|
||||
#define _DEV_MII_CIPHYREG_H_
|
||||
|
||||
/*
|
||||
* Register definitions for the Cicada CS8201 10/100/1000 gigE copper
|
||||
* PHY, embedded within the VIA Networks VT6122 controller.
|
||||
*/
|
||||
|
||||
/* Command register */
|
||||
#define CIPHY_MII_BMCR 0x00
|
||||
#define CIPHY_BMCR_RESET 0x8000
|
||||
#define CIPHY_BMCR_LOOP 0x4000
|
||||
#define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
|
||||
#define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
|
||||
#define CIPHY_BMCR_PDOWN 0x0800 /* Power down */
|
||||
#define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
|
||||
#define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */
|
||||
#define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */
|
||||
#define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
|
||||
|
||||
#define CIPHY_S1000 CIPHY_BMCR_SPD1 /* 1000mbps */
|
||||
#define CIPHY_S100 CIPHY_BMCR_SPD0 /* 100mpbs */
|
||||
#define CIPHY_S10 0 /* 10mbps */
|
||||
|
||||
/* Status register */
|
||||
#define CIPHY_MII_BMSR 0x01
|
||||
#define CIPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */
|
||||
#define CIPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
|
||||
#define CIPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
|
||||
#define CIPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
|
||||
#define CIPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
|
||||
#define CIPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
|
||||
#define CIPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
|
||||
#define CIPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
|
||||
#define CIPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
|
||||
#define CIPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
|
||||
#define CIPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
|
||||
#define CIPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
|
||||
#define CIPHY_BMSR_LINK 0x0004 /* Link status */
|
||||
#define CIPHY_BMSR_JABBER 0x0002 /* Jabber detected */
|
||||
#define CIPHY_BMSR_EXT 0x0001 /* Extended capability */
|
||||
|
||||
/* PHY ID registers */
|
||||
#define CIPHY_MII_PHYIDR1 0x02
|
||||
#define CIPHY_MII_PHYIDR2 0x03
|
||||
|
||||
/* Autoneg advertisement */
|
||||
#define CIPHY_MII_ANAR 0x04
|
||||
#define CIPHY_ANAR_NP 0x8000 /* Next page */
|
||||
#define CIPHY_ANAR_RF 0x2000 /* Remote fault */
|
||||
#define CIPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */
|
||||
#define CIPHY_ANAR_PC 0x0400 /* Pause capable */
|
||||
#define CIPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */
|
||||
#define CIPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */
|
||||
#define CIPHY_ANAR_TX 0x0080 /* local device supports 100bTx */
|
||||
#define CIPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */
|
||||
#define CIPHY_ANAR_10 0x0020 /* local device supports 10bT */
|
||||
#define CIPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */
|
||||
|
||||
/* Autoneg link partner ability */
|
||||
#define CIPHY_MII_ANLPAR 0x05
|
||||
#define CIPHY_ANLPAR_NP 0x8000 /* Next page */
|
||||
#define CIPHY_ANLPAR_ACK 0x4000 /* link partner acknowledge */
|
||||
#define CIPHY_ANLPAR_RF 0x2000 /* Remote fault */
|
||||
#define CIPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */
|
||||
#define CIPHY_ANLPAR_PC 0x0400 /* Pause capable */
|
||||
#define CIPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */
|
||||
#define CIPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */
|
||||
#define CIPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */
|
||||
#define CIPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */
|
||||
#define CIPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */
|
||||
#define CIPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */
|
||||
|
||||
#define CIPHY_SEL_TYPE 0x0001 /* ethernet */
|
||||
|
||||
/* Antoneg expansion register */
|
||||
#define CIPHY_MII_ANER 0x06
|
||||
#define CIPHY_ANER_PDF 0x0010 /* Parallel detection fault */
|
||||
#define CIPHY_ANER_LPNP 0x0008 /* Link partner can next page */
|
||||
#define CIPHY_ANER_NP 0x0004 /* Local PHY can next page */
|
||||
#define CIPHY_ANER_RX 0x0002 /* Next page received */
|
||||
#define CIPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
|
||||
|
||||
/* Autoneg next page transmit regisyer */
|
||||
#define CIPHY_MII_NEXTP 0x07
|
||||
#define CIPHY_NEXTP_MOREP 0x8000 /* More pages to follow */
|
||||
#define CIPHY_NEXTP_MESS 0x2000 /* 1 = message page, 0 = unformatted */
|
||||
#define CIPHY_NEXTP_ACK2 0x1000 /* MAC acknowledge */
|
||||
#define CIPHY_NEXTP_TOGGLE 0x0800 /* Toggle */
|
||||
#define CIPHY_NEXTP_CODE 0x07FF /* Code bits */
|
||||
|
||||
/* Autoneg link partner next page receive register */
|
||||
#define CIPHY_MII_NEXTP_LP 0x08
|
||||
#define CIPHY_NEXTPLP_MOREP 0x8000 /* More pages to follow */
|
||||
#define CIPHY_NEXTPLP_MESS 0x2000 /* 1 = message page, 0 = unformatted */
|
||||
#define CIPHY_NEXTPLP_ACK2 0x1000 /* MAC acknowledge */
|
||||
#define CIPHY_NEXTPLP_TOGGLE 0x0800 /* Toggle */
|
||||
#define CIPHY_NEXTPLP_CODE 0x07FF /* Code bits */
|
||||
|
||||
/* 1000BT control register */
|
||||
#define CIPHY_MII_1000CTL 0x09
|
||||
#define CIPHY_1000CTL_TST 0xE000 /* test modes */
|
||||
#define CIPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */
|
||||
#define CIPHY_1000CTL_MSC 0x0800 /* Master/Slave select */
|
||||
#define CIPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
|
||||
#define CIPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
|
||||
#define CIPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
|
||||
|
||||
#define CIPHY_TEST_TX_JITTER 0x2000
|
||||
#define CIPHY_TEST_TX_JITTER_MASTER_MODE 0x4000
|
||||
#define CIPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000
|
||||
#define CIPHY_TEST_TX_DISTORTION 0x8000
|
||||
|
||||
/* 1000BT status register */
|
||||
#define CIPHY_MII_1000STS 0x0A
|
||||
#define CIPHY_1000STS_MSF 0x8000 /* Master/slave fault */
|
||||
#define CIPHY_1000STS_MSR 0x4000 /* Master/slave result */
|
||||
#define CIPHY_1000STS_LRS 0x2000 /* Local receiver status */
|
||||
#define CIPHY_1000STS_RRS 0x1000 /* Remote receiver status */
|
||||
#define CIPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
|
||||
#define CIPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
|
||||
#define CIPHY_1000STS_IEC 0x00FF /* Idle error count */
|
||||
|
||||
#define CIPHY_MII_EXTSTS 0x0F /* Extended status */
|
||||
#define CIPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
|
||||
#define CIPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
|
||||
#define CIPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
|
||||
#define CIPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
|
||||
|
||||
/* 1000BT status extension register #1 */
|
||||
#define CIPHY_MII_1000STS1 0x0F
|
||||
#define CIPHY_1000STS1_1000XFDX 0x8000 /* 1000baseX FDX capable */
|
||||
#define CIPHY_1000STS1_1000XHDX 0x4000 /* 1000baseX HDX capable */
|
||||
#define CIPHY_1000STS1_1000TFDX 0x2000 /* 1000baseT FDX capable */
|
||||
#define CIPHY_1000STS1_1000THDX 0x1000 /* 1000baseT HDX capable */
|
||||
|
||||
/* Vendor-specific PHY registers */
|
||||
|
||||
/* 100baseTX status extention register */
|
||||
#define CIPHY_MII_100STS 0x10
|
||||
#define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */
|
||||
#define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */
|
||||
#define CIPHY_100STS_DISC 0x2000 /* disconnect state */
|
||||
#define CIPHY_100STS_LINK 0x1000 /* current link state */
|
||||
#define CIPHY_100STS_RXERR 0x0800 /* receive error detected */
|
||||
#define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */
|
||||
#define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */
|
||||
#define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */
|
||||
|
||||
/* 1000BT status extention register #2 */
|
||||
#define CIPHY_MII_1000STS2 0x11
|
||||
#define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */
|
||||
#define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */
|
||||
#define CIPHY_1000STS2_DISC 0x2000 /* disconnect state */
|
||||
#define CIPHY_1000STS2_LINK 0x1000 /* current link state */
|
||||
#define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */
|
||||
#define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */
|
||||
#define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */
|
||||
#define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */
|
||||
#define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extention err detected */
|
||||
#define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */
|
||||
|
||||
/* Bypass control register */
|
||||
#define CIPHY_MII_BYPASS 0x12
|
||||
#define CIPHY_BYPASS_TX 0x8000 /* transmit disable */
|
||||
#define CIPHY_BYPASS_4B5B 0x4000 /* bypass the 4B5B encoder */
|
||||
#define CIPHY_BYPASS_SCRAM 0x2000 /* bypass scrambler */
|
||||
#define CIPHY_BYPASS_DSCAM 0x1000 /* bypass descrambler */
|
||||
#define CIPHY_BYPASS_PCSRX 0x0800 /* bypass PCS receive */
|
||||
#define CIPHY_BYPASS_PCSTX 0x0400 /* bypass PCS transmit */
|
||||
#define CIPHY_BYPASS_LFI 0x0200 /* bypass LFI timer */
|
||||
#define CIPHY_BYPASS_TXCLK 0x0100 /* enable transmit clock on LED4 pin */
|
||||
#define CIPHY_BYPASS_BCM5400_F 0x0080 /* force BCM5400 detect */
|
||||
#define CIPHY_BYPASS_BCM5400 0x0040 /* bypass BCM5400 detect */
|
||||
#define CIPHY_BYPASS_PAIRSWAP 0x0020 /* disable automatic pair swap */
|
||||
#define CIPHY_BYPASS_POLARITY 0x0010 /* disable polarity correction */
|
||||
#define CIPHY_BYPASS_PARALLEL 0x0008 /* parallel detect enable */
|
||||
#define CIPHY_BYPASS_PULSE 0x0004 /* disable pulse shaping filter */
|
||||
#define CIPHY_BYPASS_1000BNP 0x0002 /* disable 1000BT next page exchange */
|
||||
|
||||
/* RX error count register */
|
||||
#define CIPHY_MII_RXERR 0x13
|
||||
|
||||
/* False carrier sense count register */
|
||||
#define CIPHY_MII_FCSERR 0x14
|
||||
|
||||
/* Ddisconnect error counter */
|
||||
#define CIPHY_MII_DISCERR 0x15
|
||||
|
||||
/* 10baseT control/status register */
|
||||
#define CIPHY_MII_10BTCSR 0x16
|
||||
#define CIPHY_10BTCSR_DLIT 0x8000 /* Disable data link integrity test */
|
||||
#define CIPHY_10BTCSR_JABBER 0x4000 /* Disable jabber detect */
|
||||
#define CIPHY_10BTCSR_ECHO 0x2000 /* Disable echo mode */
|
||||
#define CIPHY_10BTCSR_SQE 0x1000 /* Disable signal quality error */
|
||||
#define CIPHY_10BTCSR_SQUENCH 0x0C00 /* Squelch control */
|
||||
#define CIPHY_10BTCSR_EOFERR 0x0100 /* End of Frame error */
|
||||
#define CIPHY_10BTCSR_DISC 0x0080 /* Disconnect status */
|
||||
#define CIPHY_10BTCSR_LINK 0x0040 /* current link state */
|
||||
#define CIPHY_10BTCSR_ITRIM 0x0038 /* current reference trim */
|
||||
#define CIPHY_10BTCSR_CSR 0x0006 /* CSR behavior control */
|
||||
|
||||
#define CIPHY_SQUELCH_300MV 0x0000
|
||||
#define CIPHY_SQUELCH_197MV 0x0400
|
||||
#define CIPHY_SQUELCH_450MV 0x0800
|
||||
#define CIPHY_SQUELCH_RSVD 0x0C00
|
||||
|
||||
#define CIPHY_ITRIM_PLUS2 0x0000
|
||||
#define CIPHY_ITRIM_PLUS4 0x0008
|
||||
#define CIPHY_ITRIM_PLUS6 0x0010
|
||||
#define CIPHY_ITRIM_PLUS6_ 0x0018
|
||||
#define CIPHY_ITRIM_MINUS4 0x0020
|
||||
#define CIPHY_ITRIM_MINUS4_ 0x0028
|
||||
#define CIPHY_ITRIM_MINUS2 0x0030
|
||||
#define CIPHY_ITRIM_ZERO 0x0038
|
||||
|
||||
/* Extended PHY control register #1 */
|
||||
#define CIPHY_MII_ECTL1 0x17
|
||||
#define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */
|
||||
|
||||
/* Extended PHY control register #2 */
|
||||
#define CIPHY_MII_ECTL2 0x18
|
||||
#define CIPHY_ECTL2_ERATE 0xE000 /* 10/1000 edge rate control */
|
||||
#define CIPHY_ECTL2_VTRIM 0x1C00 /* voltage reference trim */
|
||||
#define CIPHY_ECTL2_CABLELEN 0x000E /* Cable quality/length */
|
||||
#define CIPHY_ECTL2_ANALOGLOOP 0x0001 /* 1000BT analog loopback */
|
||||
|
||||
#define CIPHY_CABLELEN_0TO10M 0x0000
|
||||
#define CIPHY_CABLELEN_10TO20M 0x0002
|
||||
#define CIPHY_CABLELEN_20TO40M 0x0004
|
||||
#define CIPHY_CABLELEN_40TO80M 0x0006
|
||||
#define CIPHY_CABLELEN_80TO100M 0x0008
|
||||
#define CIPHY_CABLELEN_100TO140M 0x000A
|
||||
#define CIPHY_CABLELEN_140TO180M 0x000C
|
||||
#define CIPHY_CABLELEN_OVER180M 0x000E
|
||||
|
||||
/* Interrupt mask register */
|
||||
#define CIPHY_MII_IMR 0x19
|
||||
#define CIPHY_IMR_PINENABLE 0x8000 /* Interrupt pin enable */
|
||||
#define CIPHY_IMR_SPEED 0x4000 /* speed changed event */
|
||||
#define CIPHY_IMR_LINK 0x2000 /* link change/ActiPHY event */
|
||||
#define CIPHY_IMR_DPX 0x1000 /* duplex change event */
|
||||
#define CIPHY_IMR_ANEGERR 0x0800 /* autoneg error event */
|
||||
#define CIPHY_IMR_ANEGDONE 0x0400 /* autoneg done event */
|
||||
#define CIPHY_IMR_NPRX 0x0200 /* page received event */
|
||||
#define CIPHY_IMR_SYMERR 0x0100 /* symbol error event */
|
||||
#define CIPHY_IMR_LOCKERR 0x0080 /* descrambler lock lost event */
|
||||
#define CIPHY_IMR_XOVER 0x0040 /* MDI crossover change event */
|
||||
#define CIPHY_IMR_POLARITY 0x0020 /* polarity change event */
|
||||
#define CIPHY_IMR_JABBER 0x0010 /* jabber detect event */
|
||||
#define CIPHY_IMR_SSDERR 0x0008 /* false carrier detect event */
|
||||
#define CIPHY_IMR_ESDERR 0x0004 /* parallel detect error event */
|
||||
#define CIPHY_IMR_MASTERSLAVE 0x0002 /* master/slave resolve done event */
|
||||
#define CIPHY_IMR_RXERR 0x0001 /* RX error event */
|
||||
|
||||
/* Interrupt status register */
|
||||
#define CIPHY_MII_ISR 0x1A
|
||||
#define CIPHY_ISR_IPENDING 0x8000 /* Interrupt is pending */
|
||||
#define CIPHY_ISR_SPEED 0x4000 /* speed changed event */
|
||||
#define CIPHY_ISR_LINK 0x2000 /* link change/ActiPHY event */
|
||||
#define CIPHY_ISR_DPX 0x1000 /* duplex change event */
|
||||
#define CIPHY_ISR_ANEGERR 0x0800 /* autoneg error event */
|
||||
#define CIPHY_ISR_ANEGDONE 0x0400 /* autoneg done event */
|
||||
#define CIPHY_ISR_NPRX 0x0200 /* page received event */
|
||||
#define CIPHY_ISR_SYMERR 0x0100 /* symbol error event */
|
||||
#define CIPHY_ISR_LOCKERR 0x0080 /* descrambler lock lost event */
|
||||
#define CIPHY_ISR_XOVER 0x0040 /* MDI crossover change event */
|
||||
#define CIPHY_ISR_POLARITY 0x0020 /* polarity change event */
|
||||
#define CIPHY_ISR_JABBER 0x0010 /* jabber detect event */
|
||||
#define CIPHY_ISR_SSDERR 0x0008 /* false carrier detect event */
|
||||
#define CIPHY_ISR_ESDERR 0x0004 /* parallel detect error event */
|
||||
#define CIPHY_ISR_MASTERSLAVE 0x0002 /* master/slave resolve done event */
|
||||
#define CIPHY_ISR_RXERR 0x0001 /* RX error event */
|
||||
|
||||
/* LED control register */
|
||||
#define CIPHY_MII_LED 0x1B
|
||||
#define CIPHY_LED_LINK10FORCE 0x8000 /* Force on link10 LED */
|
||||
#define CIPHY_LED_LINK10DIS 0x4000 /* Disable link10 LED */
|
||||
#define CIPHY_LED_LINK100FORCE 0x2000 /* Force on link10 LED */
|
||||
#define CIPHY_LED_LINK100DIS 0x1000 /* Disable link100 LED */
|
||||
#define CIPHY_LED_LINK1000FORCE 0x0800 /* Force on link1000 LED */
|
||||
#define CIPHY_LED_LINK1000DIS 0x0400 /* Disable link1000 LED */
|
||||
#define CIPHY_LED_FDXFORCE 0x0200 /* Force on duplex LED */
|
||||
#define CIPHY_LED_FDXDIS 0x0100 /* Disable duplex LED */
|
||||
#define CIPHY_LED_ACTFORCE 0x0080 /* Force on activity LED */
|
||||
#define CIPHY_LED_ACTDIS 0x0040 /* Disable activity LED */
|
||||
#define CIPHY_LED_PULSE 0x0008 /* LED pulse enable */
|
||||
#define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */
|
||||
#define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */
|
||||
|
||||
/* Auxilliary control and status register */
|
||||
#define CIPHY_MII_AUXCSR 0x1C
|
||||
#define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */
|
||||
#define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */
|
||||
#define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */
|
||||
#define CIPHY_AUXCSR_PAIRSWAP 0x1000 /* pair swap indication */
|
||||
#define CIPHY_AUXCSR_APOLARITY 0x0800 /* polarity inversion pair A */
|
||||
#define CIPHY_AUXCSR_BPOLARITY 0x0400 /* polarity inversion pair B */
|
||||
#define CIPHY_AUXCSR_CPOLARITY 0x0200 /* polarity inversion pair C */
|
||||
#define CIPHY_AUXCSR_DPOLARITY 0x0100 /* polarity inversion pair D */
|
||||
#define CIPHY_AUXCSR_FDX 0x0020 /* duplex 1=full, 0=half */
|
||||
#define CIPHY_AUXCSR_SPEED 0x0018 /* speed */
|
||||
#define CIPHY_AUXCSR_MDPPS 0x0004 /* No idea, not documented */
|
||||
#define CIPHY_AUXCSR_STICKYREST 0x0002 /* reset clears sticky bits */
|
||||
|
||||
#define CIPHY_SPEED10 0x0000
|
||||
#define CIPHY_SPEED100 0x0008
|
||||
#define CIPHY_SPEED1000 0x0010
|
||||
|
||||
/* Delay skew status register */
|
||||
#define CIPHY_MII_DSKEW 0x1D
|
||||
#define CIPHY_DSKEW_PAIRA 0x7000 /* Pair A skew in symbol times */
|
||||
#define CIPHY_DSKEW_PAIRB 0x0700 /* Pair B skew in symbol times */
|
||||
#define CIPHY_DSKEW_PAIRC 0x0070 /* Pair C skew in symbol times */
|
||||
#define CIPHY_DSKEW_PAIRD 0x0007 /* Pair D skew in symbol times */
|
||||
|
||||
#endif /* _DEV_CIPHY_MIIREG_H_ */
|
||||
@ -52,6 +52,7 @@ $FreeBSD$
|
||||
oui ALTIMA 0x0010a9 Altima Communications
|
||||
oui AMD 0x00001a Advanced Micro Devices
|
||||
oui BROADCOM 0x001018 Broadcom Corporation
|
||||
oui CICADA 0x0003F1 Cicada Semiconductor
|
||||
oui DAVICOM 0x00606e Davicom Semiconductor
|
||||
oui ICS 0x00a0be Integrated Circuit Systems
|
||||
oui INTEL 0x00aa00 Intel
|
||||
@ -121,6 +122,11 @@ model xxBROADCOM BCM5703 0x0016 BCM5703 10/100/1000baseTX PHY
|
||||
model xxBROADCOM BCM5704 0x0019 BCM5704 10/100/1000baseTX PHY
|
||||
model xxBROADCOM BCM5705 0x001a BCM5705 10/100/1000baseTX PHY
|
||||
|
||||
/* Cicada Semiconductor PHYs (now owned by Vitesse?) */
|
||||
model CICADA CS8201 0x0001 Cicada CS8201 10/100/1000TX PHY
|
||||
model CICADA CS8201A 0x0020 Cicada CS8201 10/100/1000TX PHY
|
||||
model CICADA CS8201B 0x0021 Cicada CS8201 10/100/1000TX PHY
|
||||
|
||||
/* Davicom Semiconductor PHYs */
|
||||
model xxDAVICOM DM9101 0x0000 DM9101 10/100 media interface
|
||||
|
||||
|
||||
2445
sys/dev/vge/if_vge.c
Normal file
2445
sys/dev/vge/if_vge.c
Normal file
File diff suppressed because it is too large
Load Diff
697
sys/dev/vge/if_vgereg.h
Normal file
697
sys/dev/vge/if_vgereg.h
Normal file
@ -0,0 +1,697 @@
|
||||
/*
|
||||
* Copyright (c) 2004
|
||||
* Bill Paul <wpaul@windriver.com>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Register definitions for the VIA VT6122 gigabit ethernet controller.
|
||||
* Definitions for the built-in copper PHY can be found in vgphy.h.
|
||||
*
|
||||
* The VT612x controllers have 256 bytes of register space. The
|
||||
* manual seems to imply that the registers should all be accessed
|
||||
* using 32-bit I/O cycles, but some of them are less than 32 bits
|
||||
* wide. Go figure.
|
||||
*/
|
||||
|
||||
#ifndef _IF_VGEREG_H_
|
||||
#define _IF_VGEREG_H_
|
||||
|
||||
#define VIA_VENDORID 0x1106
|
||||
#define VIA_DEVICEID_61XX 0x3119
|
||||
|
||||
#define VGE_PAR0 0x00 /* physical address register */
|
||||
#define VGE_PAR1 0x02
|
||||
#define VGE_PAR2 0x04
|
||||
#define VGE_RXCTL 0x06 /* RX control register */
|
||||
#define VGE_TXCTL 0x07 /* TX control register */
|
||||
#define VGE_CRS0 0x08 /* Global cmd register 0 (w to set) */
|
||||
#define VGE_CRS1 0x09 /* Global cmd register 1 (w to set) */
|
||||
#define VGE_CRS2 0x0A /* Global cmd register 2 (w to set) */
|
||||
#define VGE_CRS3 0x0B /* Global cmd register 3 (w to set) */
|
||||
#define VGE_CRC0 0x0C /* Global cmd register 0 (w to clr) */
|
||||
#define VGE_CRC1 0x0D /* Global cmd register 1 (w to clr) */
|
||||
#define VGE_CRC2 0x0E /* Global cmd register 2 (w to clr) */
|
||||
#define VGE_CRC3 0x0F /* Global cmd register 3 (w to clr) */
|
||||
#define VGE_MAR0 0x10 /* Mcast hash/CAM register 0 */
|
||||
#define VGE_MAR1 0x14 /* Mcast hash/CAM register 1 */
|
||||
#define VGE_CAM0 0x10
|
||||
#define VGE_CAM1 0x11
|
||||
#define VGE_CAM2 0x12
|
||||
#define VGE_CAM3 0x13
|
||||
#define VGE_CAM4 0x14
|
||||
#define VGE_CAM5 0x15
|
||||
#define VGE_CAM6 0x16
|
||||
#define VGE_CAM7 0x17
|
||||
#define VGE_TXDESC_HIADDR 0x18 /* Hi part of 64bit txdesc base addr */
|
||||
#define VGE_DATABUF_HIADDR 0x1D /* Hi part of 64bit data buffer addr */
|
||||
#define VGE_INTCTL0 0x20 /* interrupt control register */
|
||||
#define VGE_RXSUPPTHR 0x20
|
||||
#define VGE_TXSUPPTHR 0x20
|
||||
#define VGE_INTHOLDOFF 0x20
|
||||
#define VGE_INTCTL1 0x21 /* interrupt control register */
|
||||
#define VGE_TXHOSTERR 0x22 /* TX host error status */
|
||||
#define VGE_RXHOSTERR 0x23 /* RX host error status */
|
||||
#define VGE_ISR 0x24 /* Interrupt status register */
|
||||
#define VGE_IMR 0x28 /* Interrupt mask register */
|
||||
#define VGE_TXSTS_PORT 0x2C /* Transmit status port (???) */
|
||||
#define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */
|
||||
#define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */
|
||||
#define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */
|
||||
#define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */
|
||||
#define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */
|
||||
#define VGE_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */
|
||||
#define VGE_RXQTIMER 0x3E /* RX queue timer pend register */
|
||||
#define VGE_TXQTIMER 0x3F /* TX queue timer pend register */
|
||||
#define VGE_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */
|
||||
#define VGE_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */
|
||||
#define VGE_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */
|
||||
#define VGE_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */
|
||||
#define VGE_RXDESCNUM 0x50 /* Size of RX desc ring */
|
||||
#define VGE_TXDESCNUM 0x52 /* Size of TX desc ring */
|
||||
#define VGE_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */
|
||||
#define VGE_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */
|
||||
#define VGE_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */
|
||||
#define VGE_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */
|
||||
#define VGE_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */
|
||||
#define VGE_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */
|
||||
#define VGE_FIFOTEST0 0x60 /* FIFO test register */
|
||||
#define VGE_FIFOTEST1 0x64 /* FIFO test register */
|
||||
#define VGE_CAMADDR 0x68 /* CAM address register */
|
||||
#define VGE_CAMCTL 0x69 /* CAM control register */
|
||||
#define VGE_GFTEST 0x6A
|
||||
#define VGE_FTSCMD 0x6B
|
||||
#define VGE_MIICFG 0x6C /* MII port config register */
|
||||
#define VGE_MIISTS 0x6D /* MII port status register */
|
||||
#define VGE_PHYSTS0 0x6E /* PHY status register */
|
||||
#define VGE_PHYSTS1 0x6F /* PHY status register */
|
||||
#define VGE_MIICMD 0x70 /* MII command register */
|
||||
#define VGE_MIIADDR 0x71 /* MII address register */
|
||||
#define VGE_MIIDATA 0x72 /* MII data register */
|
||||
#define VGE_SSTIMER 0x74 /* single-shot timer */
|
||||
#define VGE_PTIMER 0x76 /* periodic timer */
|
||||
#define VGE_CHIPCFG0 0x78 /* chip config A */
|
||||
#define VGE_CHIPCFG1 0x79 /* chip config B */
|
||||
#define VGE_CHIPCFG2 0x7A /* chip config C */
|
||||
#define VGE_CHIPCFG3 0x7B /* chip config D */
|
||||
#define VGE_DMACFG0 0x7C /* DMA config 0 */
|
||||
#define VGE_DMACFG1 0x7D /* DMA config 1 */
|
||||
#define VGE_RXCFG 0x7E /* MAC RX config */
|
||||
#define VGE_TXCFG 0x7F /* MAC TX config */
|
||||
#define VGE_PWRMGMT 0x82 /* power management shadow register */
|
||||
#define VGE_PWRSTAT 0x83 /* power state shadow register */
|
||||
#define VGE_MIBCSR 0x84 /* MIB control/status register */
|
||||
#define VGE_SWEEDATA 0x85 /* EEPROM software loaded data */
|
||||
#define VGE_MIBDATA 0x88 /* MIB data register */
|
||||
#define VGE_EEWRDAT 0x8C /* EEPROM embedded write */
|
||||
#define VGE_EECSUM 0x92 /* EEPROM checksum */
|
||||
#define VGE_EECSR 0x93 /* EEPROM control/status */
|
||||
#define VGE_EERDDAT 0x94 /* EEPROM embedded read */
|
||||
#define VGE_EEADDR 0x96 /* EEPROM address */
|
||||
#define VGE_EECMD 0x97 /* EEPROM embedded command */
|
||||
#define VGE_CHIPSTRAP 0x99 /* Chip jumper strapping status */
|
||||
#define VGE_MEDIASTRAP 0x9B /* Media jumper strapping */
|
||||
#define VGE_DIAGSTS 0x9C /* Chip diagnostic status */
|
||||
#define VGE_DBGCTL 0x9E /* Chip debug control */
|
||||
#define VGE_DIAGCTL 0x9F /* Chip diagnostic control */
|
||||
#define VGE_WOLCR0S 0xA0 /* WOL0 event set */
|
||||
#define VGE_WOLCR1S 0xA1 /* WOL1 event set */
|
||||
#define VGE_PWRCFGS 0xA2 /* Power management config set */
|
||||
#define VGE_WOLCFGS 0xA3 /* WOL config set */
|
||||
#define VGE_WOLCR0C 0xA4 /* WOL0 event clear */
|
||||
#define VGE_WOLCR1C 0xA5 /* WOL1 event clear */
|
||||
#define VGE_PWRCFGC 0xA6 /* Power management config clear */
|
||||
#define VGE_WOLCFGC 0xA7 /* WOL config clear */
|
||||
#define VGE_WOLSR0S 0xA8 /* WOL status set */
|
||||
#define VGE_WOLSR1S 0xA9 /* WOL status set */
|
||||
#define VGE_WOLSR0C 0xAC /* WOL status clear */
|
||||
#define VGE_WOLSR1C 0xAD /* WOL status clear */
|
||||
#define VGE_WAKEPAT_CRC0 0xB0
|
||||
#define VGE_WAKEPAT_CRC1 0xB2
|
||||
#define VGE_WAKEPAT_CRC2 0xB4
|
||||
#define VGE_WAKEPAT_CRC3 0xB6
|
||||
#define VGE_WAKEPAT_CRC4 0xB8
|
||||
#define VGE_WAKEPAT_CRC5 0xBA
|
||||
#define VGE_WAKEPAT_CRC6 0xBC
|
||||
#define VGE_WAKEPAT_CRC7 0xBE
|
||||
#define VGE_WAKEPAT_MSK0_0 0xC0
|
||||
#define VGE_WAKEPAT_MSK0_1 0xC4
|
||||
#define VGE_WAKEPAT_MSK0_2 0xC8
|
||||
#define VGE_WAKEPAT_MSK0_3 0xCC
|
||||
#define VGE_WAKEPAT_MSK1_0 0xD0
|
||||
#define VGE_WAKEPAT_MSK1_1 0xD4
|
||||
#define VGE_WAKEPAT_MSK1_2 0xD8
|
||||
#define VGE_WAKEPAT_MSK1_3 0xDC
|
||||
#define VGE_WAKEPAT_MSK2_0 0xE0
|
||||
#define VGE_WAKEPAT_MSK2_1 0xE4
|
||||
#define VGE_WAKEPAT_MSK2_2 0xE8
|
||||
#define VGE_WAKEPAT_MSK2_3 0xEC
|
||||
#define VGE_WAKEPAT_MSK3_0 0xF0
|
||||
#define VGE_WAKEPAT_MSK3_1 0xF4
|
||||
#define VGE_WAKEPAT_MSK3_2 0xF8
|
||||
#define VGE_WAKEPAT_MSK3_3 0xFC
|
||||
|
||||
/* Receive control register */
|
||||
|
||||
#define VGE_RXCTL_RX_BADFRAMES 0x01 /* accept CRC error frames */
|
||||
#define VGE_RXCTL_RX_RUNT 0x02 /* accept runts */
|
||||
#define VGE_RXCTL_RX_MCAST 0x04 /* accept multicasts */
|
||||
#define VGE_RXCTL_RX_BCAST 0x08 /* accept broadcasts */
|
||||
#define VGE_RXCTL_RX_PROMISC 0x10 /* promisc mode */
|
||||
#define VGE_RXCTL_RX_GIANT 0x20 /* accept VLAN tagged frames */
|
||||
#define VGE_RXCTL_RX_UCAST 0x40 /* use perfect filtering */
|
||||
#define VGE_RXCTL_RX_SYMERR 0x80 /* accept symbol err packet */
|
||||
|
||||
/* Transmit control register */
|
||||
|
||||
#define VGE_TXCTL_LOOPCTL 0x03 /* loopback control */
|
||||
#define VGE_TXCTL_COLLCTL 0x0C /* collision retry control */
|
||||
|
||||
#define VGE_TXLOOPCTL_OFF 0x00
|
||||
#define VGE_TXLOOPCTL_MAC_INTERNAL 0x01
|
||||
#define VGE_TXLOOPCTL_EXTERNAL 0x02
|
||||
|
||||
#define VGE_TXCOLLS_NORMAL 0x00 /* one set of 16 retries */
|
||||
#define VGE_TXCOLLS_32 0x04 /* two sets of 16 retries */
|
||||
#define VGE_TXCOLLS_48 0x08 /* three sets of 16 retries */
|
||||
#define VGE_TXCOLLS_INFINITE 0x0C /* retry forever */
|
||||
|
||||
/* Global command register 0 */
|
||||
|
||||
#define VGE_CR0_START 0x01 /* start NIC */
|
||||
#define VGE_CR0_STOP 0x02 /* stop NIC */
|
||||
#define VGE_CR0_RX_ENABLE 0x04 /* turn on RX engine */
|
||||
#define VGE_CR0_TX_ENABLE 0x08 /* turn on TX engine */
|
||||
|
||||
/* Global command register 1 */
|
||||
|
||||
#define VGE_CR1_NOUCAST 0x01 /* disable unicast reception */
|
||||
#define VGE_CR1_NOPOLL 0x08 /* disable RX/TX desc polling */
|
||||
#define VGE_CR1_TIMER0_ENABLE 0x20 /* enable single shot timer */
|
||||
#define VGE_CR1_TIMER1_ENABLE 0x40 /* enable periodic timer */
|
||||
#define VGE_CR1_SOFTRESET 0x80 /* software reset */
|
||||
|
||||
/* Global command register 2 */
|
||||
|
||||
#define VGE_CR2_TXPAUSE_THRESH_LO 0x03 /* TX pause frame lo threshold */
|
||||
#define VGE_CR2_TXPAUSE_THRESH_HI 0x0C /* TX pause frame hi threshold */
|
||||
#define VGE_CR2_HDX_FLOWCTL_ENABLE 0x10 /* half duplex flow control */
|
||||
#define VGE_CR2_FDX_RXFLOWCTL_ENABLE 0x20 /* full duplex RX flow control */
|
||||
#define VGE_CR2_FDX_TXFLOWCTL_ENABLE 0x40 /* full duplex TX flow control */
|
||||
#define VGE_CR2_XON_ENABLE 0x80 /* 802.3x XON/XOFF flow control */
|
||||
|
||||
/* Global command register 3 */
|
||||
|
||||
#define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */
|
||||
#define VGE_CR3_INT_GMSK 0x02 /* mask off all interrupts */
|
||||
#define VGE_CR3_INT_HOLDOFF 0x04 /* enable int hold off timer */
|
||||
#define VGE_CR3_DIAG 0x10 /* diagnostic enabled */
|
||||
#define VGE_CR3_PHYRST 0x20 /* assert PHYRSTZ */
|
||||
#define VGE_CR3_STOP_FORCE 0x40 /* force NIC to stopped state */
|
||||
|
||||
/* Interrupt control register */
|
||||
|
||||
#define VGE_INTCTL_SC_RELOAD 0x01 /* reload hold timer */
|
||||
#define VGE_INTCTL_HC_RELOAD 0x02 /* enable hold timer reload */
|
||||
#define VGE_INTCTL_STATUS 0x04 /* interrupt pending status */
|
||||
#define VGE_INTCTL_MASK 0x18 /* multilayer int mask */
|
||||
#define VGE_INTCTL_RXINTSUP_DISABLE 0x20 /* disable RX int supression */
|
||||
#define VGE_INTCTL_TXINTSUP_DISABLE 0x40 /* disable TX int supression */
|
||||
#define VGE_INTCTL_SOFTINT 0x80 /* request soft interrupt */
|
||||
|
||||
#define VGE_INTMASK_LAYER0 0x00
|
||||
#define VGE_INTMASK_LAYER1 0x08
|
||||
#define VGE_INTMASK_ALL 0x10
|
||||
#define VGE_INTMASK_ALL2 0x18
|
||||
|
||||
/* Transmit host error status register */
|
||||
|
||||
#define VGE_TXHOSTERR_TDSTRUCT 0x01 /* bad TX desc structure */
|
||||
#define VGE_TXHOSTERR_TDFETCH_BUSERR 0x02 /* bus error on desc fetch */
|
||||
#define VGE_TXHOSTERR_TDWBACK_BUSERR 0x04 /* bus error on desc writeback */
|
||||
#define VGE_TXHOSTERR_FIFOERR 0x08 /* TX FIFO DMA bus error */
|
||||
|
||||
/* Receive host error status register */
|
||||
|
||||
#define VGE_RXHOSTERR_RDSTRUCT 0x01 /* bad RX desc structure */
|
||||
#define VGE_RXHOSTERR_RDFETCH_BUSERR 0x02 /* bus error on desc fetch */
|
||||
#define VGE_RXHOSTERR_RDWBACK_BUSERR 0x04 /* bus error on desc writeback */
|
||||
#define VGE_RXHOSTERR_FIFOERR 0x08 /* RX FIFO DMA bus error */
|
||||
|
||||
/* Interrupt status register */
|
||||
|
||||
#define VGE_ISR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */
|
||||
#define VGE_ISR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */
|
||||
#define VGE_ISR_RXOK 0x00000004 /* normal RX done */
|
||||
#define VGE_ISR_TXOK 0x00000008 /* combo results for next 4 bits */
|
||||
#define VGE_ISR_TXOK0 0x00000010 /* TX complete on queue 0 */
|
||||
#define VGE_ISR_TXOK1 0x00000020 /* TX complete on queue 1 */
|
||||
#define VGE_ISR_TXOK2 0x00000040 /* TX complete on queue 2 */
|
||||
#define VGE_ISR_TXOK3 0x00000080 /* TX complete on queue 3 */
|
||||
#define VGE_ISR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */
|
||||
#define VGE_ISR_RXPAUSE 0x00000800 /* pause frame RX'ed */
|
||||
#define VGE_ISR_RXOFLOW 0x00001000 /* RX FIFO overflow */
|
||||
#define VGE_ISR_RXNODESC 0x00002000 /* ran out of RX descriptors */
|
||||
#define VGE_ISR_RXNODESC_WARN 0x00004000 /* running out of RX descs */
|
||||
#define VGE_ISR_LINKSTS 0x00008000 /* link status change */
|
||||
#define VGE_ISR_TIMER0 0x00010000 /* one shot timer expired */
|
||||
#define VGE_ISR_TIMER1 0x00020000 /* periodic timer expired */
|
||||
#define VGE_ISR_PWR 0x00040000 /* wake up power event */
|
||||
#define VGE_ISR_PHYINT 0x00080000 /* PHY interrupt */
|
||||
#define VGE_ISR_STOPPED 0x00100000 /* software shutdown complete */
|
||||
#define VGE_ISR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */
|
||||
#define VGE_ISR_SOFTINT 0x00400000 /* software interrupt */
|
||||
#define VGE_ISR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */
|
||||
#define VGE_ISR_RXDMA_STALL 0x01000000 /* RX DMA stall */
|
||||
#define VGE_ISR_TXDMA_STALL 0x02000000 /* TX DMA STALL */
|
||||
#define VGE_ISR_ISRC0 0x10000000 /* interrupt source indication */
|
||||
#define VGE_ISR_ISRC1 0x20000000 /* interrupt source indication */
|
||||
#define VGE_ISR_ISRC2 0x40000000 /* interrupt source indication */
|
||||
#define VGE_ISR_ISRC3 0x80000000 /* interrupt source indication */
|
||||
|
||||
#define VGE_INTRS (VGE_ISR_TXOK0|VGE_ISR_RXOK|VGE_ISR_STOPPED| \
|
||||
VGE_ISR_RXOFLOW|VGE_ISR_PHYINT| \
|
||||
VGE_ISR_LINKSTS|VGE_ISR_RXNODESC| \
|
||||
VGE_ISR_RXDMA_STALL|VGE_ISR_TXDMA_STALL| \
|
||||
VGE_ISR_MIBOFLOW|VGE_ISR_TIMER0)
|
||||
|
||||
/* Interrupt mask register */
|
||||
|
||||
#define VGE_IMR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */
|
||||
#define VGE_IMR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */
|
||||
#define VGE_IMR_RXOK 0x00000004 /* normal RX done */
|
||||
#define VGE_IMR_TXOK 0x00000008 /* combo results for next 4 bits */
|
||||
#define VGE_IMR_TXOK0 0x00000010 /* TX complete on queue 0 */
|
||||
#define VGE_IMR_TXOK1 0x00000020 /* TX complete on queue 1 */
|
||||
#define VGE_IMR_TXOK2 0x00000040 /* TX complete on queue 2 */
|
||||
#define VGE_IMR_TXOK3 0x00000080 /* TX complete on queue 3 */
|
||||
#define VGE_IMR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */
|
||||
#define VGE_IMR_RXPAUSE 0x00000800 /* pause frame RX'ed */
|
||||
#define VGE_IMR_RXOFLOW 0x00001000 /* RX FIFO overflow */
|
||||
#define VGE_IMR_RXNODESC 0x00002000 /* ran out of RX descriptors */
|
||||
#define VGE_IMR_RXNODESC_WARN 0x00004000 /* running out of RX descs */
|
||||
#define VGE_IMR_LINKSTS 0x00008000 /* link status change */
|
||||
#define VGE_IMR_TIMER0 0x00010000 /* one shot timer expired */
|
||||
#define VGE_IMR_TIMER1 0x00020000 /* periodic timer expired */
|
||||
#define VGE_IMR_PWR 0x00040000 /* wake up power event */
|
||||
#define VGE_IMR_PHYINT 0x00080000 /* PHY interrupt */
|
||||
#define VGE_IMR_STOPPED 0x00100000 /* software shutdown complete */
|
||||
#define VGE_IMR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */
|
||||
#define VGE_IMR_SOFTINT 0x00400000 /* software interrupt */
|
||||
#define VGE_IMR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */
|
||||
#define VGE_IMR_RXDMA_STALL 0x01000000 /* RX DMA stall */
|
||||
#define VGE_IMR_TXDMA_STALL 0x02000000 /* TX DMA STALL */
|
||||
#define VGE_IMR_ISRC0 0x10000000 /* interrupt source indication */
|
||||
#define VGE_IMR_ISRC1 0x20000000 /* interrupt source indication */
|
||||
#define VGE_IMR_ISRC2 0x40000000 /* interrupt source indication */
|
||||
#define VGE_IMR_ISRC3 0x80000000 /* interrupt source indication */
|
||||
|
||||
/* TX descriptor queue control/status register */
|
||||
|
||||
#define VGE_TXQCSR_RUN0 0x0001 /* Enable TX queue 0 */
|
||||
#define VGE_TXQCSR_ACT0 0x0002 /* queue 0 active indicator */
|
||||
#define VGE_TXQCSR_WAK0 0x0004 /* Wake up (poll) queue 0 */
|
||||
#define VGE_TXQCST_DEAD0 0x0008 /* queue 0 dead indicator */
|
||||
#define VGE_TXQCSR_RUN1 0x0010 /* Enable TX queue 1 */
|
||||
#define VGE_TXQCSR_ACT1 0x0020 /* queue 1 active indicator */
|
||||
#define VGE_TXQCSR_WAK1 0x0040 /* Wake up (poll) queue 1 */
|
||||
#define VGE_TXQCST_DEAD1 0x0080 /* queue 1 dead indicator */
|
||||
#define VGE_TXQCSR_RUN2 0x0100 /* Enable TX queue 2 */
|
||||
#define VGE_TXQCSR_ACT2 0x0200 /* queue 2 active indicator */
|
||||
#define VGE_TXQCSR_WAK2 0x0400 /* Wake up (poll) queue 2 */
|
||||
#define VGE_TXQCST_DEAD2 0x0800 /* queue 2 dead indicator */
|
||||
#define VGE_TXQCSR_RUN3 0x1000 /* Enable TX queue 3 */
|
||||
#define VGE_TXQCSR_ACT3 0x2000 /* queue 3 active indicator */
|
||||
#define VGE_TXQCSR_WAK3 0x4000 /* Wake up (poll) queue 3 */
|
||||
#define VGE_TXQCST_DEAD3 0x8000 /* queue 3 dead indicator */
|
||||
|
||||
/* RX descriptor queue control/status register */
|
||||
|
||||
#define VGE_RXQCSR_RUN 0x0001 /* Enable RX queue */
|
||||
#define VGE_RXQCSR_ACT 0x0002 /* queue active indicator */
|
||||
#define VGE_RXQCSR_WAK 0x0004 /* Wake up (poll) queue */
|
||||
#define VGE_RXQCSR_DEAD 0x0008 /* queue dead indicator */
|
||||
|
||||
/* RX/TX queue empty interrupt delay timer register */
|
||||
|
||||
#define VGE_QTIMER_PENDCNT 0x3F
|
||||
#define VGE_QTIMER_RESOLUTION 0xC0
|
||||
|
||||
#define VGE_QTIMER_RES_1US 0x00
|
||||
#define VGE_QTIMER_RES_4US 0x40
|
||||
#define VGE_QTIMER_RES_16US 0x80
|
||||
#define VGE_QTIMER_RES_64US 0xC0
|
||||
|
||||
/* CAM address register */
|
||||
|
||||
#define VGE_CAMADDR_ADDR 0x3F /* CAM address to program */
|
||||
#define VGE_CAMADDR_AVSEL 0x40 /* 0 = address cam, 1 = VLAN cam */
|
||||
#define VGE_CAMADDR_ENABLE 0x80 /* enable CAM read/write */
|
||||
|
||||
#define VGE_CAM_MAXADDRS 64
|
||||
|
||||
/*
|
||||
* CAM command register
|
||||
* Note that the page select bits in this register affect three
|
||||
* different things:
|
||||
* - The behavior of the MAR0/MAR1 registers at offset 0x10 (the
|
||||
* page select bits control whether the MAR0/MAR1 registers affect
|
||||
* the multicast hash filter or the CAM table)
|
||||
* - The behavior of the interrupt holdoff timer register at offset
|
||||
* 0x20 (the page select bits allow you to set the interrupt
|
||||
* holdoff timer, the TX interrupt supression count or the
|
||||
* RX interrupt supression count)
|
||||
* - The behavior the WOL pattern programming registers at offset
|
||||
* 0xC0 (controls which pattern is set)
|
||||
*/
|
||||
|
||||
|
||||
#define VGE_CAMCTL_WRITE 0x04 /* CAM write command */
|
||||
#define VGE_CAMCTL_READ 0x08 /* CAM read command */
|
||||
#define VGE_CAMCTL_INTPKT_SIZ 0x10 /* select interesting pkt CAM size */
|
||||
#define VGE_CAMCTL_INTPKT_ENB 0x20 /* enable interesting packet mode */
|
||||
#define VGE_CAMCTL_PAGESEL 0xC0 /* page select */
|
||||
|
||||
#define VGE_PAGESEL_MAR 0x00
|
||||
#define VGE_PAGESEL_CAMMASK 0x40
|
||||
#define VGE_PAGESEL_CAMDATA 0x80
|
||||
|
||||
#define VGE_PAGESEL_INTHLDOFF 0x00
|
||||
#define VGE_PAGESEL_TXSUPPTHR 0x40
|
||||
#define VGE_PAGESEL_RXSUPPTHR 0x80
|
||||
|
||||
#define VGE_PAGESEL_WOLPAT0 0x00
|
||||
#define VGE_PAGESEL_WOLPAT1 0x40
|
||||
|
||||
/* MII port config register */
|
||||
|
||||
#define VGE_MIICFG_PHYADDR 0x1F /* PHY address (internal PHY is 1) */
|
||||
#define VGE_MIICFG_MDCSPEED 0x20 /* MDC accelerate x 4 */
|
||||
#define VGE_MIICFG_POLLINT 0xC0 /* polling interval */
|
||||
|
||||
#define VGE_MIIPOLLINT_1024 0x00
|
||||
#define VGE_MIIPOLLINT_512 0x40
|
||||
#define VGE_MIIPOLLINT_128 0x80
|
||||
#define VGE_MIIPOLLINT_64 0xC0
|
||||
|
||||
/* MII port status register */
|
||||
|
||||
#define VGE_MIISTS_IIDL 0x80 /* not at sofrware/timer poll cycle */
|
||||
|
||||
/* PHY status register */
|
||||
|
||||
#define VGE_PHYSTS_TXFLOWCAP 0x01 /* resolved TX flow control cap */
|
||||
#define VGE_PHYSTS_RXFLOWCAP 0x02 /* resolved RX flow control cap */
|
||||
#define VGE_PHYSTS_SPEED10 0x04 /* PHY in 10Mbps mode */
|
||||
#define VGE_PHYSTS_SPEED1000 0x08 /* PHY in giga mode */
|
||||
#define VGE_PHYSTS_FDX 0x10 /* PHY in full duplex mode */
|
||||
#define VGE_PHYSTS_LINK 0x40 /* link status */
|
||||
#define VGE_PHYSTS_RESETSTS 0x80 /* reset status */
|
||||
|
||||
/* MII management command register */
|
||||
|
||||
#define VGE_MIICMD_MDC 0x01 /* clock pin */
|
||||
#define VGE_MIICMD_MDI 0x02 /* data in pin */
|
||||
#define VGE_MIICMD_MDO 0x04 /* data out pin */
|
||||
#define VGE_MIICMD_MOUT 0x08 /* data out pin enable */
|
||||
#define VGE_MIICMD_MDP 0x10 /* enable direct programming mode */
|
||||
#define VGE_MIICMD_WCMD 0x20 /* embedded mode write */
|
||||
#define VGE_MIICMD_RCMD 0x40 /* embadded mode read */
|
||||
#define VGE_MIICMD_MAUTO 0x80 /* enable autopolling */
|
||||
|
||||
/* MII address register */
|
||||
|
||||
#define VGE_MIIADDR_SWMPL 0x80 /* initiate priority resolution */
|
||||
|
||||
/* Chip config register A */
|
||||
|
||||
#define VGE_CHIPCFG0_PACPI 0x01 /* pre-ACPI wakeup function */
|
||||
#define VGE_CHIPCFG0_ABSHDN 0x02 /* abnormal shutdown function */
|
||||
#define VGE_CHIPCFG0_GPIO1PD 0x04 /* GPIO pin enable */
|
||||
#define VGE_CHIPCFG0_SKIPTAG 0x08 /* omit 802.1p tag from CRC calc */
|
||||
#define VGE_CHIPCFG0_PHLED 0x30 /* phy LED select */
|
||||
|
||||
/* Chip config register B */
|
||||
/* Note: some of these bits are not documented in the manual! */
|
||||
|
||||
#define VGE_CHIPCFG1_BAKOPT 0x01
|
||||
#define VGE_CHIPCFG1_MBA 0x02
|
||||
#define VGE_CHIPCFG1_CAP 0x04
|
||||
#define VGE_CHIPCFG1_CRANDOM 0x08
|
||||
#define VGE_CHIPCFG1_OFSET 0x10
|
||||
#define VGE_CHIPCFG1_SLOTTIME 0x20 /* slot time 512/500 in giga mode */
|
||||
#define VGE_CHIPCFG1_MIIOPT 0x40
|
||||
#define VGE_CHIPCFG1_GTCKOPT 0x80
|
||||
|
||||
/* Chip config register C */
|
||||
|
||||
#define VGE_CHIPCFG2_EELOAD 0x80 /* enable EEPROM programming */
|
||||
|
||||
/* Chip config register D */
|
||||
|
||||
#define VGE_CHIPCFG3_64BIT_DAC 0x20 /* enable 64bit via DAC */
|
||||
#define VGE_CHIPCFG3_IODISABLE 0x80 /* disable I/O access mode */
|
||||
|
||||
/* DMA config register 0 */
|
||||
|
||||
#define VGE_DMACFG0_BURSTLEN 0x07 /* RX/TX DMA burst (in dwords) */
|
||||
|
||||
#define VGE_DMABURST_8 0x00
|
||||
#define VGE_DMABURST_16 0x01
|
||||
#define VGE_DMABURST_32 0x02
|
||||
#define VGE_DMABURST_64 0x03
|
||||
#define VGE_DMABURST_128 0x04
|
||||
#define VGE_DMABURST_256 0x05
|
||||
#define VGE_DMABURST_STRFWD 0x07
|
||||
|
||||
/* DMA config register 1 */
|
||||
|
||||
#define VGE_DMACFG1_LATENB 0x01 /* Latency timer enable */
|
||||
#define VGE_DMACFG1_MWWAIT 0x02 /* insert wait on master write */
|
||||
#define VGE_DMACFG1_MRWAIT 0x04 /* insert wait on master read */
|
||||
#define VGE_DMACFG1_MRM 0x08 /* use memory read multiple */
|
||||
#define VGE_DMACFG1_PERR_DIS 0x10 /* disable parity error checking */
|
||||
#define VGE_DMACFG1_XMRL 0x20 /* disable memory read line support */
|
||||
|
||||
/* RX MAC config register */
|
||||
|
||||
#define VGE_RXCFG_VLANFILT 0x01 /* filter VLAN ID mismatches */
|
||||
#define VGE_RXCFG_VTAGOPT 0x06 /* VLAN tag handling */
|
||||
#define VGE_RXCFG_FIFO_LOWAT 0x08 /* RX FIFO low watermark (7QW/15QW) */
|
||||
#define VGE_RXCFG_FIFO_THR 0x30 /* RX FIFO threshold */
|
||||
#define VGE_RXCFG_ARB_PRIO 0x80 /* arbitration priority */
|
||||
|
||||
#define VGE_VTAG_OPT0 0x00 /* TX: no tag insertion
|
||||
RX: rx all, no tag extraction */
|
||||
|
||||
#define VGE_VTAG_OPT1 0x02 /* TX: no tag insertion
|
||||
RX: rx only tagged pkts, no
|
||||
extraction */
|
||||
|
||||
#define VGE_VTAG_OPT2 0x04 /* TX: perform tag insertion,
|
||||
RX: rx all, extract tags */
|
||||
|
||||
#define VGE_VTAG_OPT3 0x06 /* TX: perform tag insertion,
|
||||
RX: rx only tagged pkts,
|
||||
with extraction */
|
||||
|
||||
#define VGE_RXFIFOTHR_128BYTES 0x00
|
||||
#define VGE_RXFIFOTHR_512BYTES 0x10
|
||||
#define VGE_RXFIFOTHR_1024BYTES 0x20
|
||||
#define VGE_RXFIFOTHR_STRNFWD 0x30
|
||||
|
||||
/* TX MAC config register */
|
||||
|
||||
#define VGE_TXCFG_SNAPOPT 0x01 /* 1 == insert VLAN tag at
|
||||
13th byte
|
||||
0 == insert VLANM tag after
|
||||
SNAP header (21st byte) */
|
||||
#define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */
|
||||
#define VGE_TXCFG_NONBLK_THR 0x0C /* non-blocking threshold */
|
||||
#define VGE_TXCFG_ARB_PRIO 0x80 /* arbitration priority */
|
||||
|
||||
#define VGE_TXBLOCK_64PKTS 0x00
|
||||
#define VGE_TXBLOCK_32PKTS 0x04
|
||||
#define VGE_TXBLOCK_128PKTS 0x08
|
||||
#define VGE_TXBLOCK_8PKTS 0x0C
|
||||
|
||||
/* EEPROM control/status register */
|
||||
|
||||
#define VGE_EECSR_EDO 0x01 /* data out pin */
|
||||
#define VGE_EECSR_EDI 0x02 /* data in pin */
|
||||
#define VGE_EECSR_ECK 0x04 /* clock pin */
|
||||
#define VGE_EECSR_ECS 0x08 /* chip select pin */
|
||||
#define VGE_EECSR_DPM 0x10 /* direct program mode enable */
|
||||
#define VGE_EECSR_RELOAD 0x20 /* trigger reload from EEPROM */
|
||||
#define VGE_EECSR_EMBP 0x40 /* embedded program mode enable */
|
||||
|
||||
/* EEPROM embedded command register */
|
||||
|
||||
#define VGE_EECMD_ERD 0x01 /* EEPROM read command */
|
||||
#define VGE_EECMD_EWR 0x02 /* EEPROM write command */
|
||||
#define VGE_EECMD_EWEN 0x04 /* EEPROM write enable */
|
||||
#define VGE_EECMD_EWDIS 0x08 /* EEPROM write disable */
|
||||
#define VGE_EECMD_EDONE 0x80 /* read/write done */
|
||||
|
||||
/* Chip operation and diagnostic control register */
|
||||
|
||||
#define VGE_DIAGCTL_PHYINT_ENB 0x01 /* Enable PHY interrupts */
|
||||
#define VGE_DIAGCTL_TIMER0_RES 0x02 /* timer0 uSec resolution */
|
||||
#define VGE_DIAGCTL_TIMER1_RES 0x04 /* timer1 uSec resolution */
|
||||
#define VGE_DIAGCTL_LPSEL_DIS 0x08 /* disable LPSEL field */
|
||||
#define VGE_DIAGCTL_MACFORCE 0x10 /* MAC side force mode */
|
||||
#define VGE_DIAGCTL_FCRSVD 0x20 /* reserved for future fiber use */
|
||||
#define VGE_DIAGCTL_FDXFORCE 0x40 /* force full duplex mode */
|
||||
#define VGE_DIAGCTL_GMII 0x80 /* force GMII mode, otherwise MII */
|
||||
|
||||
/* Location of station address in EEPROM */
|
||||
#define VGE_EE_EADDR 0
|
||||
|
||||
/* DMA descriptor structures */
|
||||
|
||||
/*
|
||||
* Each TX DMA descriptor has a control and status word, and 7
|
||||
* fragment address/length words. If a transmitted packet spans
|
||||
* more than 7 fragments, it has to be coalesced.
|
||||
*/
|
||||
|
||||
#define VGE_TX_FRAGS 7
|
||||
|
||||
struct vge_tx_frag {
|
||||
uint32_t vge_addrlo;
|
||||
uint16_t vge_addrhi;
|
||||
uint16_t vge_buflen;
|
||||
};
|
||||
|
||||
/*
|
||||
* The high bit in the buflen field of fragment #0 has special meaning.
|
||||
* Normally, the chip requires the driver to issue a TX poll command
|
||||
* for every packet that gets put in the TX DMA queue. Sometimes though,
|
||||
* the driver might want to queue up several packets at once and just
|
||||
* issue one transmit command to have all of them processed. In order
|
||||
* to obtain this behavior, the special 'queue' bit must be set.
|
||||
*/
|
||||
|
||||
#define VGE_TXDESC_Q 0x8000
|
||||
|
||||
struct vge_tx_desc {
|
||||
uint32_t vge_sts;
|
||||
uint32_t vge_ctl;
|
||||
struct vge_tx_frag vge_frag[VGE_TX_FRAGS];
|
||||
};
|
||||
|
||||
#define VGE_TDSTS_COLLCNT 0x0000000F /* TX collision count */
|
||||
#define VGE_TDSTS_COLL 0x00000010 /* collision seen */
|
||||
#define VGE_TDSTS_OWINCOLL 0x00000020 /* out of window collision */
|
||||
#define VGE_TDSTS_OWT 0x00000040 /* jumbo frame tx abort */
|
||||
#define VGE_TDSTS_EXCESSCOLL 0x00000080 /* TX aborted, excess colls */
|
||||
#define VGE_TDSTS_HBEATFAIL 0x00000100 /* heartbeat detect failed */
|
||||
#define VGE_TDSTS_CARRLOSS 0x00000200 /* carrier sense lost */
|
||||
#define VGE_TDSTS_SHUTDOWN 0x00000400 /* shutdown during TX */
|
||||
#define VGE_TDSTS_LINKFAIL 0x00001000 /* link fail during TX */
|
||||
#define VGE_TDSTS_GMII 0x00002000 /* GMII transmission */
|
||||
#define VGE_TDSTS_FDX 0x00004000 /* full duplex transmit */
|
||||
#define VGE_TDSTS_TXERR 0x00008000 /* error occurred */
|
||||
#define VGE_TDSTS_SEGSIZE 0x3FFF0000 /* TCP large send size */
|
||||
#define VGE_TDSTS_OWN 0x80000000 /* own bit */
|
||||
|
||||
#define VGE_TDCTL_VLANID 0x00000FFF /* VLAN ID */
|
||||
#define VGE_TDCTL_CFI 0x00001000 /* VLAN CFI bit */
|
||||
#define VGE_TDCTL_PRIO 0x0000E000 /* VLAN prio bits */
|
||||
#define VGE_TDCTL_NOCRC 0x00010000 /* disable CRC generation */
|
||||
#define VGE_TDCTL_JUMBO 0x00020000 /* jumbo frame */
|
||||
#define VGE_TDCTL_TCPCSUM 0x00040000 /* do TCP hw checksum */
|
||||
#define VGE_TDCTL_UDPCSUM 0x00080000 /* do UDP hw checksum */
|
||||
#define VGE_TDCTL_IPCSUM 0x00100000 /* do IP hw checksum */
|
||||
#define VGE_TDCTL_VTAG 0x00200000 /* insert VLAN tag */
|
||||
#define VGE_TDCTL_PRIO_INT 0x00400000 /* priority int request */
|
||||
#define VGE_TDCTL_TIC 0x00800000 /* transfer int request */
|
||||
#define VGE_TDCTL_TCPLSCTL 0x03000000 /* TCP large send ctl */
|
||||
#define VGE_TDCTL_FRAGCNT 0xF0000000 /* number of frags used */
|
||||
|
||||
#define VGE_TD_LS_MOF 0x00000000 /* middle of large send */
|
||||
#define VGE_TD_LS_SOF 0x01000000 /* start of large send */
|
||||
#define VGE_TD_LS_EOF 0x02000000 /* end of large send */
|
||||
#define VGE_TD_LS_NORM 0x03000000 /* normal frame */
|
||||
|
||||
/* Receive DMA descriptors have a single fragment pointer. */
|
||||
|
||||
struct vge_rx_desc {
|
||||
volatile uint32_t vge_sts;
|
||||
volatile uint32_t vge_ctl;
|
||||
volatile uint32_t vge_addrlo;
|
||||
volatile uint16_t vge_addrhi;
|
||||
volatile uint16_t vge_buflen;
|
||||
};
|
||||
|
||||
/*
|
||||
* Like the TX descriptor, the high bit in the buflen field in the
|
||||
* RX descriptor has special meaning. This bit controls whether or
|
||||
* not interrupts are generated for this descriptor.
|
||||
*/
|
||||
|
||||
#define VGE_RXDESC_I 0x8000
|
||||
|
||||
#define VGE_RDSTS_VIDM 0x00000001 /* VLAN tag filter miss */
|
||||
#define VGE_RDSTS_CRCERR 0x00000002 /* bad CRC error */
|
||||
#define VGE_RDSTS_FAERR 0x00000004 /* frame alignment error */
|
||||
#define VGE_RDSTS_CSUMERR 0x00000008 /* bad TCP/IP checksum */
|
||||
#define VGE_RDSTS_RLERR 0x00000010 /* RX length error */
|
||||
#define VGE_RDSTS_SYMERR 0x00000020 /* PCS symbol error */
|
||||
#define VGE_RDSTS_SNTAG 0x00000040 /* RX'ed tagged SNAP pkt */
|
||||
#define VGE_RDSTS_DETAG 0x00000080 /* VLAN tag extracted */
|
||||
#define VGE_RDSTS_BOUNDARY 0x00000300 /* frame boundary bits */
|
||||
#define VGE_RDSTS_VTAG 0x00000400 /* VLAN tag indicator */
|
||||
#define VGE_RDSTS_UCAST 0x00000800 /* unicast frame */
|
||||
#define VGE_RDSTS_BCAST 0x00001000 /* broadcast frame */
|
||||
#define VGE_RDSTS_MCAST 0x00002000 /* multicast frame */
|
||||
#define VGE_RDSTS_PFT 0x00004000 /* perfect filter hit */
|
||||
#define VGE_RDSTS_RXOK 0x00008000 /* frame is good. */
|
||||
#define VGE_RDSTS_BUFSIZ 0x3FFF0000 /* received frame len */
|
||||
#define VGE_RDSTS_SHUTDOWN 0x40000000 /* shutdown during RX */
|
||||
#define VGE_RDSTS_OWN 0x80000000 /* own bit. */
|
||||
|
||||
#define VGE_RXPKT_ONEFRAG 0x00000000 /* only one fragment */
|
||||
#define VGE_RXPKT_EOF 0x00000100 /* first frag in frame */
|
||||
#define VGE_RXPKT_SOF 0x00000200 /* last frag in frame */
|
||||
#define VGE_RXPKT_MOF 0x00000300 /* intermediate frag */
|
||||
|
||||
#define VGE_RDCTL_VLANID 0x0000FFFF /* VLAN ID info */
|
||||
#define VGE_RDCTL_UDPPKT 0x00010000 /* UDP packet received */
|
||||
#define VGE_RDCTL_TCPPKT 0x00020000 /* TCP packet received */
|
||||
#define VGE_RDCTL_IPPKT 0x00040000 /* IP packet received */
|
||||
#define VGE_RDCTL_UDPZERO 0x00080000 /* pkt with UDP CSUM of 0 */
|
||||
#define VGE_RDCTL_FRAG 0x00100000 /* received IP frag */
|
||||
#define VGE_RDCTL_PROTOCSUMOK 0x00200000 /* TCP/UDP checksum ok */
|
||||
#define VGE_RDCTL_IPCSUMOK 0x00400000 /* IP checksum ok */
|
||||
#define VGE_RDCTL_FILTIDX 0x3C000000 /* interesting filter idx */
|
||||
|
||||
#endif /* _IF_VGEREG_H_ */
|
||||
174
sys/dev/vge/if_vgevar.h
Normal file
174
sys/dev/vge/if_vgevar.h
Normal file
@ -0,0 +1,174 @@
|
||||
/*
|
||||
* Copyright (c) 2004
|
||||
* Bill Paul <wpaul@windriver.com>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#if !defined(__i386__)
|
||||
#define VGE_FIXUP_RX
|
||||
#endif
|
||||
|
||||
#define VGE_JUMBO_MTU 9000
|
||||
|
||||
#define VGE_IFQ_MAXLEN 64
|
||||
|
||||
#define VGE_TX_DESC_CNT 256
|
||||
#define VGE_RX_DESC_CNT 256 /* Must be a multiple of 4!! */
|
||||
#define VGE_RING_ALIGN 256
|
||||
#define VGE_RX_LIST_SZ (VGE_RX_DESC_CNT * sizeof(struct vge_rx_desc))
|
||||
#define VGE_TX_LIST_SZ (VGE_TX_DESC_CNT * sizeof(struct vge_tx_desc))
|
||||
#define VGE_TX_DESC_INC(x) (x = (x + 1) % VGE_TX_DESC_CNT)
|
||||
#define VGE_RX_DESC_INC(x) (x = (x + 1) % VGE_RX_DESC_CNT)
|
||||
#define VGE_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF)
|
||||
#define VGE_ADDR_HI(y) ((u_int64_t) (y) >> 32)
|
||||
#define VGE_BUFLEN(y) ((y) & 0x7FFF)
|
||||
#define VGE_OWN(x) (le32toh((x)->vge_sts) & VGE_RDSTS_OWN)
|
||||
#define VGE_RXBYTES(x) ((le32toh((x)->vge_sts) & \
|
||||
VGE_RDSTS_BUFSIZ) >> 16)
|
||||
#define VGE_MIN_FRAMELEN 60
|
||||
|
||||
#ifdef VGE_FIXUP_RX
|
||||
#define VGE_ETHER_ALIGN sizeof(uint32_t)
|
||||
#else
|
||||
#define VGE_ETHER_ALIGN 0
|
||||
#endif
|
||||
|
||||
struct vge_type {
|
||||
uint16_t vge_vid;
|
||||
uint16_t vge_did;
|
||||
char *vge_name;
|
||||
};
|
||||
|
||||
struct vge_softc;
|
||||
|
||||
struct vge_dmaload_arg {
|
||||
struct vge_softc *sc;
|
||||
int vge_idx;
|
||||
int vge_maxsegs;
|
||||
struct mbuf *vge_m0;
|
||||
u_int32_t vge_flags;
|
||||
};
|
||||
|
||||
struct vge_list_data {
|
||||
struct mbuf *vge_tx_mbuf[VGE_TX_DESC_CNT];
|
||||
struct mbuf *vge_rx_mbuf[VGE_RX_DESC_CNT];
|
||||
int vge_tx_prodidx;
|
||||
int vge_rx_prodidx;
|
||||
int vge_tx_considx;
|
||||
int vge_tx_free;
|
||||
bus_dmamap_t vge_tx_dmamap[VGE_TX_DESC_CNT];
|
||||
bus_dmamap_t vge_rx_dmamap[VGE_RX_DESC_CNT];
|
||||
bus_dma_tag_t vge_mtag; /* mbuf mapping tag */
|
||||
bus_dma_tag_t vge_rx_list_tag;
|
||||
bus_dmamap_t vge_rx_list_map;
|
||||
struct vge_rx_desc *vge_rx_list;
|
||||
bus_addr_t vge_rx_list_addr;
|
||||
bus_dma_tag_t vge_tx_list_tag;
|
||||
bus_dmamap_t vge_tx_list_map;
|
||||
struct vge_tx_desc *vge_tx_list;
|
||||
bus_addr_t vge_tx_list_addr;
|
||||
};
|
||||
|
||||
struct vge_softc {
|
||||
struct arpcom arpcom; /* interface info */
|
||||
device_t vge_dev;
|
||||
bus_space_handle_t vge_bhandle; /* bus space handle */
|
||||
bus_space_tag_t vge_btag; /* bus space tag */
|
||||
struct resource *vge_res;
|
||||
struct resource *vge_irq;
|
||||
void *vge_intrhand;
|
||||
device_t vge_miibus;
|
||||
bus_dma_tag_t vge_parent_tag;
|
||||
bus_dma_tag_t vge_tag;
|
||||
u_int8_t vge_unit; /* interface number */
|
||||
u_int8_t vge_type;
|
||||
int vge_if_flags;
|
||||
int vge_rx_consumed;
|
||||
int vge_link;
|
||||
int vge_camidx;
|
||||
struct task vge_txtask;
|
||||
struct mtx vge_mtx;
|
||||
struct mbuf *vge_head;
|
||||
struct mbuf *vge_tail;
|
||||
|
||||
struct vge_list_data vge_ldata;
|
||||
|
||||
int suspended; /* 0 = normal 1 = suspended */
|
||||
#ifdef DEVICE_POLLING
|
||||
int rxcycles;
|
||||
#endif
|
||||
|
||||
u_int32_t saved_maps[5]; /* pci data */
|
||||
u_int32_t saved_biosaddr;
|
||||
u_int8_t saved_intline;
|
||||
u_int8_t saved_cachelnsz;
|
||||
u_int8_t saved_lattimer;
|
||||
};
|
||||
|
||||
#define VGE_LOCK(_sc) mtx_lock(&(_sc)->vge_mtx)
|
||||
#define VGE_UNLOCK(_sc) mtx_unlock(&(_sc)->vge_mtx)
|
||||
#define VGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vge_mtx, MA_OWNED)
|
||||
|
||||
/*
|
||||
* register space access macros
|
||||
*/
|
||||
#define CSR_WRITE_STREAM_4(sc, reg, val) \
|
||||
bus_space_write_stream_4(sc->vge_btag, sc->vge_bhandle, reg, val)
|
||||
#define CSR_WRITE_4(sc, reg, val) \
|
||||
bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val)
|
||||
#define CSR_WRITE_2(sc, reg, val) \
|
||||
bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val)
|
||||
#define CSR_WRITE_1(sc, reg, val) \
|
||||
bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val)
|
||||
|
||||
#define CSR_READ_4(sc, reg) \
|
||||
bus_space_read_4(sc->vge_btag, sc->vge_bhandle, reg)
|
||||
#define CSR_READ_2(sc, reg) \
|
||||
bus_space_read_2(sc->vge_btag, sc->vge_bhandle, reg)
|
||||
#define CSR_READ_1(sc, reg) \
|
||||
bus_space_read_1(sc->vge_btag, sc->vge_bhandle, reg)
|
||||
|
||||
#define CSR_SETBIT_1(sc, reg, x) \
|
||||
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
|
||||
#define CSR_SETBIT_2(sc, reg, x) \
|
||||
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
|
||||
#define CSR_SETBIT_4(sc, reg, x) \
|
||||
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
|
||||
|
||||
#define CSR_CLRBIT_1(sc, reg, x) \
|
||||
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
|
||||
#define CSR_CLRBIT_2(sc, reg, x) \
|
||||
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
|
||||
#define CSR_CLRBIT_4(sc, reg, x) \
|
||||
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
|
||||
|
||||
#define VGE_TIMEOUT 10000
|
||||
|
||||
@ -203,6 +203,8 @@ device bfe # Broadcom BCM440x 10/100 Ethernet
|
||||
device bge # Broadcom BCM570xx Gigabit Ethernet
|
||||
device dc # DEC/Intel 21143 and various workalikes
|
||||
device fxp # Intel EtherExpress PRO/100B (82557, 82558)
|
||||
device lge # Level 1 LXT1001 gigabit ethernet
|
||||
device nge # NatSemi DP83820 gigabit ethernet
|
||||
device pcn # AMD Am79C97x PCI 10/100 (precedence over 'lnc')
|
||||
device re # RealTek 8139C+/8169/8169S/8110S
|
||||
device rl # RealTek 8129/8139
|
||||
@ -213,6 +215,7 @@ device ste # Sundance ST201 (D-Link DFE-550TX)
|
||||
device ti # Alteon Networks Tigon I/II gigabit Ethernet
|
||||
device tl # Texas Instruments ThunderLAN
|
||||
device tx # SMC EtherPower II (83c170 ``EPIC'')
|
||||
device vge # VIA VT612x gigabit ethernet
|
||||
device vr # VIA Rhine, Rhine II
|
||||
device wb # Winbond W89C840F
|
||||
device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
|
||||
|
||||
@ -240,6 +240,7 @@ SUBDIR= ${_3dfx} \
|
||||
uvisor \
|
||||
uvscom \
|
||||
${_vesa} \
|
||||
vge \
|
||||
vinum \
|
||||
vpo \
|
||||
vr \
|
||||
|
||||
8
sys/modules/vge/Makefile
Normal file
8
sys/modules/vge/Makefile
Normal file
@ -0,0 +1,8 @@
|
||||
# $FreeBSD$
|
||||
|
||||
.PATH: ${.CURDIR}/../../dev/vge
|
||||
|
||||
KMOD= if_vge
|
||||
SRCS= if_vge.c miibus_if.h opt_bdg.h device_if.h bus_if.h pci_if.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
@ -186,6 +186,8 @@ device bfe # Broadcom BCM440x 10/100 Ethernet
|
||||
device bge # Broadcom BCM570xx Gigabit Ethernet
|
||||
device dc # DEC/Intel 21143 and various workalikes
|
||||
device fxp # Intel EtherExpress PRO/100B (82557, 82558)
|
||||
device lge # Level 1 LXT1001 gigabit ethernet
|
||||
device nge # NatSemi DP83820 gigabit ethernet
|
||||
device pcn # AMD Am79C97x PCI 10/100 (precedence over 'lnc')
|
||||
device re # RealTek 8139C+/8169/8169S/8110S
|
||||
device rl # RealTek 8129/8139
|
||||
@ -196,6 +198,7 @@ device ste # Sundance ST201 (D-Link DFE-550TX)
|
||||
device ti # Alteon Networks Tigon I/II gigabit Ethernet
|
||||
device tl # Texas Instruments ThunderLAN
|
||||
device tx # SMC EtherPower II (83c170 ``EPIC'')
|
||||
device vge # VIA VT612x gigabit ethernet
|
||||
device vr # VIA Rhine, Rhine II
|
||||
device wb # Winbond W89C840F
|
||||
device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
|
||||
|
||||
@ -125,6 +125,7 @@ static struct _devname {
|
||||
{ DEVICE_TYPE_NETWORK, "txp", "3Com 3cR990 ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "ti", "Alteon Networks PCI gigabit ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "tl", "Texas Instruments ThunderLAN PCI ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "vge", "VIA VT612x PCI gigabit ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "vr", "VIA VT3043/VT86C100A Rhine PCI ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "vlan", "IEEE 802.1Q VLAN network interface" },
|
||||
{ DEVICE_TYPE_NETWORK, "vx", "3COM 3c590 / 3c595 ethernet card" },
|
||||
|
||||
@ -125,6 +125,7 @@ static struct _devname {
|
||||
{ DEVICE_TYPE_NETWORK, "txp", "3Com 3cR990 ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "ti", "Alteon Networks PCI gigabit ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "tl", "Texas Instruments ThunderLAN PCI ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "vge", "VIA VT612x PCI gigabit ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "vr", "VIA VT3043/VT86C100A Rhine PCI ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "vlan", "IEEE 802.1Q VLAN network interface" },
|
||||
{ DEVICE_TYPE_NETWORK, "vx", "3COM 3c590 / 3c595 ethernet card" },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user