ARM64 disassembler: support for LDR instructions
Implemented disassembly for a whole bunch of
various ldr instructions.
Obtained from: Semihalf
Sponsored by: Cavium
Approved by: cognet (mentor)
Reviewed by: zbb
Differential revision: https://reviews.freebsd.org/D5217
This commit is contained in:
wma
parent
826ad6942a
commit
a33f5ef2d9
@ -38,6 +38,16 @@ __FBSDID("$FreeBSD$");
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#define ARM64_MAX_TOKEN_LEN 8
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#define ARM64_MAX_TOKEN_CNT 10
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#define ARM_INSN_SIZE_OFFSET 30
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#define ARM_INSN_SIZE_MASK 0x3
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/* Special options for instruction printing */
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#define OP_SIGN_EXT (1UL << 0) /* Sign-extend immediate value */
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#define OP_LITERAL (1UL << 1) /* Use literal (memory offset) */
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#define OP_MULT_4 (1UL << 2) /* Multiply immediate by 4 */
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#define OP_SF32 (1UL << 3) /* Force 32-bit access */
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#define OP_SF_INV (1UL << 6) /* SF is inverted (1 means 32 bit access) */
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static const char *w_reg[] = {
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"w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
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"w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
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@ -74,6 +84,10 @@ struct arm64_insn_token {
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enum arm64_format_type {
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TYPE_01, /* OP <RD>, <RN>, <RM>{, <shift [LSL, LSR, ASR]> #<imm>} SF32/64
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OP <RD>, <RN>, #<imm>{, <shift [0, 12]>} SF32/64 */
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TYPE_02, /* OP <RT>, [<RN>, #<imm>]{!}] SF32/64
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OP <RT>, [<RN>], #<imm>{!} SF32/64
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OP <RT>, <RN>, <RM> {, EXTEND AMOUNT } */
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TYPE_03, /* OP <RT>, #imm SF32/64 */
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};
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/*
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@ -112,12 +126,57 @@ struct arm64_insn {
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* SHIFT - type of shift (instruction dependent)
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* IMM - immediate value
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* Rx - register number
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* OPTION - command specific options
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* SCALE - scaling of immediate value
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*/
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static struct arm64_insn arm64_i[] = {
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{ "add", "SF(1)|0001011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", TYPE_01, 0 },
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{ "mov", "SF(1)|001000100000000000000|RN(5)|RD(5)", TYPE_01, 0 },
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{ "add", "SF(1)|0010001|SHIFT(2)|IMM(12)|RN(5)|RD(5)", TYPE_01, 0 },
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{ NULL, NULL }
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{ "add", "SF(1)|0001011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)",
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TYPE_01, 0 },
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{ "mov", "SF(1)|001000100000000000000|RN(5)|RD(5)",
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TYPE_01, 0 },
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{ "add", "SF(1)|0010001|SHIFT(2)|IMM(12)|RN(5)|RD(5)",
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TYPE_01, 0 },
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{ "ldr", "1|SF(1)|111000010|IMM(9)|OPTION(2)|RN(5)|RT(5)",
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TYPE_02, OP_SIGN_EXT }, /* ldr immediate post/pre index */
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{ "ldr", "1|SF(1)|11100101|IMM(12)|RN(5)|RT(5)",
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TYPE_02, 0 }, /* ldr immediate unsigned */
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{ "ldr", "1|SF(1)|111000011|RM(5)|OPTION(3)|SCALE(1)|10|RN(5)|RT(5)",
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TYPE_02, 0 }, /* ldr register */
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{ "ldr", "0|SF(1)|011000|IMM(19)|RT(5)",
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TYPE_03, OP_SIGN_EXT | OP_LITERAL | OP_MULT_4 }, /* ldr literal */
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{ "ldrb", "00|111000010|IMM(9)|OPTION(2)|RN(5)|RT(5)",
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TYPE_02, OP_SIGN_EXT | OP_SF32 }, /* ldrb immediate post/pre index */
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{ "ldrb", "00|11100101|IMM(12)|RN(5)|RT(5)",
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TYPE_02, OP_SF32 }, /* ldrb immediate unsigned */
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{ "ldrb", "00|111000011|RM(5)|OPTION(3)|SCALE(1)|10|RN(5)|RT(5)",
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TYPE_02, OP_SF32 }, /* ldrb register */
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{ "ldrh", "01|111000010|IMM(9)|OPTION(2)|RN(5)|RT(5)", TYPE_02,
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OP_SIGN_EXT | OP_SF32 }, /* ldrh immediate post/pre index */
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{ "ldrh", "01|11100101|IMM(12)|RN(5)|RT(5)",
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TYPE_02, OP_SF32 }, /* ldrh immediate unsigned */
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{ "ldrh", "01|111000011|RM(5)|OPTION(3)|SCALE(1)|10|RN(5)|RT(5)",
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TYPE_02, OP_SF32 }, /* ldrh register */
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{ "ldrsb", "001110001|SF(1)|0|IMM(9)|OPTION(2)|RN(5)|RT(5)",
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TYPE_02, OP_SIGN_EXT | OP_SF_INV }, /* ldrsb immediate post/pre index */
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{ "ldrsb", "001110011|SF(1)|IMM(12)|RN(5)|RT(5)",\
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TYPE_02, OP_SF_INV}, /* ldrsb immediate unsigned */
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{ "ldrsb", "001110001|SF(1)|1|RM(5)|OPTION(3)|SCALE(1)|10|RN(5)|RT(5)",
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TYPE_02, OP_SF_INV }, /* ldrsb register */
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{ "ldrsh", "011110001|SF(1)|0|IMM(9)|OPTION(2)|RN(5)|RT(5)",
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TYPE_02, OP_SIGN_EXT | OP_SF_INV }, /* ldrsh immediate post/pre index */
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{ "ldrsh", "011110011|SF(1)|IMM(12)|RN(5)|RT(5)",
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TYPE_02, OP_SF_INV}, /* ldrsh immediate unsigned */
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{ "ldrsh", "011110001|SF(1)|1|RM(5)|OPTION(3)|SCALE(1)|10|RN(5)|RT(5)",
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TYPE_02, OP_SF_INV }, /* ldrsh register */
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{ "ldrsw", "10111000100|IMM(9)|OPTION(2)|RN(5)|RT(5)",
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TYPE_02, OP_SIGN_EXT }, /* ldrsw immediate post/pre index */
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{ "ldrsw", "1011100110|IMM(12)|RN(5)|RT(5)",
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TYPE_02, 0 }, /* ldrsw immediate unsigned */
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{ "ldrsw", "10111000101|RM(5)|OPTION(3)|SCALE(1)|10|RN(5)|RT(5)",
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TYPE_02, 0 }, /* ldrsw register */
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{ "ldrsw", "10011000|IMM(19)|RT(5)",
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TYPE_03, OP_SIGN_EXT | OP_LITERAL | OP_MULT_4 }, /* ldr literal */
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{ NULL, NULL }
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};
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static void
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@ -240,6 +299,29 @@ arm64_disasm_read_token(struct arm64_insn *insn, u_int opcode,
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return (EINVAL);
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}
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static int
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arm64_disasm_read_token_sign_ext(struct arm64_insn *insn, u_int opcode,
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const char *token, int *val)
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{
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int i;
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int msk;
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for (i = 0; i < ARM64_MAX_TOKEN_CNT; i++) {
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if (strcmp(insn->tokens[i].name, token) == 0) {
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msk = (1 << insn->tokens[i].len) - 1;
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*val = ((opcode >> insn->tokens[i].pos) & msk);
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/* If last bit is 1, sign-extend the value */
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if (*val & (1 << (insn->tokens[i].len - 1)))
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*val |= ~msk;
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return (0);
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}
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}
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return (EINVAL);
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}
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static const char *
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arm64_reg(int b64, int num)
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{
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@ -257,11 +339,17 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt)
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uint32_t insn;
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int matchp;
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int ret;
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int shift, rm, rd, rn, imm, sf;
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int shift, rm, rt, rd, rn, imm, sf, idx, option, scale, amount;
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int sign_ext;
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int rm_absent;
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/* Indicate if immediate should be outside or inside brackets */
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int inside;
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/* Print exclamation mark if pre-incremented */
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int pre;
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/* Initialize defaults, all are 0 except SF indicating 64bit access */
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shift = rd = rm = rn = imm = 0;
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shift = rd = rm = rn = imm = idx = option = amount = scale = 0;
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sign_ext = 0;
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sf = 1;
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matchp = 0;
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@ -278,14 +366,33 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt)
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if (matchp == 0)
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goto undefined;
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/* Global options */
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if (i_ptr->special_ops & OP_SF32)
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sf = 0;
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/* Global optional tokens */
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arm64_disasm_read_token(i_ptr, insn, "SF", &sf);
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if (i_ptr->special_ops & OP_SF_INV)
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sf = 1 - sf;
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if (arm64_disasm_read_token(i_ptr, insn, "SIGN", &sign_ext) == 0)
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sign_ext = 1 - sign_ext;
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if (i_ptr->special_ops & OP_SIGN_EXT)
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sign_ext = 1;
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if (sign_ext != 0)
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arm64_disasm_read_token_sign_ext(i_ptr, insn, "IMM", &imm);
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else
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arm64_disasm_read_token(i_ptr, insn, "IMM", &imm);
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if (i_ptr->special_ops & OP_MULT_4)
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imm <<= 2;
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/* Print opcode by type */
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switch (i_ptr->type) {
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case TYPE_01:
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/* OP <RD>, <RN>, <RM>{, <shift [LSL, LSR, ASR]> #<imm>} SF32/64
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OP <RD>, <RN>, #<imm>{, <shift [0, 12]>} SF32/64 */
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/* Mandatory tokens */
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ret = arm64_disasm_read_token(i_ptr, insn, "SF", &sf);
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ret |= arm64_disasm_read_token(i_ptr, insn, "RD", &rd);
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ret = arm64_disasm_read_token(i_ptr, insn, "RD", &rd);
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ret |= arm64_disasm_read_token(i_ptr, insn, "RN", &rn);
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if (ret != 0) {
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printf("ERROR: Missing mandatory token for op %s type %d\n",
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@ -294,7 +401,6 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt)
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}
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/* Optional tokens */
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arm64_disasm_read_token(i_ptr, insn, "IMM", &imm);
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arm64_disasm_read_token(i_ptr, insn, "SHIFT", &shift);
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rm_absent = arm64_disasm_read_token(i_ptr, insn, "RM", &rm);
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@ -312,6 +418,115 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt)
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if (shift != 0)
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di->di_printf(" LSL #12");
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}
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break;
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case TYPE_02:
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/* OP <RT>, [<RN>, #<imm>]{!}] SF32/64
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OP <RT>, [<RN>], #<imm>{!} SF32/64
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OP <RT>, <RN>, <RM> {, EXTEND AMOUNT } */
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/* Mandatory tokens */
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ret = arm64_disasm_read_token(i_ptr, insn, "RT", &rt);
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ret |= arm64_disasm_read_token(i_ptr, insn, "RN", &rn);
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if (ret != 0) {
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printf("ERROR: Missing mandatory token for op %s type %d\n",
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i_ptr->name, i_ptr->type);
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goto undefined;
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}
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/* Optional tokens */
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arm64_disasm_read_token(i_ptr, insn, "OPTION", &option);
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arm64_disasm_read_token(i_ptr, insn, "SCALE", &scale);
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rm_absent = arm64_disasm_read_token(i_ptr, insn, "RM", &rm);
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if (rm_absent) {
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/*
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* In unsigned operation, shift immediate value
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* and reset options to default.
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*/
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if (sign_ext == 0) {
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imm = imm << ((insn >> ARM_INSN_SIZE_OFFSET) &
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ARM_INSN_SIZE_MASK);
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option = 0;
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}
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switch (option) {
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case 0x0:
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pre = 0;
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inside = 1;
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break;
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case 0x1:
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pre = 0;
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inside = 0;
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break;
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case 0x2:
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default:
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pre = 1;
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inside = 1;
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break;
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}
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di->di_printf("%s\t%s, ", i_ptr->name, arm64_reg(sf, rt));
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if (inside != 0) {
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di->di_printf("[%s", arm64_reg(1, rn));
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if (imm != 0)
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di->di_printf(", #%d", imm);
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di->di_printf("]");
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} else {
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di->di_printf("[%s]", arm64_reg(1, rn));
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if (imm != 0)
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di->di_printf(", #%d", imm);
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}
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if (pre != 0)
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di->di_printf("!");
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} else {
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/* Last bit of option field determines 32/64 bit offset */
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di->di_printf("%s\t%s, [%s, %s", i_ptr->name,
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arm64_reg(sf, rt), arm64_reg(1, rn),
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arm64_reg(option & 1, rm));
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/* Calculate amount, it's op(31:30) */
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amount = (insn >> ARM_INSN_SIZE_OFFSET) &
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ARM_INSN_SIZE_MASK;
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switch (option) {
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case 0x2:
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di->di_printf(", uxtw #%d", amount);
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break;
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case 0x3:
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if (scale != 0)
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di->di_printf(", lsl #%d", amount);
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break;
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case 0x6:
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di->di_printf(", sxtw #%d", amount);
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break;
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case 0x7:
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di->di_printf(", sxts #%d", amount);
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break;
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default:
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di->di_printf(", RSVD");
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break;
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}
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di->di_printf("]");
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}
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break;
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case TYPE_03:
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/* OP <RT>, #imm SF32/64 */
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/* Mandatory tokens */
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ret = arm64_disasm_read_token(i_ptr, insn, "RT", &rt);
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if (ret != 0) {
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printf("ERROR: Missing mandatory token for op %s type %d\n",
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i_ptr->name, i_ptr->type);
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goto undefined;
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}
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di->di_printf("%s\t%s, ", i_ptr->name, arm64_reg(sf, rt));
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if (i_ptr->special_ops & OP_LITERAL)
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di->di_printf("0x%lx", loc + imm);
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else
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di->di_printf("#%d", imm);
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break;
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default:
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goto undefined;
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