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MFC: r266336, r270230 and r273263

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r266336:
Allow us to compile the Ti iic driver for both OMAP4 and AM335x.

r270230:
Rewrite of ti_i2c based on gonzo's patch, fix the following bugs/problems:

  . interrupt storm detected on "intr70:"; throttling interrupt source;

  . Added access serialization on iicbus_transfer(), previously there was
    no such protection and a new transfer could easily confuse the
    controller;

  . Add error checkings (i.e. stop the transfer when a error is detected
    and do _not_ overwrite the previous error);

  . On command done interrupt do not assume that the transfer was finished
    sucessfully as we will receive the command done interrupt even after
    errors;

  . Simplify the FIFO handling;

  . Reset the FIFO between the transfers as the FIFO may contain data from
    the last (failed) transfer;

  . Fix the iicbus speed for AM335x, which in turn will make better use of
    the I2C noise filter (set to one internal clock cycle);

  . Move the read and write handler to ithread instead of notifying the
    requesting thread with wakeup(9);

  . Fix the comments based on OMAP4 TRM.

The above changes allows me to read the EDID from my HDMI monitor on BBB
with gonzo's patches to support TDA19988 (which does 128 bytes reads) and
repeatedly scan the iicbus (with a modified i2c(8)) without lock up the bus.

r273263:
Fix the chan address for mtx_sleep() on bus wait.  Without this fix the
threads waiting for the bus would never wake.
This commit is contained in:
loos 2014-10-27 12:18:07 +00:00
parent 14fa4d63cd
commit a3704ff4d4
2 changed files with 583 additions and 775 deletions
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1340
sys/arm/ti/ti_i2c.c
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File diff suppressed because it is too large Load Diff

18
sys/arm/ti/ti_i2c.h
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@ -69,7 +69,12 @@
#define I2C_STAT_NACK (1UL << 1)
#define I2C_STAT_AL (1UL << 0)
#define I2C_REG_SYSS 0x90
#define I2C_SYSS_RDONE (1UL << 0)
#define I2C_REG_BUF 0x94
#define I2C_BUF_RXFIFO_CLR (1UL << 14)
#define I2C_BUF_TXFIFO_CLR (1UL << 6)
#define I2C_BUF_RXTRSH_SHIFT 8
#define I2C_BUF_TRSH_MASK 0x3f
#define I2C_REG_CNT 0x98
#define I2C_REG_DATA 0x9c
#define I2C_REG_CON 0xa4
@ -91,10 +96,17 @@
#define I2C_REG_OA0 0xa8
#define I2C_REG_SA 0xac
#define I2C_REG_PSC 0xb0
#define I2C_PSC_MASK 0xff
#define I2C_REG_SCLL 0xb4
#define I2C_SCLL_MASK 0xff
#define I2C_HSSCLL_SHIFT 8
#define I2C_REG_SCLH 0xb8
#define I2C_SCLH_MASK 0xff
#define I2C_HSSCLH_SHIFT 8
#define I2C_REG_SYSTEST 0xbc
#define I2C_REG_BUFSTAT 0xc0
#define I2C_BUFSTAT_FIFODEPTH_MASK 0x3
#define I2C_BUFSTAT_FIFODEPTH_SHIFT 14
#define I2C_REG_OA1 0xc4
#define I2C_REG_OA2 0xc8
#define I2C_REG_OA3 0xcc
@ -107,9 +119,13 @@
#define I2C_REG_REVNB_LO 0x00
#define I2C_REG_REVNB_HI 0x04
#define I2C_REG_SYSC 0x10
#define I2C_REG_SYSC_SRST (1UL << 1)
#define I2C_REG_STATUS_RAW 0x24
#define I2C_REG_STATUS 0x28
#define I2C_REG_IRQENABLE_SET 0x2C
#define I2C_REG_IRQENABLE_CLR 0x30
#define I2C_CLK 96000000UL /* 96MHz */
#define I2C_ICLK 12000000UL /* 12MHz */
#endif /* _TI_I2C_H_ */