Bug fixes found internally as detailed below:
1. While disabling interrupt the FW disables interrupts for only 16 vectors. In case of Invader which supports 96 MSI-x vectors, some spurious interrupts may come on other vectors even after interrupt disable. So, driver uses a flag and ignores the spurious interrupts. 2. Reply queue depth is made double the number of commands supported by FW. 3. Misplaced interrupt enable code is now moved down in the OCR path. 4. Updated error handling code in OCR path. 5. Removed un-necessary print. Reviewed by: ambrisko MFC after: 2 weeks Sponsored by: AVAGO Technologies
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@ -274,6 +274,7 @@ mrsas_disable_intr(struct mrsas_softc *sc)
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u_int32_t mask = 0xFFFFFFFF;
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u_int32_t status;
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sc->mask_interrupts=1;
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mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), mask);
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/* Dummy read to force pci flush */
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status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask));
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@ -285,6 +286,7 @@ mrsas_enable_intr(struct mrsas_softc *sc)
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u_int32_t mask = MFI_FUSION_ENABLE_INTERRUPT_MASK;
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u_int32_t status;
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sc->mask_interrupts=0;
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mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status), ~0);
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status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status));
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@ -1442,6 +1444,9 @@ mrsas_isr(void *arg)
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struct mrsas_softc *sc = irq_context->sc;
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int status = 0;
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if (sc->mask_interrupts)
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return;
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if (!sc->msix_vectors) {
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status = mrsas_clear_intr(sc);
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if (!status)
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@ -2154,7 +2159,7 @@ mrsas_init_adapter(struct mrsas_softc *sc)
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max_cmd = sc->max_fw_cmds;
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/* Determine allocation size of command frames */
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sc->reply_q_depth = ((max_cmd + 1 + 15) / 16 * 16);
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sc->reply_q_depth = ((max_cmd + 1 + 15) / 16 * 16) * 2;
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sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * max_cmd;
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sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth);
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sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (max_cmd + 1));
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@ -2807,9 +2812,6 @@ mrsas_reset_ctrl(struct mrsas_softc *sc)
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mrsas_dprint(sc, MRSAS_OCR, "mrsas_ioc_init() failed!\n");
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continue;
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}
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mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
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mrsas_enable_intr(sc);
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sc->adprecovery = MRSAS_HBA_OPERATIONAL;
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/* Re-fire management commands */
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for (j = 0; j < sc->max_fw_cmds; j++) {
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@ -2842,12 +2844,17 @@ mrsas_reset_ctrl(struct mrsas_softc *sc)
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if (mrsas_get_ctrl_info(sc)) {
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mrsas_kill_hba(sc);
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retval = -1;
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retval = FAIL;
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goto out;
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}
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if (!mrsas_get_map_info(sc))
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mrsas_sync_map_info(sc);
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mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
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mrsas_enable_intr(sc);
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sc->adprecovery = MRSAS_HBA_OPERATIONAL;
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/* Adapter reset completed successfully */
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device_printf(sc->mrsas_dev, "Reset successful\n");
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retval = SUCCESS;
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@ -2667,6 +2667,7 @@ struct mrsas_softc {
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int msix_vectors;
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int msix_enable;
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uint32_t msix_reg_offset[16];
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uint8_t mask_interrupts;
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struct mrsas_mpt_cmd **mpt_cmd_list;
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struct mrsas_mfi_cmd **mfi_cmd_list;
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TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head;
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@ -375,7 +375,6 @@ MR_ValidateMapInfo(struct mrsas_softc *sc)
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return 1;
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}
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if (sc->UnevenSpanSupport) {
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printf("Updating span set\n\n");
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mr_update_span_set(drv_map, ldSpanInfo);
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}
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mrsas_update_load_balance_params(sc, drv_map, sc->load_balance_info);
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