Support of Ralink Ethernet MAC, used in RT3050F/RT3052F and I belive in other Ralink SoCs.
Approved by: adrian (mentor)
This commit is contained in:
Aleksandr Rybalko
parent
7c9acc776a
commit
a4e33603b2
@ -106,4 +106,5 @@ dev/siba/siba_pcib.c optional siba pci
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dev/hwpmc/hwpmc_mips.c optional hwpmc
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dev/hwpmc/hwpmc_mips24k.c optional hwpmc
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dev/rt/if_rt.c optional rt
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dev/nvram2env/nvram2env.c optional nvram2env
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@ -70,3 +70,11 @@ OCTEON_BOARD_CAPK_0100ND opt_cvmx.h
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# Options that control the Atheros SoC peripherals
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#
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ARGE_DEBUG opt_global.h
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#
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# Options that control the Ralink RT305xF Etherenet MAC.
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#
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IF_RT_DEBUG opt_if_rt.h
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IF_RT_PHY_SUPPORT opt_if_rt.h
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IF_RT_RING_DATA_COUNT opt_if_rt.h
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2616
sys/dev/rt/if_rt.c
Normal file
2616
sys/dev/rt/if_rt.c
Normal file
File diff suppressed because it is too large
Load Diff
289
sys/dev/rt/if_rtreg.h
Normal file
289
sys/dev/rt/if_rtreg.h
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@ -0,0 +1,289 @@
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/*-
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* Copyright (c) 2009, Aleksandr Rybalko
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_RTREG_H_
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#define _IF_RTREG_H_
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#define RT_READ(sc, reg) \
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bus_space_read_4((sc)->bst, (sc)->bsh, reg)
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#define RT_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->bst, (sc)->bsh, reg, val)
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#define GE_PORT_BASE 0x0000
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#define MDIO_ACCESS 0x00
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#define MDIO_CMD_ONGO (1<<31)
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#define MDIO_CMD_WR (1<<30)
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#define MDIO_PHY_ADDR_MASK 0x1f000000
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#define MDIO_PHY_ADDR_SHIFT 24
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#define MDIO_PHYREG_ADDR_MASK 0x001f0000
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#define MDIO_PHYREG_ADDR_SHIFT 16
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#define MDIO_PHY_DATA_MASK 0x0000ffff
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#define MDIO_PHY_DATA_SHIFT 0
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#define FE_GLO_CFG 0x08 /*Frame Engine Global Configuration */
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#define EXT_VLAN_TYPE_MASK 0xffff0000
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#define EXT_VLAN_TYPE_SHIFT 16
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#define EXT_VLAN_TYPE_DFLT 0x81000000
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#define US_CYC_CNT_MASK 0x0000ff00
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#define US_CYC_CNT_SHIFT 8
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#define US_CYC_CNT_DFLT (132<<8) /* sys clocks per 1uS */
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#define L2_SPACE (8<<4) /* L2 space. Unit is 8 bytes */
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#define FE_RST_GLO 0x0C /*Frame Engine Global Reset*/
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#define FC_DROP_CNT_MASK 0xffff0000 /*Flow cntrl drop count */
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#define FC_DROP_CNT_SHIFT 16
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#define PSE_RESET (1<<0)
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#define FE_INT_STATUS 0x10
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#define CNT_PPE_AF (1<<31)
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#define CNT_GDM_AF (1<<29)
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#define PSE_P2_FC (1<<26)
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#define GDM_CRC_DROP (1<<25)
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#define PSE_BUF_DROP (1<<24)
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#define GDM_OTHER_DROP (1<<23)
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#define PSE_P1_FC (1<<22)
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#define PSE_P0_FC (1<<21)
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#define PSE_FQ_EMPTY (1<<20)
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#define INT_TX_COHERENT (1<<17)
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#define INT_RX_COHERENT (1<<16)
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#define INT_TXQ3_DONE (1<<11)
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#define INT_TXQ2_DONE (1<<10)
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#define INT_TXQ1_DONE (1<<9)
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#define INT_TXQ0_DONE (1<<8)
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#define INT_RX_DONE (1<<2)
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#define TX_DLY_INT (1<<1) /* TXQ[0|1]_DONE with delay */
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#define RX_DLY_INT (1<<0) /* RX_DONE with delay */
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#define FE_INT_ENABLE 0x14
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#define MDIO_CFG2 0x18
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#define FOE_TS_T 0x1c
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#define PSE_FQ_PCNT_MASK 0xff000000
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#define PSE_FQ_PCNT_SHIFT 24
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#define FOE_TS_TIMESTAMP_MASK 0x0000ffff
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#define FOE_TS_TIMESTAMP_SHIFT 0
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#define GDMA1_BASE 0x0020
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#define GDMA2_BASE 0x0060
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#define CDMA_BASE 0x0080
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#define GDMA_FWD_CFG 0x00 /* Only GDMA */
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#define GDM_DROP_256B (1<<23)
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#define GDM_ICS_EN (1<<22)
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#define GDM_TCS_EN (1<<21)
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#define GDM_UCS_EN (1<<20)
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#define GDM_DISPAD (1<<18)
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#define GDM_DISCRC (1<<17)
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#define GDM_STRPCRC (1<<16)
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#define GDM_UFRC_P_SHIFT 12
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#define GDM_BFRC_P_SHIFT 8
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#define GDM_MFRC_P_SHIFT 4
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#define GDM_OFRC_P_SHIFT 0
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#define GDM_XFRC_P_MASK 0x07
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#define GDM_DST_PORT_CPU 0
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#define GDM_DST_PORT_GDMA1 1
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#define GDM_DST_PORT_GDMA2 2
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#define GDM_DST_PORT_PPE 6
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#define GDM_DST_PORT_DISCARD 7
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#define CDMA_CSG_CFG 0x00 /* Only CDMA */
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#define INS_VLAN_TAG (0x8100<<16)
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#define ICS_GEN_EN (1<<2)
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#define TCS_GEN_EN (1<<1)
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#define UCS_GEN_EN (1<<0)
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#define GDMA_SCH_CFG 0x04
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#define GDM1_SCH_MOD_MASK 0x03000000
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#define GDM1_SCH_MOD_SHIFT 24
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#define GDM1_SCH_MOD_WRR 0
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#define GDM1_SCH_MOD_STRICT 1
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#define GDM1_SCH_MOD_MIXED 2
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#define GDM1_WT_1 0
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#define GDM1_WT_2 1
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#define GDM1_WT_4 2
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#define GDM1_WT_8 3
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#define GDM1_WT_16 4
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#define GDM1_WT_Q3_SHIFT 12
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#define GDM1_WT_Q2_SHIFT 8
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#define GDM1_WT_Q1_SHIFT 4
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#define GDM1_WT_Q0_SHIFT 0
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#define GDMA_SHPR_CFG 0x08
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#define GDM1_SHPR_EN (1<<24)
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#define GDM1_BK_SIZE_MASK 0x00ff0000 /* Bucket size 1kB units */
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#define GDM1_BK_SIZE_SHIFT 16
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#define GDM1_TK_RATE_MASK 0x00003fff /* Shaper token rate 8B/ms units */
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#define GDM1_TK_RATE_SHIFT 0
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#define GDMA_MAC_ADRL 0x0C
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#define GDMA_MAC_ADRH 0x10
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#define PPPOE_SID_0001 0x08 /* 0..15 SID0, 15..31 SID1 */
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#define PPPOE_SID_0203 0x0c
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#define PPPOE_SID_0405 0x10
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#define PPPOE_SID_0607 0x14
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#define PPPOE_SID_0809 0x18
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#define PPPOE_SID_1011 0x1c
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#define PPPOE_SID_1213 0x20
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#define PPPOE_SID_1415 0x24
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#define VLAN_ID_0001 0x28 /* 0..11 VID0, 15..26 VID1 */
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#define VLAN_ID_0203 0x2c
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#define VLAN_ID_0405 0x30
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#define VLAN_ID_0607 0x34
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#define VLAN_ID_0809 0x38
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#define VLAN_ID_1011 0x3c
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#define VLAN_ID_1213 0x40
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#define VLAN_ID_1415 0x44
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#define PSE_BASE 0x0040
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#define PSE_FQFC_CFG 0x00
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#define FQ_MAX_PCNT_MASK 0xff000000
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#define FQ_MAX_PCNT_SHIFT 24
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#define FQ_FC_RLS_MASK 0x00ff0000
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#define FQ_FC_RLS_SHIFT 16
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#define FQ_FC_ASRT_MASK 0x0000ff00
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#define FQ_FC_ASRT_SHIFT 8
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#define FQ_FC_DROP_MASK 0x000000ff
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#define FQ_FC_DROP_SHIFT 0
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#define CDMA_FC_CFG 0x04
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#define GDMA1_FC_CFG 0x08
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#define GDMA2_FC_CFG 0x0C
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#define P_SHARING (1<<28)
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#define P_HQ_DEF_MASK 0x0f000000
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#define P_HQ_DEF_SHIFT 24
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#define P_HQ_RESV_MASK 0x00ff0000
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#define P_HQ_RESV_SHIFT 16
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#define P_LQ_RESV_MASK 0x0000ff00
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#define P_LQ_RESV_SHIFT 8
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#define P_IQ_ASRT_MASK 0x000000ff
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#define P_IQ_ASRT_SHIFT 0
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#define CDMA_OQ_STA 0x10
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#define GDMA1_OQ_STA 0x14
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#define GDMA2_OQ_STA 0x18
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#define P_OQ3_PCNT_MASK 0xff000000
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#define P_OQ3_PCNT_SHIFT 24
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#define P_OQ2_PCNT_MASK 0x00ff0000
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#define P_OQ2_PCNT_SHIFT 16
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#define P_OQ1_PCNT_MASK 0x0000ff00
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#define P_OQ1_PCNT_SHIFT 8
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#define P_OQ0_PCNT_MASK 0x000000ff
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#define P_OQ0_PCNT_SHIFT 0
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#define PSE_IQ_STA 0x1C
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#define P6_OQ0_PCNT_MASK 0xff000000
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#define P6_OQ0_PCNT_SHIFT 24
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#define P2_IQ_PCNT_MASK 0x00ff0000
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#define P2_IQ_PCNT_SHIFT 16
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#define P1_IQ_PCNT_MASK 0x0000ff00
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#define P1_IQ_PCNT_SHIFT 8
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#define P0_IQ_PCNT_MASK 0x000000ff
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#define P0_IQ_PCNT_SHIFT 0
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#define PDMA_BASE 0x0100
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#define PDMA_GLO_CFG 0x00
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#define FE_TX_WB_DDONE (1<<6)
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#define FE_DMA_BT_SIZE4 (0<<4)
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#define FE_DMA_BT_SIZE8 (1<<4)
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#define FE_DMA_BT_SIZE16 (2<<4)
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#define FE_RX_DMA_BUSY (1<<3)
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#define FE_RX_DMA_EN (1<<2)
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#define FE_TX_DMA_BUSY (1<<1)
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#define FE_TX_DMA_EN (1<<0)
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#define PDMA_RST_IDX 0x04
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#define FE_RST_DRX_IDX0 (1<<16)
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#define FE_RST_DTX_IDX3 (1<<3)
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#define FE_RST_DTX_IDX2 (1<<2)
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#define FE_RST_DTX_IDX1 (1<<1)
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#define FE_RST_DTX_IDX0 (1<<0)
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#define PDMA_SCH_CFG 0x08
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#define DELAY_INT_CFG 0x0C
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#define TXDLY_INT_EN (1<<31)
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#define TXMAX_PINT_SHIFT 24
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#define TXMAX_PTIME_SHIFT 16
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#define RXDLY_INT_EN (1<<15)
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#define RXMAX_PINT_SHIFT 8
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#define RXMAX_PTIME_SHIFT 0
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#define TX_BASE_PTR0 0x10
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#define TX_MAX_CNT0 0x14
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#define TX_CTX_IDX0 0x18
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#define TX_DTX_IDX0 0x1C
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#define TX_BASE_PTR1 0x20
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#define TX_MAX_CNT1 0x24
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#define TX_CTX_IDX1 0x28
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#define TX_DTX_IDX1 0x2C
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#define RX_BASE_PTR0 0x30
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#define RX_MAX_CNT0 0x34
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#define RX_CALC_IDX0 0x38
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#define RX_DRX_IDX0 0x3C
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#define TX_BASE_PTR2 0x40
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#define TX_MAX_CNT2 0x44
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#define TX_CTX_IDX2 0x48
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#define TX_DTX_IDX2 0x4C
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#define TX_BASE_PTR3 0x50
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#define TX_MAX_CNT3 0x54
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#define TX_CTX_IDX3 0x58
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#define TX_DTX_IDX3 0x5C
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#define TX_BASE_PTR(qid) (((qid>1)?(0x20):(0x10)) + (qid) * 16)
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#define TX_MAX_CNT(qid) (((qid>1)?(0x24):(0x14)) + (qid) * 16)
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#define TX_CTX_IDX(qid) (((qid>1)?(0x28):(0x18)) + (qid) * 16)
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#define TX_DTX_IDX(qid) (((qid>1)?(0x2c):(0x1c)) + (qid) * 16)
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#define PPE_BASE 0x0200
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#define CNTR_BASE 0x0400
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#define PPE_AC_BCNT0 0x000
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#define PPE_AC_PCNT0 0x004
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#define PPE_AC_BCNT63 0x1F8
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#define PPE_AC_PCNT63 0x1FC
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#define PPE_MTR_CNT0 0x200
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#define PPE_MTR_CNT63 0x2FC
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#define GDMA_TX_GBCNT0 0x300
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#define GDMA_TX_GPCNT0 0x304
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#define GDMA_TX_SKIPCNT0 0x308
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#define GDMA_TX_COLCNT0 0x30C
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#define GDMA_RX_GBCNT0 0x320
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#define GDMA_RX_GPCNT0 0x324
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#define GDMA_RX_OERCNT0 0x328
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#define GDMA_RX_FERCNT0 0x32C
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#define GDMA_RX_SHORT_ERCNT0 0x330
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#define GDMA_RX_LONG_ERCNT0 0x334
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#define GDMA_RX_CSUM_ERCNT0 0x338
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#define POLICYTABLE_BASE 0x1000
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#endif /* _IF_RTREG_H_ */
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282
sys/dev/rt/if_rtvar.h
Normal file
282
sys/dev/rt/if_rtvar.h
Normal file
@ -0,0 +1,282 @@
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/*-
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* Copyright (c) 2010-2011 Aleksandr Rybalko <ray@ddteam.net>
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* Copyright (c) 2009-2010 Alexander Egorenkov <egorenar@gmail.com>
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* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
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#ifndef _IF_RTVAR_H_
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#define _IF_RTVAR_H_
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#include <sys/param.h>
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#include <sys/sysctl.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/taskqueue.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <net/bpf.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include "opt_if_rt.h"
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#define RT_SOFTC_LOCK(sc) mtx_lock(&(sc)->lock)
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#define RT_SOFTC_UNLOCK(sc) mtx_unlock(&(sc)->lock)
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#define RT_SOFTC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED)
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#define RT_SOFTC_TX_RING_LOCK(ring) mtx_lock(&(ring)->lock)
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#define RT_SOFTC_TX_RING_UNLOCK(ring) mtx_unlock(&(ring)->lock)
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#define RT_SOFTC_TX_RING_ASSERT_LOCKED(ring) \
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mtx_assert(&(ring)->lock, MA_OWNED)
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#define RT_SOFTC_TX_RING_COUNT 4
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#ifndef IF_RT_RING_DATA_COUNT
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#define IF_RT_RING_DATA_COUNT 128
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#endif
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#define RT_SOFTC_RX_RING_DATA_COUNT IF_RT_RING_DATA_COUNT
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|
||||
#define RT_SOFTC_MAX_SCATTER 10
|
||||
|
||||
#define RT_SOFTC_TX_RING_DATA_COUNT (IF_RT_RING_DATA_COUNT/4)
|
||||
#define RT_SOFTC_TX_RING_DESC_COUNT \
|
||||
(RT_SOFTC_TX_RING_DATA_COUNT * RT_SOFTC_MAX_SCATTER)
|
||||
|
||||
#define RT_TXDESC_SDL1_BURST (1 << 15)
|
||||
#define RT_TXDESC_SDL1_LASTSEG (1 << 14)
|
||||
#define RT_TXDESC_SDL0_DDONE (1 << 15)
|
||||
#define RT_TXDESC_SDL0_LASTSEG (1 << 14)
|
||||
struct rt_txdesc
|
||||
{
|
||||
uint32_t sdp0;
|
||||
uint16_t sdl1;
|
||||
uint16_t sdl0;
|
||||
uint32_t sdp1;
|
||||
uint8_t vid;
|
||||
#define TXDSCR_INS_VLAN_TAG 0x80
|
||||
#define TXDSCR_VLAN_PRIO_MASK 0x70
|
||||
#define TXDSCR_VLAN_IDX_MASK 0x0f
|
||||
uint8_t pppoe;
|
||||
#define TXDSCR_USR_DEF_FLD 0x80
|
||||
#define TXDSCR_INS_PPPOE_HDR 0x10
|
||||
#define TXDSCR_PPPOE_SID_MASK 0x0f
|
||||
uint8_t qn;
|
||||
#define TXDSCR_QUEUE_MASK 0x07
|
||||
uint8_t dst;
|
||||
#define TXDSCR_IP_CSUM_GEN 0x80
|
||||
#define TXDSCR_UDP_CSUM_GEN 0x40
|
||||
#define TXDSCR_TCP_CSUM_GEN 0x20
|
||||
#define TXDSCR_DST_PORT_MASK 0x07
|
||||
#define TXDSCR_DST_PORT_CPU 0x00
|
||||
#define TXDSCR_DST_PORT_GDMA1 0x01
|
||||
#define TXDSCR_DST_PORT_GDMA2 0x02
|
||||
#define TXDSCR_DST_PORT_PPE 0x06
|
||||
#define TXDSCR_DST_PORT_DISC 0x07
|
||||
} __packed;
|
||||
|
||||
#define RT_RXDESC_SDL0_DDONE (1 << 15)
|
||||
struct rt_rxdesc
|
||||
{
|
||||
uint32_t sdp0;
|
||||
uint16_t sdl1;
|
||||
uint16_t sdl0;
|
||||
uint32_t sdp1;
|
||||
uint16_t foe;
|
||||
#define RXDSXR_FOE_ENTRY_VALID 0x40
|
||||
#define RXDSXR_FOE_ENTRY_MASK 0x3f
|
||||
uint8_t ai;
|
||||
#define RXDSXR_AI_COU_REASON 0xff
|
||||
#define RXDSXR_AI_PARSER_RSLT_MASK 0xff
|
||||
uint8_t src;
|
||||
#define RXDSXR_SRC_IPFVLD 0x80
|
||||
#define RXDSXR_SRC_L4FVLD 0x40
|
||||
#define RXDSXR_SRC_IP_CSUM_FAIL 0x20
|
||||
#define RXDSXR_SRC_L4_CSUM_FAIL 0x10
|
||||
#define RXDSXR_SRC_AIS 0x08
|
||||
#define RXDSXR_SRC_PORT_MASK 0x07
|
||||
} __packed;
|
||||
|
||||
struct rt_softc_rx_data
|
||||
{
|
||||
bus_dmamap_t dma_map;
|
||||
struct mbuf *m;
|
||||
};
|
||||
|
||||
struct rt_softc_rx_ring
|
||||
{
|
||||
bus_dma_tag_t desc_dma_tag;
|
||||
bus_dmamap_t desc_dma_map;
|
||||
bus_addr_t desc_phys_addr;
|
||||
struct rt_rxdesc *desc;
|
||||
bus_dma_tag_t data_dma_tag;
|
||||
bus_dmamap_t spare_dma_map;
|
||||
struct rt_softc_rx_data data[RT_SOFTC_RX_RING_DATA_COUNT];
|
||||
int cur;
|
||||
};
|
||||
|
||||
struct rt_softc_tx_data
|
||||
{
|
||||
bus_dmamap_t dma_map;
|
||||
struct mbuf *m;
|
||||
};
|
||||
|
||||
struct rt_softc_tx_ring
|
||||
{
|
||||
struct mtx lock;
|
||||
bus_dma_tag_t desc_dma_tag;
|
||||
bus_dmamap_t desc_dma_map;
|
||||
bus_addr_t desc_phys_addr;
|
||||
struct rt_txdesc *desc;
|
||||
int desc_queued;
|
||||
int desc_cur;
|
||||
int desc_next;
|
||||
bus_dma_tag_t seg0_dma_tag;
|
||||
bus_dmamap_t seg0_dma_map;
|
||||
bus_addr_t seg0_phys_addr;
|
||||
uint8_t *seg0;
|
||||
bus_dma_tag_t data_dma_tag;
|
||||
struct rt_softc_tx_data data[RT_SOFTC_TX_RING_DATA_COUNT];
|
||||
int data_queued;
|
||||
int data_cur;
|
||||
int data_next;
|
||||
int qid;
|
||||
};
|
||||
|
||||
struct rt_softc
|
||||
{
|
||||
device_t dev;
|
||||
struct mtx lock;
|
||||
uint32_t flags;
|
||||
|
||||
int mem_rid;
|
||||
struct resource *mem;
|
||||
int irq_rid;
|
||||
struct resource *irq;
|
||||
void *irqh;
|
||||
|
||||
bus_space_tag_t bst;
|
||||
bus_space_handle_t bsh;
|
||||
|
||||
struct ifnet *ifp;
|
||||
int if_flags;
|
||||
struct ifmedia rt_ifmedia;
|
||||
|
||||
uint32_t mac_rev;
|
||||
uint8_t mac_addr[ETHER_ADDR_LEN];
|
||||
device_t rt_miibus;
|
||||
|
||||
uint32_t intr_enable_mask;
|
||||
uint32_t intr_disable_mask;
|
||||
uint32_t intr_pending_mask;
|
||||
|
||||
struct task rx_done_task;
|
||||
int rx_process_limit;
|
||||
struct task tx_done_task;
|
||||
struct task periodic_task;
|
||||
struct callout periodic_ch;
|
||||
unsigned long periodic_round;
|
||||
struct taskqueue *taskqueue;
|
||||
|
||||
struct rt_softc_rx_ring rx_ring;
|
||||
struct rt_softc_tx_ring tx_ring[RT_SOFTC_TX_RING_COUNT];
|
||||
int tx_ring_mgtqid;
|
||||
|
||||
struct callout tx_watchdog_ch;
|
||||
int tx_timer;
|
||||
|
||||
/* statistic counters */
|
||||
unsigned long interrupts;
|
||||
unsigned long tx_coherent_interrupts;
|
||||
unsigned long rx_coherent_interrupts;
|
||||
unsigned long rx_interrupts;
|
||||
unsigned long rx_delay_interrupts;
|
||||
unsigned long tx_interrupts[RT_SOFTC_TX_RING_COUNT];
|
||||
unsigned long tx_delay_interrupts;
|
||||
unsigned long tx_data_queue_full[RT_SOFTC_TX_RING_COUNT];
|
||||
unsigned long tx_watchdog_timeouts;
|
||||
unsigned long tx_defrag_packets;
|
||||
unsigned long no_tx_desc_avail;
|
||||
unsigned long rx_mbuf_alloc_errors;
|
||||
unsigned long rx_mbuf_dmamap_errors;
|
||||
unsigned long tx_queue_not_empty[2];
|
||||
|
||||
unsigned long rx_bytes;
|
||||
unsigned long rx_packets;
|
||||
unsigned long rx_crc_err;
|
||||
unsigned long rx_phy_err;
|
||||
unsigned long rx_dup_packets;
|
||||
unsigned long rx_fifo_overflows;
|
||||
unsigned long rx_short_err;
|
||||
unsigned long rx_long_err;
|
||||
unsigned long tx_bytes;
|
||||
unsigned long tx_packets;
|
||||
unsigned long tx_skip;
|
||||
unsigned long tx_collision;
|
||||
|
||||
int phy_addr;
|
||||
|
||||
#ifdef IF_RT_DEBUG
|
||||
int debug;
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef IF_RT_DEBUG
|
||||
enum
|
||||
{
|
||||
RT_DEBUG_RX = 0x00000001,
|
||||
RT_DEBUG_TX = 0x00000002,
|
||||
RT_DEBUG_INTR = 0x00000004,
|
||||
RT_DEBUG_STATE = 0x00000008,
|
||||
RT_DEBUG_STATS = 0x00000010,
|
||||
RT_DEBUG_PERIODIC = 0x00000020,
|
||||
RT_DEBUG_WATCHDOG = 0x00000040,
|
||||
RT_DEBUG_ANY = 0xffffffff
|
||||
};
|
||||
|
||||
#define RT_DPRINTF(sc, m, fmt, ...) \
|
||||
do { if ((sc)->debug & (m)) \
|
||||
device_printf(sc->dev, fmt, __VA_ARGS__); } while (0)
|
||||
#else
|
||||
#define RT_DPRINTF(sc, m, fmt, ...)
|
||||
#endif /* #ifdef IF_RT_DEBUG */
|
||||
|
||||
#endif /* #ifndef _IF_RTVAR_H_ */
|
||||
Loading…
Reference in New Issue
Block a user