Finish implementation of ARM PMU interrupts.
The ARM PMU may use single per-core interrupt or may use multiple generic interrupts, one per core. In this case, special attention must be paid to the correct identification of the physical location of the core, its order in the external database (FDT) and the associated cpuid. Also keep in mind that a SoC can have multiple different PMUs (usually one per cluster)
This commit is contained in:
Michal Meloun
parent
22f5cb76eb
commit
a527975133
@ -60,31 +60,17 @@ __FBSDID("$FreeBSD$");
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#ifdef notyet
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#define MAX_RLEN 8
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#else
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#define MAX_RLEN 1
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#endif
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struct pmu_softc {
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struct resource *res[MAX_RLEN];
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device_t dev;
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void *ih[MAX_RLEN];
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struct pmu_intr {
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struct resource *res;
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void *ih;
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int cpuid;
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};
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static struct resource_spec pmu_spec[] = {
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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/* We don't currently handle pmu events, other than on cpu 0 */
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#ifdef notyet
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{ SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL },
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#endif
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{ -1, 0 }
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struct pmu_softc {
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device_t dev;
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struct pmu_intr irq[MAX_RLEN];
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};
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/* CCNT */
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@ -130,6 +116,128 @@ pmu_intr(void *arg)
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return (FILTER_HANDLED);
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}
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static int
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pmu_parse_affinity(struct pmu_softc *sc, struct pmu_intr *irq, phandle_t xref,
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uint32_t mpidr)
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{
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struct pcpu *pcpu;
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int i, err;
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if (xref != 0) {
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err = OF_getencprop(OF_node_from_xref(xref), "reg", &mpidr,
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sizeof(mpidr));
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if (err < 0) {
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device_printf(sc->dev, "missing 'reg' property\n");
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return (ENXIO);
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}
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}
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for (i = 0; i < MAXCPU; i++) {
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pcpu = pcpu_find(i);
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if (pcpu != NULL && pcpu->pc_mpidr == mpidr) {
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irq->cpuid = i;
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return (0);
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}
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}
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device_printf(sc->dev, "Cannot find CPU with MPIDR: 0x%08X\n", mpidr);
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return (ENXIO);
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}
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static int
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pmu_parse_intr(struct pmu_softc *sc)
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{
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bool has_affinity;
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phandle_t node, *cpus;
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int rid, err, ncpus, i;
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node = ofw_bus_get_node(sc->dev);
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has_affinity = OF_hasprop(node, "interrupt-affinity");
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for (i = 0; i < MAX_RLEN; i++)
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sc->irq[i].cpuid = -1;
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cpus = NULL;
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if (has_affinity) {
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ncpus = OF_getencprop_alloc_multi(node, "interrupt-affinity",
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sizeof(*cpus), (void **)&cpus);
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if (ncpus < 0) {
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device_printf(sc->dev,
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"Cannot read interrupt affinity property\n");
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return (ENXIO);
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}
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}
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/* Process first interrupt */
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rid = 0;
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sc->irq[0].res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (sc->irq[0].res == NULL) {
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device_printf(sc->dev, "Cannot get interrupt\n");
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err = ENXIO;
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goto done;
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}
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/* Check if PMU have one per-CPU interrupt */
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if (intr_is_per_cpu(sc->irq[0].res)) {
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if (has_affinity) {
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device_printf(sc->dev,
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"Per CPU interupt have declared affinity\n");
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err = ENXIO;
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goto done;
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}
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return (0);
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}
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/*
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* PMU with set of generic interrupts (one per core)
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* Each one must be binded to exact core.
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*/
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err = pmu_parse_affinity(sc, sc->irq + 0, has_affinity ? cpus[0]: 0,
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0);
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if (err != 0) {
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device_printf(sc->dev, "Cannot parse affinity for CPUid: 0\n");
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goto done;
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}
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for (i = 1; i < MAX_RLEN; i++) {
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rid = i;
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sc->irq[i].res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
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&rid, RF_ACTIVE | RF_SHAREABLE);
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if (sc->irq[i].res == NULL)
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break;
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if (intr_is_per_cpu(sc->irq[i].res))
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{
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device_printf(sc->dev, "Unexpected per CPU interupt\n");
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err = ENXIO;
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goto done;
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}
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if (has_affinity && i >= ncpus) {
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device_printf(sc->dev, "Missing value in interrupt "
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"affinity property\n");
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err = ENXIO;
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goto done;
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}
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err = pmu_parse_affinity(sc, sc->irq + i,
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has_affinity ? cpus[i]: 0, i);
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if (err != 0) {
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device_printf(sc->dev,
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"Cannot parse affinity for CPUid: %d.\n", i);
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goto done;
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}
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}
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err = 0;
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done:
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OF_prop_free(cpus);
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return (err);
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}
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static int
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pmu_attach(device_t dev)
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{
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@ -137,27 +245,34 @@ pmu_attach(device_t dev)
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#if defined(__arm__) && (__ARM_ARCH > 6)
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uint32_t iesr;
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#endif
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int err;
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int i;
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int err, i;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, pmu_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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err = pmu_parse_intr(sc);
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if (err != 0)
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return (err);
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/* Setup interrupt handler */
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for (i = 0; i < MAX_RLEN; i++) {
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if (sc->res[i] == NULL)
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if (sc->irq[i].res == NULL)
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break;
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err = bus_setup_intr(dev, sc->res[i], INTR_MPSAFE | INTR_TYPE_MISC,
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pmu_intr, NULL, NULL, &sc->ih[i]);
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if (err) {
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device_printf(dev, "Unable to setup interrupt handler.\n");
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return (ENXIO);
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err = bus_setup_intr(dev, sc->irq[i].res,
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INTR_MPSAFE | INTR_TYPE_MISC, pmu_intr, NULL, NULL,
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&sc->irq[i].ih);
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if (err != 0) {
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device_printf(dev,
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"Unable to setup interrupt handler.\n");
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goto fail;
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}
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if (sc->irq[i].cpuid != -1) {
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err = bus_bind_intr(dev, sc->irq[i].res,
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sc->irq[i].cpuid);
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if (err != 0) {
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device_printf(sc->dev,
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"Unable to bind interrupt.\n");
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goto fail;
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}
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}
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}
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@ -176,11 +291,32 @@ pmu_attach(device_t dev)
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#endif
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return (0);
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fail:
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for (i = 1; i < MAX_RLEN; i++) {
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if (sc->irq[i].ih != NULL)
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bus_teardown_intr(dev, sc->irq[i].res, sc->irq[i].ih);
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if (sc->irq[i].res != NULL)
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bus_release_resource(dev, SYS_RES_IRQ, i,
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sc->irq[i].res);
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}
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return(err);
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}
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#ifdef FDT
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static struct ofw_compat_data compat_data[] = {
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{"arm,armv8-pmuv3", 1},
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{"arm,cortex-a77-pmu", 1},
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{"arm,cortex-a76-pmu", 1},
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{"arm,cortex-a75-pmu", 1},
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{"arm,cortex-a73-pmu", 1},
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{"arm,cortex-a72-pmu", 1},
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{"arm,cortex-a65-pmu", 1},
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{"arm,cortex-a57-pmu", 1},
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{"arm,cortex-a55-pmu", 1},
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{"arm,cortex-a53-pmu", 1},
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{"arm,cortex-a34-pmu", 1},
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{"arm,cortex-a17-pmu", 1},
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{"arm,cortex-a15-pmu", 1},
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{"arm,cortex-a12-pmu", 1},
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