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Import partial support for the IQ31244 eval board (i80321 CPU). IQ80321 might

Browse Source 
work out of the box too, but I have no hardware to test.
It works well enough to go multiuser. Network works, SATA does not, as I have
no drive to test.
Thanks to Intel for sending such a board.

Obtained from:  NetBSD
This commit is contained in:
cognet 2004-09-23 22:45:36 +00:00
parent b43de02af0
commit a5a4c2b9b8
21 changed files with 3870 additions and 0 deletions
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8
sys/arm/xscale/i80321/files.i80321 Normal file
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#$FreeBSD$
arm/arm/cpufunc_asm_xscale.S standard
arm/arm/irq_dispatch.S standard
arm/xscale/i80321/i80321.c standard
arm/xscale/i80321/i80321_mcu.c standard
arm/xscale/i80321/i80321_pci.c optional pci
arm/xscale/i80321/i80321_space.c standard
arm/xscale/i80321/i80321_timer.c standard

8
sys/arm/xscale/i80321/files.iq31244 Normal file
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#$FreeBSD$
arm/xscale/i80321/iq80321.c standard
arm/xscale/i80321/iq31244_machdep.c standard
arm/xscale/i80321/obio.c standard
arm/xscale/i80321/obio_space.c standard
arm/xscale/i80321/uart_cpu_i80321.c optional uart
arm/xscale/i80321/uart_bus_i80321.c optional uart
dev/uart/uart_dev_ns8250.c optional uart

269
sys/arm/xscale/i80321/i80321.c Normal file
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/* $NetBSD: i80321.c,v 1.15 2003/10/06 16:06:05 thorpej Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Autoconfiguration support for the Intel i80321 I/O Processor.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#define _ARM32_BUS_DMA_PRIVATE
#include <machine/bus.h>
#include <machine/intr.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/i80321_intr.h>
#include <dev/pci/pcireg.h>
volatile uint32_t intr_enabled;
uint32_t intr_steer = 0;
/*
* Statically-allocated bus_space stucture used to access the
* i80321's own registers.
*/
struct bus_space i80321_bs_tag;
/*
* There can be only one i80321, so we keep a global pointer to
* the softc, so board-specific code can use features of the
* i80321 without having to have a handle on the softc itself.
*/
struct i80321_softc *i80321_softc;
/* Built-in devices. */
static const struct iopxs_device {
const char *id_name;
bus_addr_t id_offset;
bus_size_t id_size;
} iopxs_devices[] = {
{ "iopaau", VERDE_AAU_BASE, VERDE_AAU_SIZE },
/* { "iopdma", VERDE_DMA_BASE0, VERDE_DMA_CHSIZE }, */
/* { "iopdma", VERDE_DMA_BASE1, VERDE_DMA_CHSIZE }, */
{ "iopiic", VERDE_I2C_BASE0, VERDE_I2C_CHSIZE },
{ "iopiic", VERDE_I2C_BASE1, VERDE_I2C_CHSIZE },
/* { "iopssp", VERDE_SSP_BASE, VERDE_SSP_SIZE }, */
{ "iopmu", VERDE_MU_BASE, VERDE_MU_SIZE },
{ "iopwdog", 0, 0 },
{ NULL, 0, 0 }
};
#define PCI_MAPREG_MEM_ADDR(x) ((x) & 0xfffffff0)
/*
* i80321_attach:
*
* Board-independent attach routine for the i80321.
*/
void
i80321_attach(struct i80321_softc *sc)
{
i80321_softc = sc;
uint32_t preg;
/* We expect the Memory Controller to be already sliced off. */
/*
* Program the Inbound windows.
*/
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0,
(0xffffffff - (sc->sc_iwin[0].iwin_size - 1)) & 0xffffffc0);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR0,
sc->sc_iwin[0].iwin_xlate);
if (sc->sc_is_host) {
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_MAPS, sc->sc_iwin[0].iwin_base_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_MAPS + 0x04, sc->sc_iwin[0].iwin_base_hi);
} else {
sc->sc_iwin[0].iwin_base_lo = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_MAPS);
sc->sc_iwin[0].iwin_base_hi = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_MAPS + 0x04);
sc->sc_iwin[0].iwin_base_lo =
PCI_MAPREG_MEM_ADDR(sc->sc_iwin[0].iwin_base_lo);
}
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1,
(0xffffffff - (sc->sc_iwin[1].iwin_size - 1)) & 0xffffffc0);
/* no xlate for window 1 */
if (sc->sc_is_host) {
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_MAPS + 0x08, sc->sc_iwin[1].iwin_base_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_MAPS + 0x0c, sc->sc_iwin[1].iwin_base_hi);
} else {
sc->sc_iwin[1].iwin_base_lo = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_MAPS + 0x08);
sc->sc_iwin[1].iwin_base_hi = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_MAPS + 0x0c);
sc->sc_iwin[1].iwin_base_lo =
PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
}
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2,
(0xffffffff - (sc->sc_iwin[2].iwin_size - 1)) & 0xffffffc0);
printf("size : %d\n", (sc->sc_iwin[2].iwin_size - 1) / (1024 * 1024));
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR2,
sc->sc_iwin[2].iwin_xlate);
if (sc->sc_is_host) {
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_MAPS + 0x10, sc->sc_iwin[2].iwin_base_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_MAPS + 0x14, sc->sc_iwin[2].iwin_base_hi);
} else {
sc->sc_iwin[2].iwin_base_lo = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_MAPS + 0x10);
sc->sc_iwin[2].iwin_base_hi = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_MAPS + 0x14);
sc->sc_iwin[2].iwin_base_lo =
PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo);
}
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR3,
(0xffffffff - (sc->sc_iwin[3].iwin_size - 1)) & 0xffffffc0);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR3,
sc->sc_iwin[3].iwin_xlate);
if (sc->sc_is_host) {
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_IABAR3, sc->sc_iwin[3].iwin_base_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_IAUBAR3, sc->sc_iwin[3].iwin_base_hi);
} else {
sc->sc_iwin[3].iwin_base_lo = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, ATU_IABAR3);
sc->sc_iwin[3].iwin_base_hi = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, ATU_IAUBAR3);
sc->sc_iwin[3].iwin_base_lo =
PCI_MAPREG_MEM_ADDR(sc->sc_iwin[3].iwin_base_lo);
}
/*
* Mask (disable) the ATU interrupt sources.
* XXX May want to revisit this if we encounter
* XXX an application that wants it.
*/
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_ATUIMR,
ATUIMR_IMW1BU|ATUIMR_ISCEM|ATUIMR_RSCEM|ATUIMR_PST|
ATUIMR_DPE|ATUIMR_P_SERR_ASRT|ATUIMR_PMA|ATUIMR_PTAM|
ATUIMR_PTAT|ATUIMR_PMPE);
/*
* Program the outbound windows.
*/
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_OIOWTVR, sc->sc_ioout_xlate);
if (!sc->sc_is_host) {
sc->sc_owin[0].owin_xlate_lo = sc->sc_iwin[1].iwin_base_lo;
sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
}
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_OMWTVR0, sc->sc_owin[0].owin_xlate_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_OUMWTVR0, sc->sc_owin[0].owin_xlate_hi);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_OMWTVR1, sc->sc_owin[1].owin_xlate_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_OUMWTVR1, sc->sc_owin[1].owin_xlate_hi);
/*
* Set up the ATU configuration register. All we do
* right now is enable Outbound Windows.
*/
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUCR,
ATUCR_OUT_EN);
/*
* Enable bus mastering, memory access, SERR, and parity
* checking on the ATU.
*/
if (sc->sc_is_host) {
preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
PCIR_COMMAND);
preg |= PCIM_CMD_MEMEN |
PCIM_CMD_BUSMASTEREN | PCIM_CMD_PERRESPEN |
PCIM_CMD_SERRESPEN;
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_COMMAND, preg);
preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
PCIR_COMMAND);
}
/* Initialize the bus space tags. */
i80321_io_bs_init(&sc->sc_pci_iot, sc);
i80321_mem_bs_init(&sc->sc_pci_memt, sc);
intr_enabled = 0;
i80321_set_intrmask();
i80321_set_intrsteer();
}
static __inline uint32_t
i80321_iintsrc_read(void)
{
uint32_t iintsrc;
__asm __volatile("mrc p6, 0, %0, c8, c0, 0"
: "=r" (iintsrc));
/*
* The IINTSRC register shows bits that are active even
* if they are masked in INTCTL, so we have to mask them
* off with the interrupts we consider enabled.
*/
return (iintsrc & intr_enabled);
}
int
arm_get_irqnb(void *clockframe)
{
return (i80321_iintsrc_read());
}

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sys/arm/xscale/i80321/i80321_intr.h Normal file
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/* $NetBSD: i80321_intr.h,v 1.5 2004/01/12 10:25:06 scw Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _I80321_INTR_H_
#define _I80321_INTR_H_
#define ARM_IRQ_HANDLER _C_LABEL(i80321_intr_dispatch)
#ifndef _LOCORE
#include <machine/armreg.h>
#include <machine/cpufunc.h>
#include <arm/xscale/i80321/i80321reg.h>
void i80321_do_pending(void);
extern __volatile uint32_t intr_enabled;
extern uint32_t intr_steer;
static __inline void __attribute__((__unused__))
i80321_set_intrmask(void)
{
__asm __volatile("mcr p6, 0, %0, c0, c0, 0"
:
: "r" (intr_enabled & ICU_INT_HWMASK));
}
static __inline void
i80321_set_intrsteer(void)
{
__asm __volatile("mcr p6, 0, %0, c4, c0, 0"
:
: "r" (intr_steer & ICU_INT_HWMASK));
}
#define INT_SWMASK \
((1U << ICU_INT_bit26) | (1U << ICU_INT_bit22) | \
(1U << ICU_INT_bit5) | (1U << ICU_INT_bit4))
#if 0
static __inline void __attribute__((__unused__))
i80321_splx(int new)
{
extern __volatile uint32_t intr_enabled;
extern __volatile int current_spl_level;
extern __volatile int i80321_ipending;
extern void i80321_do_pending(void);
int oldirqstate, hwpend;
/* Don't let the compiler re-order this code with preceding code */
__insn_barrier();
current_spl_level = new;
hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new;
if (hwpend != 0) {
oldirqstate = disable_interrupts(I32_bit);
intr_enabled |= hwpend;
i80321_set_intrmask();
restore_interrupts(oldirqstate);
}
if ((i80321_ipending & INT_SWMASK) & ~new)
i80321_do_pending();
}
static __inline int __attribute__((__unused__))
i80321_splraise(int ipl)
{
extern __volatile int current_spl_level;
extern int i80321_imask[];
int old;
old = current_spl_level;
current_spl_level |= i80321_imask[ipl];
/* Don't let the compiler re-order this code with subsequent code */
__insn_barrier();
return (old);
}
static __inline int __attribute__((__unused__))
i80321_spllower(int ipl)
{
extern __volatile int current_spl_level;
extern int i80321_imask[];
int old = current_spl_level;
i80321_splx(i80321_imask[ipl]);
return(old);
}
#endif
#if !defined(EVBARM_SPL_NOINLINE)
#define splx(new) i80321_splx(new)
#define _spllower(ipl) i80321_spllower(ipl)
#define _splraise(ipl) i80321_splraise(ipl)
void _setsoftintr(int);
#else
int _splraise(int);
int _spllower(int);
void splx(int);
void _setsoftintr(int);
#endif /* ! EVBARM_SPL_NOINLINE */
#endif /* _LOCORE */
#endif /* _I80321_INTR_H_ */

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/* $NetBSD: i80321_mcu.c,v 1.2 2003/07/15 00:24:54 lukem Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Intel i80321 I/O Processor memory controller support.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
/*
* i80321_sdram_bounds:
*
* Retrieve the start and size of SDRAM.
*/
void
i80321_sdram_bounds(bus_space_tag_t st, bus_space_handle_t sh,
vm_paddr_t *start, vm_size_t *size)
{
uint32_t sdbr, sbr0, sbr1;
uint32_t bank0, bank1;
sdbr = bus_space_read_4(st, sh, MCU_SDBR);
sbr0 = bus_space_read_4(st, sh, MCU_SBR0);
sbr1 = bus_space_read_4(st, sh, MCU_SBR1);
#ifdef VERBOSE_INIT_ARM
printf("i80321: SBDR = 0x%08x SBR0 = 0x%08x SBR1 = 0x%08x\n",
sdbr, sbr0, sbr1);
#endif
*start = sdbr;
sdbr = (sdbr >> 25) & 0x1f;
sbr0 &= 0x3f;
sbr1 &= 0x3f;
bank0 = (sbr0 - sdbr) << 25;
bank1 = (sbr1 - sbr0) << 25;
#ifdef VERBOSE_INIT_ARM
printf("i80321: BANK0 = 0x%08x BANK1 = 0x%08x\n", bank0, bank1);
#endif
*size = bank0 + bank1;
}

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/* $NetBSD: i80321_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* PCI configuration support for i80321 I/O Processor chip.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#define __RMAN_RESOURCE_VISIBLE
#include <sys/rman.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/pcb.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_extern.h>
#include <machine/pmap.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/i80321_intr.h>
#include <dev/pci/pcib_private.h>
#include "pcib_if.h"
#include <dev/pci/pcireg.h>
extern struct i80321_softc *i80321_softc;
struct i80321_pci_softc {
device_t sc_dev;
bus_space_tag_t sc_st;
bus_space_handle_t sc_atu_sh;
bus_space_tag_t sc_pciio;
bus_space_tag_t sc_pcimem;
int sc_busno;
struct rman sc_mem_rman;
struct rman sc_io_rman;
struct rman sc_irq_rman;
uint32_t sc_mem;
uint32_t sc_io;
};
static int
i80321_pci_probe(device_t dev)
{
device_set_desc(dev, "i80321 PCI bus");
return (0);
}
static int
i80321_pci_attach(device_t dev)
{
uint32_t busno;
struct i80321_pci_softc *sc = device_get_softc(dev);
sc->sc_st = i80321_softc->sc_st;
sc->sc_atu_sh = i80321_softc->sc_atu_sh;
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
sc->sc_dev = dev;
sc->sc_busno = busno;
sc->sc_pciio = &i80321_softc->sc_pci_iot;
sc->sc_pcimem = &i80321_softc->sc_pci_memt;
sc->sc_mem = i80321_softc->sc_owin[0].owin_xlate_lo +
VERDE_OUT_XLATE_MEM_WIN_SIZE;
sc->sc_io = i80321_softc->sc_iow_vaddr;
/* Initialize memory and i/o rmans. */
sc->sc_io_rman.rm_type = RMAN_ARRAY;
sc->sc_io_rman.rm_descr = "I80321 PCI I/O Ports";
if (rman_init(&sc->sc_io_rman) != 0 ||
rman_manage_region(&sc->sc_io_rman,
sc->sc_io,
sc->sc_io +
VERDE_OUT_XLATE_IO_WIN_SIZE) != 0) {
panic("i80321_pci_probe: failed to set up I/O rman");
}
sc->sc_mem_rman.rm_type = RMAN_ARRAY;
sc->sc_mem_rman.rm_descr = "I80321 PCI Memory";
if (rman_init(&sc->sc_mem_rman) != 0 ||
rman_manage_region(&sc->sc_mem_rman,
0, VERDE_OUT_XLATE_MEM_WIN_SIZE) != 0) {
panic("i80321_pci_probe: failed to set up memory rman");
}
sc->sc_irq_rman.rm_type = RMAN_ARRAY;
sc->sc_irq_rman.rm_descr = "i80321 PCI IRQs";
if (rman_init(&sc->sc_irq_rman) != 0 ||
rman_manage_region(&sc->sc_irq_rman, 26, 32) != 0)
panic("i80321_pci_probe: failed to set up IRQ rman");
device_add_child(dev, "pci",busno);
return (bus_generic_attach(dev));
}
static int
i80321_pci_maxslots(device_t dev)
{
return (PCI_SLOTMAX);
}
static int
i80321_pci_conf_setup(struct i80321_pci_softc *sc, int bus, int slot, int func,
int reg, uint32_t *addr)
{
uint32_t busno;
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
/*
* If the bus # is the same as our own, then use Type 0 cycles,
* else use Type 1.
*
* XXX We should filter out all non-private devices here!
* XXX How does private space interact with PCI-PCI bridges?
*/
if (bus == busno) {
if (slot > (31 - 16))
return (1);
/*
* NOTE: PCI-X requires that that devices updated their
* PCIXSR on every config write with the device number
* specified in AD[15:11]. If we don't set this field,
* each device could end of thinking it is at device 0,
* which can cause a number of problems. Doing this
* unconditionally should be OK when only PCI devices
* are present.
*/
bus &= 0xff;
slot &= 0x1f;
func &= 0x07;
*addr = (1U << (slot + 16)) |
(slot << 11) | (func << 8) | reg;
} else {
*addr = (bus << 16) | (slot << 11) | (func << 8) | reg | 1;
}
return (0);
}
static u_int32_t
i80321_pci_read_config(device_t dev, int bus, int slot, int func, int reg,
int bytes)
{
struct i80321_pci_softc *sc = device_get_softc(dev);
uint32_t isr;
uint32_t addr;
u_int32_t ret = 0;
vm_offset_t va;
int err = 0;
if (i80321_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
return (-1);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
addr/* & ~3*/);
va = sc->sc_atu_sh;
switch (bytes) {
case 1:
err = badaddr_read((void*)(va + ATU_OCCDR + (reg & 3)), 1, &ret);
break;
case 2:
err = badaddr_read((void*)(va + ATU_OCCDR + (reg & 3)), 2, &ret);
break;
case 4:
err = badaddr_read((void *)(va + ATU_OCCDR), 4, &ret);
break;
default:
printf("i803218_read_config: invalid size %d\n", bytes);
ret = -1;
}
if (err) {
isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR,
isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM|
ATUISR_PTAT|ATUISR_PMPE));
return (-1);
}
return (ret);
}
static void
i80321_pci_write_config(device_t dev, int bus, int slot, int func, int reg,
u_int32_t data, int bytes)
{
struct i80321_pci_softc *sc = device_get_softc(dev);
uint32_t addr;
if (i80321_pci_conf_setup(sc, bus, slot, func, reg, &addr))
return;
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
addr);
switch (bytes) {
case 1:
bus_space_write_1(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, data);
break;
case 2:
bus_space_write_2(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, data);
break;
case 4:
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, data);
break;
default:
printf("i80321_pci_write_config: Invalid size : %d\n", bytes);
}
}
static int
i80321_pci_route_interrupt(device_t pcib, device_t dev, int pin)
{
int bus;
int device;
int func;
uint32_t busno;
struct i80321_pci_softc *sc = device_get_softc(pcib);
bus = pci_get_bus(dev);
device = pci_get_slot(dev);
func = pci_get_function(dev);
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
if (bus != busno)
goto no_mapping;
switch (device) {
/* IQ31244 PCI */
case 1: /* PCIX-PCIX bridge */
/*
* The S-ATA chips are behind the bridge, and all of
* the S-ATA interrupts are wired together.
*/
return (ICU_INT_XINT(2));
case 2: /* PCI slot */
/* All pins are wired together. */
return (ICU_INT_XINT(3));
case 3: /* i82546 dual Gig-E */
if (pin == 1 || pin == 2)
return (ICU_INT_XINT(0));
goto no_mapping;
/* IQ80321 PCI */
case 4: /* i82544 Gig-E */
if (pin == 1)
return (ICU_INT_XINT(0));
goto no_mapping;
case 6: /* S-PCI-X slot */
if (pin == 1)
return (ICU_INT_XINT(2));
if (pin == 2)
return (ICU_INT_XINT(3));
goto no_mapping;
default:
no_mapping:
printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin);
}
return (0);
}
static int
i80321_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{
struct i80321_pci_softc *sc = device_get_softc(dev);
switch (which) {
case PCIB_IVAR_BUS:
*result = sc->sc_busno;
return (0);
}
return (ENOENT);
}
static int
i80321_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
{
struct i80321_pci_softc * sc = device_get_softc(dev);
switch (which) {
case PCIB_IVAR_BUS:
sc->sc_busno = result;
return (0);
}
return (ENOENT);
}
static struct resource *
i80321_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags)
{
struct i80321_pci_softc *sc = device_get_softc(bus);
struct resource *rv;
struct rman *rm;
bus_space_tag_t bt = NULL;
bus_space_handle_t bh = 0;
if (type == SYS_RES_IRQ) {
rv = malloc(sizeof(*rv), M_DEVBUF, M_WAITOK);
rv->r_start = start;
rv->r_end = end;
rv->r_rid = *rid;
return (rv);
}
switch (type) {
case SYS_RES_IRQ:
rm = &sc->sc_mem_rman;
break;
case SYS_RES_MEMORY:
rm = &sc->sc_mem_rman;
bt = sc->sc_pcimem;
bh = sc->sc_mem;
break;
case SYS_RES_IOPORT:
rm = &sc->sc_io_rman;
bt = sc->sc_pciio;
bh = sc->sc_io;
start = start - 0x90000000 + sc->sc_io;
end = end - 0x90000000 + sc->sc_io;
break;
default:
return (NULL);
}
rv = rman_reserve_resource(rm, start, end, count, flags, child);
if (rv == NULL)
return (NULL);
if (type != SYS_RES_IRQ) {
bh += (rman_get_start(rv));
rman_set_bustag(rv, bt);
rman_set_bushandle(rv, bh);
if (flags & RF_ACTIVE) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
}
return (rv);
}
static int
i80321_pci_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
u_long p;
int error;
if (type == SYS_RES_MEMORY) {
error = bus_space_map(rman_get_bustag(r),
rman_get_bushandle(r), rman_get_size(r), 0, &p);
if (error)
return (error);
rman_set_bushandle(r, p);
}
return (rman_activate_resource(r));
}
static int
i80321_pci_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_intr_t *intr, void *arg,
void **cookiep)
{
return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
intr, arg, cookiep));
}
static device_method_t i80321_pci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, i80321_pci_probe),
DEVMETHOD(device_attach, i80321_pci_attach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
/* Bus interface */
DEVMETHOD(bus_print_child, bus_generic_print_child),
DEVMETHOD(bus_read_ivar, i80321_read_ivar),
DEVMETHOD(bus_write_ivar, i80321_write_ivar),
DEVMETHOD(bus_alloc_resource, i80321_pci_alloc_resource),
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
DEVMETHOD(bus_activate_resource, i80321_pci_activate_resource),
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
DEVMETHOD(bus_setup_intr, i80321_pci_setup_intr),
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
/* pcib interface */
DEVMETHOD(pcib_maxslots, i80321_pci_maxslots),
DEVMETHOD(pcib_read_config, i80321_pci_read_config),
DEVMETHOD(pcib_write_config, i80321_pci_write_config),
DEVMETHOD(pcib_route_interrupt, i80321_pci_route_interrupt),
{0, 0}
};
static driver_t i80321_pci_driver = {
"pcib",
i80321_pci_methods,
sizeof(struct i80321_pci_softc),
};
static devclass_t i80321_pci_devclass;
DRIVER_MODULE(ipci, iq, i80321_pci_driver, i80321_pci_devclass, 0, 0);

309
sys/arm/xscale/i80321/i80321_space.c Normal file
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/* $NetBSD: i80321_space.c,v 1.6 2003/10/06 15:43:35 thorpej Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* bus_space functions for i80321 I/O Processor.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <machine/pcb.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#include <vm/pmap.h>
#include <vm/vm_page.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
/* Prototypes for all the bus_space structure functions */
bs_protos(i80321);
bs_protos(i80321_io);
bs_protos(i80321_mem);
bs_protos(generic);
bs_protos(generic_armv4);
bs_protos(bs_notimpl);
/*
* Template bus_space -- copied, and the bits that are NULL are
* filled in.
*/
const struct bus_space i80321_bs_tag_template = {
/* cookie */
(void *) 0,
/* mapping/unmapping */
NULL,
NULL,
i80321_bs_subregion,
/* allocation/deallocation */
NULL,
NULL,
/* barrier */
i80321_bs_barrier,
/* read (single) */
generic_bs_r_1,
generic_armv4_bs_r_2,
generic_bs_r_4,
NULL,
/* read multiple */
generic_bs_rm_1,
generic_armv4_bs_rm_2,
generic_bs_rm_4,
NULL,
/* read region */
NULL,
generic_armv4_bs_rr_2,
generic_bs_rr_4,
NULL,
/* write (single) */
generic_bs_w_1,
generic_armv4_bs_w_2,
generic_bs_w_4,
NULL,
/* write multiple */
generic_bs_wm_1,
generic_armv4_bs_wm_2,
generic_bs_wm_4,
NULL,
/* write region */
NULL,
generic_armv4_bs_wr_2,
generic_bs_wr_4,
NULL,
/* set multiple */
NULL,
NULL,
NULL,
NULL,
/* set region */
NULL,
generic_armv4_bs_sr_2,
generic_bs_sr_4,
NULL,
/* copy */
NULL,
generic_armv4_bs_c_2,
NULL,
NULL,
};
void
i80321_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = i80321_bs_tag_template;
bs->bs_cookie = cookie;
}
void
i80321_io_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = i80321_bs_tag_template;
bs->bs_cookie = cookie;
bs->bs_map = i80321_io_bs_map;
bs->bs_unmap = i80321_io_bs_unmap;
bs->bs_alloc = i80321_io_bs_alloc;
bs->bs_free = i80321_io_bs_free;
}
void
i80321_mem_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = i80321_bs_tag_template;
bs->bs_cookie = cookie;
bs->bs_map = i80321_mem_bs_map;
bs->bs_unmap = i80321_mem_bs_unmap;
bs->bs_alloc = i80321_mem_bs_alloc;
bs->bs_free = i80321_mem_bs_free;
}
/* *** Routines shared by i80321, PCI IO, and PCI MEM. *** */
int
i80321_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t size, bus_space_handle_t *nbshp)
{
*nbshp = bsh + offset;
return (0);
}
void
i80321_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t len, int flags)
{
/* Nothing to do. */
}
/* *** Routines for PCI IO. *** */
extern struct i80321_softc *i80321_softc;
int
i80321_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
bus_space_handle_t *bshp)
{
struct i80321_softc *sc = i80321_softc;
vm_offset_t winvaddr;
uint32_t busbase;
if (bpa >= sc->sc_ioout_xlate &&
bpa < (sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE)) {
busbase = sc->sc_ioout_xlate;
winvaddr = sc->sc_iow_vaddr;
} else
return (EINVAL);
if ((bpa + size) >= (busbase + VERDE_OUT_XLATE_IO_WIN_SIZE))
return (EINVAL);
/*
* Found the window -- PCI I/O space is mapped at a fixed
* virtual address by board-specific code. Translate the
* bus address to the virtual address.
*/
*bshp = winvaddr + (bpa - busbase);
return (0);
}
void
i80321_io_bs_unmap(void *t, bus_size_t size)
{
/* Nothing to do. */
}
int
i80321_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
bus_addr_t *bpap, bus_space_handle_t *bshp)
{
panic("i80321_io_bs_alloc(): not implemented");
}
void
i80321_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{
panic("i80321_io_bs_free(): not implemented");
}
/* *** Routines for PCI MEM. *** */
extern int badaddr_read(void *, int, void *);
int
i80321_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
bus_space_handle_t *bshp)
{
vm_offset_t va;
uint32_t busbase;
vm_paddr_t pa, endpa, physbase;
/*
* Found the window -- PCI MEM space is not mapped by allocating
* some kernel VA space and mapping the pages with pmap_enter().
* pmap_enter() will map unmanaged pages as non-cacheable.
*/
pa = trunc_page((bpa - busbase) + physbase);
endpa = round_page(((bpa - busbase) + physbase) + size);
pa = trunc_page(bpa);
endpa = round_page(bpa + size);
*bshp = va + (bpa & PAGE_MASK);
*bshp = pa;
*bshp = (vm_offset_t)pmap_mapdev(pa, endpa - pa);
return (0);
}
void
i80321_mem_bs_unmap(void *t, bus_size_t size)
{
vm_offset_t va, endva;
va = trunc_page((vm_offset_t)t);
endva = va + round_page(size);
/* Free the kernel virtual mapping. */
kmem_free(kernel_map, va, endva - va);
}
int
i80321_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
bus_addr_t *bpap, bus_space_handle_t *bshp)
{
panic("i80321_mem_bs_alloc(): not implemented");
}
void
i80321_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{
panic("i80321_mem_bs_free(): not implemented");
}

394
sys/arm/xscale/i80321/i80321_timer.c Normal file
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/* $NetBSD: i80321_timer.c,v 1.7 2003/07/27 04:52:28 thorpej Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Timer/clock support for the Intel i80321 I/O processor.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/time.h>
#include <sys/bus.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/timetc.h>
#include <machine/bus.h>
#include <machine/cpufunc.h>
#include <machine/resource.h>
#include <machine/intr.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/xscalevar.h>
struct i80321_timer_softc {
device_t dev;
} timer_softc;
static unsigned i80321_timer_get_timecount(struct timecounter *tc);
static uint32_t counts_per_hz;
static uint32_t offset = 0;
static int32_t last = -1;
static int ticked = 0;
#define COUNTS_PER_SEC 200000000 /* 200MHz */
#define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000)
static struct timecounter i80321_timer_timecounter = {
i80321_timer_get_timecount, /* get_timecount */
NULL, /* no poll_pps */
~0u, /* counter_mask */
COUNTS_PER_SEC, /* frequency */
"i80321 timer", /* name */
1000 /* quality */
};
static int
i80321_timer_probe(device_t dev)
{
return (0);
}
static int
i80321_timer_attach(device_t dev)
{
timer_softc.dev = dev;
return (0);
}
static device_method_t i80321_timer_methods[] = {
DEVMETHOD(device_probe, i80321_timer_probe),
DEVMETHOD(device_attach, i80321_timer_attach),
{0, 0},
};
static driver_t i80321_timer_driver = {
"itimer",
i80321_timer_methods,
sizeof(struct i80321_timer_softc),
};
static devclass_t i80321_timer_devclass;
DRIVER_MODULE(itimer, iq, i80321_timer_driver, i80321_timer_devclass, 0, 0);
void counterhandler(void *);
void clockhandler(void *);
static __inline uint32_t
tmr1_read(void)
{
uint32_t rv;
__asm __volatile("mrc p6, 0, %0, c1, c1, 0"
: "=r" (rv));
return (rv);
}
static __inline void
tmr1_write(uint32_t val)
{
__asm __volatile("mcr p6, 0, %0, c1, c1, 0"
:
: "r" (val));
}
static __inline uint32_t
tcr1_read(void)
{
uint32_t rv;
__asm __volatile("mrc p6, 0, %0, c3, c1, 0"
: "=r" (rv));
return (rv);
}
static __inline void
tcr1_write(uint32_t val)
{
__asm __volatile("mcr p6, 0, %0, c3, c1, 0"
:
: "r" (val));
}
static __inline void
trr1_write(uint32_t val)
{
__asm __volatile("mcr p6, 1, %0, c5, c1, 0"
:
: "r" (val));
}
static __inline uint32_t
tmr0_read(void)
{
uint32_t rv;
__asm __volatile("mrc p6, 0, %0, c0, c1, 0"
: "=r" (rv));
return (rv);
}
static __inline void
tmr0_write(uint32_t val)
{
__asm __volatile("mcr p6, 0, %0, c0, c1, 0"
:
: "r" (val));
}
static __inline uint32_t
tcr0_read(void)
{
uint32_t rv;
__asm __volatile("mrc p6, 0, %0, c2, c1, 0"
: "=r" (rv));
return (rv);
}
static __inline void
tcr0_write(uint32_t val)
{
__asm __volatile("mcr p6, 0, %0, c2, c1, 0"
:
: "r" (val));
}
static __inline void
trr0_write(uint32_t val)
{
__asm __volatile("mcr p6, 0, %0, c4, c1, 0"
:
: "r" (val));
}
static __inline void
tisr_write(uint32_t val)
{
__asm __volatile("mcr p6, 0, %0, c6, c1, 0"
:
: "r" (val));
}
static __inline uint32_t
tisr_read(void)
{
int ret;
__asm __volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (ret));
return (ret);
}
static unsigned
i80321_timer_get_timecount(struct timecounter *tc)
{
int32_t cur = tcr0_read();
if (cur > last && last != -1) {
offset += counts_per_hz;
if (ticked > 0)
ticked--;
}
if (ticked) {
offset += ticked * counts_per_hz;
ticked = 0;
}
last = cur;
return (counts_per_hz - cur + offset);
}
/*
* i80321_calibrate_delay:
*
* Calibrate the delay loop.
*/
void
i80321_calibrate_delay(void)
{
/*
* Just use hz=100 for now -- we'll adjust it, if necessary,
* in cpu_initclocks().
*/
counts_per_hz = COUNTS_PER_SEC / 100;
tmr0_write(0); /* stop timer */
tisr_write(TISR_TMR0); /* clear interrupt */
trr0_write(counts_per_hz); /* reload value */
tcr0_write(counts_per_hz); /* current value */
tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
}
/*
* cpu_initclocks:
*
* Initialize the clock and get them going.
*/
void
cpu_initclocks(void)
{
u_int oldirqstate;
struct resource *irq;
int rid = 0;
void *ihl;
device_t dev = timer_softc.dev;
if (hz < 50 || COUNTS_PER_SEC % hz) {
printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
hz = 100;
}
tick = 1000000 / hz; /* number of microseconds between interrupts */
/*
* We only have one timer available; stathz and profhz are
* always left as 0 (the upper-layer clock code deals with
* this situation).
*/
if (stathz != 0)
printf("Cannot get %d Hz statclock\n", stathz);
stathz = 0;
if (profhz != 0)
printf("Cannot get %d Hz profclock\n", profhz);
profhz = 0;
/* Report the clock frequency. */
oldirqstate = disable_interrupts(I32_bit);
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, ICU_INT_TMR0,
ICU_INT_TMR0, 1, RF_ACTIVE);
if (!irq)
panic("Unable to setup the clock irq handler.\n");
else
bus_setup_intr(dev, irq, INTR_TYPE_CLK | INTR_FAST,
clockhandler, NULL, &ihl);
tmr0_write(0); /* stop timer */
tisr_write(TISR_TMR0); /* clear interrupt */
counts_per_hz = COUNTS_PER_SEC / hz;
trr0_write(counts_per_hz); /* reload value */
tcr0_write(counts_per_hz); /* current value */
tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
tc_init(&i80321_timer_timecounter);
restore_interrupts(oldirqstate);
}
/*
* DELAY:
*
* Delay for at least N microseconds.
*/
void
DELAY(int n)
{
uint32_t cur, last, delta, usecs;
/*
* This works by polling the timer and counting the
* number of microseconds that go by.
*/
last = tcr0_read();
delta = usecs = 0;
while (n > usecs) {
cur = tcr0_read();
/* Check to see if the timer has wrapped around. */
if (last < cur)
delta += (last + (counts_per_hz - cur));
else
delta += (last - cur);
last = cur;
if (delta >= COUNTS_PER_USEC) {
usecs += delta / COUNTS_PER_USEC;
delta %= COUNTS_PER_USEC;
}
}
}
/*
* clockhandler:
*
* Handle the hardclock interrupt.
*/
void
clockhandler(void *arg)
{
struct clockframe *frame = arg;
ticked++;
tisr_write(TISR_TMR0);
hardclock(frame);
return;
}
void
cpu_startprofclock(void)
{
}
void
cpu_stopprofclock(void)
{
}

504
sys/arm/xscale/i80321/i80321reg.h Normal file
View File

@ -0,0 +1,504 @@
/* $NetBSD: i80321reg.h,v 1.14 2003/12/19 10:08:11 gavan Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _ARM_XSCALE_I80321REG_H_
#define _ARM_XSCALE_I80321REG_H_
/*
* Register definitions for the Intel 80321 (``Verde'') I/O processor,
* based on the XScale core.
*/
/*
* Base i80321 memory map:
*
* 0x0000.0000 - 0x7fff.ffff ATU Outbound Direct Addressing Window
* 0x8000.0000 - 0x9001.ffff ATU Outbound Translation Windows
* 0x9002.0000 - 0xffff.dfff External Memory
* 0xffff.e000 - 0xffff.e8ff Peripheral Memory Mapped Registers
* 0xffff.e900 - 0xffff.ffff Reserved
*/
#define VERDE_OUT_DIRECT_WIN_BASE 0x00000000UL
#define VERDE_OUT_DIRECT_WIN_SIZE 0x80000000UL
#define VERDE_OUT_XLATE_MEM_WIN_SIZE 0x04000000UL
#define VERDE_OUT_XLATE_IO_WIN_SIZE 0x00010000UL
#define VERDE_OUT_XLATE_MEM_WIN0_BASE 0x80000000UL
#define VERDE_OUT_XLATE_MEM_WIN1_BASE 0x84000000UL
#define VERDE_OUT_XLATE_IO_WIN0_BASE 0x90000000UL
#define VERDE_EXTMEM_BASE 0x90020000UL
#define VERDE_PMMR_BASE 0xffffe000UL
#define VERDE_PMMR_SIZE 0x00001700UL
/*
* Peripheral Memory Mapped Registers. Defined as offsets
* from the VERDE_PMMR_BASE.
*/
#define VERDE_ATU_BASE 0x0100
#define VERDE_ATU_SIZE 0x0100
#define VERDE_MU_BASE 0x0300
#define VERDE_MU_SIZE 0x0100
#define VERDE_DMA_BASE 0x0400
#define VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00)
#define VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40)
#define VERDE_DMA_SIZE 0x0100
#define VERDE_DMA_CHSIZE 0x0040
#define VERDE_MCU_BASE 0x0500
#define VERDE_MCU_SIZE 0x0100
#define VERDE_SSP_BASE 0x0600
#define VERDE_SSP_SIZE 0x0080
#define VERDE_PBIU_BASE 0x0680
#define VERDE_PBIU_SIZE 0x0080
#define VERDE_AAU_BASE 0x0800
#define VERDE_AAU_SIZE 0x0100
#define VERDE_I2C_BASE 0x1680
#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00)
#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20)
#define VERDE_I2C_SIZE 0x0080
#define VERDE_I2C_CHSIZE 0x0020
/*
* Address Translation Unit
*/
/* 0x00 - 0x38 -- PCI configuration space header */
#define ATU_IALR0 0x40 /* Inbound ATU Limit 0 */
#define ATU_IATVR0 0x44 /* Inbound ATU Xlate Value 0 */
#define ATU_ERLR 0x48 /* Expansion ROM Limit */
#define ATU_ERTVR 0x4c /* Expansion ROM Xlate Value */
#define ATU_IALR1 0x50 /* Inbound ATU Limit 1 */
#define ATU_IALR2 0x54 /* Inbound ATU Limit 2 */
#define ATU_IATVR2 0x58 /* Inbound ATU Xlate Value 2 */
#define ATU_OIOWTVR 0x5c /* Outbound I/O Window Xlate Value */
#define ATU_OMWTVR0 0x60 /* Outbound Mem Window Xlate Value 0 */
#define ATU_OUMWTVR0 0x64 /* Outbound Mem Window Xlate Value 0 Upper */
#define ATU_OMWTVR1 0x68 /* Outbound Mem Window Xlate Value 1 */
#define ATU_OUMWTVR1 0x6c /* Outbound Mem Window Xlate Value 1 Upper */
#define ATU_OUDWTVR 0x78 /* Outbound Mem Direct Xlate Value Upper */
#define ATU_ATUCR 0x80 /* ATU Configuration */
#define ATU_PCSR 0x84 /* PCI Configuration and Status */
#define ATU_ATUISR 0x88 /* ATU Interrupt Status */
#define ATU_ATUIMR 0x8c /* ATU Interrupt Mask */
#define ATU_IABAR3 0x90 /* Inbound ATU Base Address 3 */
#define ATU_IAUBAR3 0x94 /* Inbound ATU Base Address 3 Upper */
#define ATU_IALR3 0x98 /* Inbound ATU Limit 3 */
#define ATU_IATVR3 0x9c /* Inbound ATU Xlate Value 3 */
#define ATU_OCCAR 0xa4 /* Outbound Configuration Cycle Address */
#define ATU_OCCDR 0xac /* Outbound Configuration Cycle Data */
#define ATU_MSI_PORT 0xb4 /* MSI port */
#define ATU_PDSCR 0xbc /* PCI Bus Drive Strength Control */
#define ATU_PCI_X_CAP_ID 0xe0 /* (1) */
#define ATU_PCI_X_NEXT 0xe1 /* (1) */
#define ATU_PCIXCMD 0xe2 /* PCI-X Command Register (2) */
#define ATU_PCIXSR 0xe4 /* PCI-X Status Register */
#define ATUCR_DRC_ALIAS (1U << 19)
#define ATUCR_DAU2GXEN (1U << 18)
#define ATUCR_P_SERR_MA (1U << 16)
#define ATUCR_DTS (1U << 15)
#define ATUCR_P_SERR_DIE (1U << 9)
#define ATUCR_DAE (1U << 8)
#define ATUCR_BIST_IE (1U << 3)
#define ATUCR_OUT_EN (1U << 1)
#define PCSR_DAAAPE (1U << 18)
#define PCSR_PCI_X_CAP (3U << 16)
#define PCSR_PCI_X_CAP_BORING (0 << 16)
#define PCSR_PCI_X_CAP_66 (1U << 16)
#define PCSR_PCI_X_CAP_100 (2U << 16)
#define PCSR_PCI_X_CAP_133 (3U << 16)
#define PCSR_OTQB (1U << 15)
#define PCSR_IRTQB (1U << 14)
#define PCSR_DTV (1U << 12)
#define PCSR_BUS66 (1U << 10)
#define PCSR_BUS64 (1U << 8)
#define PCSR_RIB (1U << 5)
#define PCSR_RPB (1U << 4)
#define PCSR_CCR (1U << 2)
#define PCSR_CPR (1U << 1)
#define ATUISR_IMW1BU (1U << 14)
#define ATUISR_ISCEM (1U << 13)
#define ATUISR_RSCEM (1U << 12)
#define ATUISR_PST (1U << 11)
#define ATUISR_P_SERR_ASRT (1U << 10)
#define ATUISR_DPE (1U << 9)
#define ATUISR_BIST (1U << 8)
#define ATUISR_IBMA (1U << 7)
#define ATUISR_P_SERR_DET (1U << 4)
#define ATUISR_PMA (1U << 3)
#define ATUISR_PTAM (1U << 2)
#define ATUISR_PTAT (1U << 1)
#define ATUISR_PMPE (1U << 0)
#define ATUIMR_IMW1BU (1U << 11)
#define ATUIMR_ISCEM (1U << 10)
#define ATUIMR_RSCEM (1U << 9)
#define ATUIMR_PST (1U << 8)
#define ATUIMR_DPE (1U << 7)
#define ATUIMR_P_SERR_ASRT (1U << 6)
#define ATUIMR_PMA (1U << 5)
#define ATUIMR_PTAM (1U << 4)
#define ATUIMR_PTAT (1U << 3)
#define ATUIMR_PMPE (1U << 2)
#define ATUIMR_IE_SERR_EN (1U << 1)
#define ATUIMR_ECC_TAE (1U << 0)
#define PCIXCMD_MOST_1 (0 << 4)
#define PCIXCMD_MOST_2 (1 << 4)
#define PCIXCMD_MOST_3 (2 << 4)
#define PCIXCMD_MOST_4 (3 << 4)
#define PCIXCMD_MOST_8 (4 << 4)
#define PCIXCMD_MOST_12 (5 << 4)
#define PCIXCMD_MOST_16 (6 << 4)
#define PCIXCMD_MOST_32 (7 << 4)
#define PCIXCMD_MOST_MASK (7 << 4)
#define PCIXCMD_MMRBC_512 (0 << 2)
#define PCIXCMD_MMRBC_1024 (1 << 2)
#define PCIXCMD_MMRBC_2048 (2 << 2)
#define PCIXCMD_MMRBC_4096 (3 << 2)
#define PCIXCMD_MMRBC_MASK (3 << 2)
#define PCIXCMD_ERO (1U << 1)
#define PCIXCMD_DPERE (1U << 0)
#define PCIXSR_RSCEM (1U << 29)
#define PCIXSR_DMCRS_MASK (7 << 26)
#define PCIXSR_DMOST_MASK (7 << 23)
#define PCIXSR_COMPLEX (1U << 20)
#define PCIXSR_USC (1U << 19)
#define PCIXSR_SCD (1U << 18)
#define PCIXSR_133_CAP (1U << 17)
#define PCIXSR_32PCI (1U << 16) /* 0 = 32, 1 = 64 */
#define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8)
#define PCIXSR_DEVNO(x) (((x) & 0xf8) >> 3)
#define PCIXSR_FUNCNO(x) ((x) & 0x7)
/*
* Memory Controller Unit
*/
#define MCU_SDIR 0x00 /* DDR SDRAM Init. Register */
#define MCU_SDCR 0x04 /* DDR SDRAM Control Register */
#define MCU_SDBR 0x08 /* SDRAM Base Register */
#define MCU_SBR0 0x0c /* SDRAM Boundary 0 */
#define MCU_SBR1 0x10 /* SDRAM Boundary 1 */
#define MCU_ECCR 0x34 /* ECC Control Register */
#define MCU_ELOG0 0x38 /* ECC Log 0 */
#define MCU_ELOG1 0x3c /* ECC Log 1 */
#define MCU_ECAR0 0x40 /* ECC address 0 */
#define MCU_ECAR1 0x44 /* ECC address 1 */
#define MCU_ECTST 0x48 /* ECC test register */
#define MCU_MCISR 0x4c /* MCU Interrupt Status Register */
#define MCU_RFR 0x50 /* Refresh Frequency Register */
#define MCU_DBUDSR 0x54 /* Data Bus Pull-up Drive Strength */
#define MCU_DBDDSR 0x58 /* Data Bus Pull-down Drive Strength */
#define MCU_CUDSR 0x5c /* Clock Pull-up Drive Strength */
#define MCU_CDDSR 0x60 /* Clock Pull-down Drive Strength */
#define MCU_CEUDSR 0x64 /* Clock En Pull-up Drive Strength */
#define MCU_CEDDSR 0x68 /* Clock En Pull-down Drive Strength */
#define MCU_CSUDSR 0x6c /* Chip Sel Pull-up Drive Strength */
#define MCU_CSDDSR 0x70 /* Chip Sel Pull-down Drive Strength */
#define MCU_REUDSR 0x74 /* Rx En Pull-up Drive Strength */
#define MCU_REDDSR 0x78 /* Rx En Pull-down Drive Strength */
#define MCU_ABUDSR 0x7c /* Addr Bus Pull-up Drive Strength */
#define MCU_ABDDSR 0x80 /* Addr Bus Pull-down Drive Strength */
#define MCU_DSDR 0x84 /* Data Strobe Delay Register */
#define MCU_REDR 0x88 /* Rx Enable Delay Register */
#define SDCR_DIMMTYPE (1U << 1) /* 0 = unbuf, 1 = reg */
#define SDCR_BUSWIDTH (1U << 2) /* 0 = 64, 1 = 32 */
#define SBRx_TECH (1U << 31)
#define SBRx_BOUND 0x0000003f
#define ECCR_SBERE (1U << 0)
#define ECCR_MBERE (1U << 1)
#define ECCR_SBECE (1U << 2)
#define ECCR_ECCEN (1U << 3)
#define ELOGx_SYNDROME 0x000000ff
#define ELOGx_ERRTYPE (1U << 8) /* 1 = multi-bit */
#define ELOGx_RW (1U << 12) /* 1 = write error */
/*
* Dev ID Func Requester
* 2 0 XScale core
* 2 1 ATU
* 13 0 DMA channel 0
* 13 1 DMA channel 1
* 26 0 ATU
*/
#define ELOGx_REQ_DEV(x) (((x) >> 19) & 0x1f)
#define ELOGx_REQ_FUNC(x) (((x) >> 16) & 0x3)
#define MCISR_ECC_ERR0 (1U << 0)
#define MCISR_ECC_ERR1 (1U << 1)
#define MCISR_ECC_ERRN (1U << 2)
/*
* Timers
*
* The i80321 timer registers are available in both memory-mapped
* and coprocessor spaces. Most of the registers are read-only
* if memory-mapped, so we access them via coprocessor space.
*
* TMR0 cp6 c0,1 0xffffe7e0
* TMR1 cp6 c1,1 0xffffe7e4
* TCR0 cp6 c2,1 0xffffe7e8
* TCR1 cp6 c3,1 0xffffe7ec
* TRR0 cp6 c4,1 0xffffe7f0
* TRR1 cp6 c5,1 0xffffe7f4
* TISR cp6 c6,1 0xffffe7f8
* WDTCR cp6 c7,1 0xffffe7fc
*/
#define TMRx_TC (1U << 0)
#define TMRx_ENABLE (1U << 1)
#define TMRx_RELOAD (1U << 2)
#define TMRx_CSEL_CORE (0 << 4)
#define TMRx_CSEL_CORE_div4 (1 << 4)
#define TMRx_CSEL_CORE_div8 (2 << 4)
#define TMRx_CSEL_CORE_div16 (3 << 4)
#define TISR_TMR0 (1U << 0)
#define TISR_TMR1 (1U << 1)
#define WDTCR_ENABLE1 0x1e1e1e1e
#define WDTCR_ENABLE2 0xe1e1e1e1
/*
* Interrupt Controller Unit.
*
* INTCTL cp6 c0,0 0xffffe7d0
* INTSTR cp6 c4,0 0xffffe7d4
* IINTSRC cp6 c8,0 0xffffe7d8
* FINTSRC cp6 c9,0 0xffffe7dc
* PIRSR 0xffffe1ec
*/
#define ICU_PIRSR 0x01ec
#define ICU_GPOE 0x07c4
#define ICU_GPID 0x07c8
#define ICU_GPOD 0x07cc
/*
* NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE
* INTERRUPTS. See i80321_icu.c
*/
#define ICU_INT_HPI 31 /* high priority interrupt */
#define ICU_INT_XINT0 27 /* external interrupts */
#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0)
#define ICU_INT_bit26 26
#define ICU_INT_SSP 25 /* SSP serial port */
#define ICU_INT_MUE 24 /* msg unit error */
#define ICU_INT_AAUE 23 /* AAU error */
#define ICU_INT_bit22 22
#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */
#define ICU_INT_DMA0E 20 /* DMA Ch 0 error */
#define ICU_INT_MCUE 19 /* memory controller error */
#define ICU_INT_ATUE 18 /* ATU error */
#define ICU_INT_BIUE 17 /* bus interface unit error */
#define ICU_INT_PMU 16 /* XScale PMU */
#define ICU_INT_PPM 15 /* peripheral PMU */
#define ICU_INT_BIST 14 /* ATU Start BIST */
#define ICU_INT_MU 13 /* messaging unit */
#define ICU_INT_I2C1 12 /* i2c unit 1 */
#define ICU_INT_I2C0 11 /* i2c unit 0 */
#define ICU_INT_TMR1 10 /* timer 1 */
#define ICU_INT_TMR0 9 /* timer 0 */
#define ICU_INT_CPPM 8 /* core processor PMU */
#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */
#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */
#define ICU_INT_bit5 5
#define ICU_INT_bit4 4
#define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */
#define ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */
#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */
#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */
#define ICU_INT_HWMASK (0xffffffff & \
~((1 << ICU_INT_bit26) | \
(1 << ICU_INT_bit22) | \
(1 << ICU_INT_bit5) | \
(1 << ICU_INT_bit4)))
/*
* SSP Serial Port
*/
#define SSP_SSCR0 0x00 /* SSC control 0 */
#define SSP_SSCR1 0x04 /* SSC control 1 */
#define SSP_SSSR 0x08 /* SSP status */
#define SSP_SSITR 0x0c /* SSP interrupt test */
#define SSP_SSDR 0x10 /* SSP data */
#define SSP_SSCR0_DSIZE(x) ((x) - 1)/* data size: 4..16 */
#define SSP_SSCR0_FRF_SPI (0 << 4) /* Motorola Serial Periph Iface */
#define SSP_SSCR0_FRF_SSP (1U << 4)/* TI Sync. Serial Protocol */
#define SSP_SSCR0_FRF_UWIRE (2U << 4)/* NatSemi Microwire */
#define SSP_SSCR0_FRF_rsvd (3U << 4)/* reserved */
#define SSP_SSCR0_ECS (1U << 6)/* external clock select */
#define SSP_SSCR0_SSE (1U << 7)/* sync. serial port enable */
#define SSP_SSCR0_SCR(x) ((x) << 8)/* serial clock rate */
/* bit rate = 3.6864 * 10e6 /
(2 * (SCR + 1)) */
#define SSP_SSCR1_RIE (1U << 0)/* Rx FIFO interrupt enable */
#define SSP_SSCR1_TIE (1U << 1)/* Tx FIFO interrupt enable */
#define SSP_SSCR1_LBM (1U << 2)/* loopback mode enable */
#define SSP_SSCR1_SPO (1U << 3)/* Moto SPI SSCLK pol. (1 = high) */
#define SSP_SSCR1_SPH (1U << 4)/* Moto SPI SSCLK phase:
0 = inactive full at start,
1/2 at end of frame
1 = inactive 1/2 at start,
full at end of frame */
#define SSP_SSCR1_MWDS (1U << 5)/* Microwire data size:
0 = 8 bit
1 = 16 bit */
#define SSP_SSCR1_TFT (((x) - 1) << 6) /* Tx FIFO threshold */
#define SSP_SSCR1_RFT (((x) - 1) << 10)/* Rx FIFO threshold */
#define SSP_SSCR1_EFWR (1U << 14)/* enab. FIFO write/read */
#define SSP_SSCR1_STRF (1U << 15)/* FIFO write/read FIFO select:
0 = Tx FIFO
1 = Rx FIFO */
#define SSP_SSSR_TNF (1U << 2)/* Tx FIFO not full */
#define SSP_SSSR_RNE (1U << 3)/* Rx FIFO not empty */
#define SSP_SSSR_BSY (1U << 4)/* SSP is busy */
#define SSP_SSSR_TFS (1U << 5)/* Tx FIFO service request */
#define SSP_SSSR_RFS (1U << 6)/* Rx FIFO service request */
#define SSP_SSSR_ROR (1U << 7)/* Rx FIFO overrun */
#define SSP_SSSR_TFL(x) (((x) >> 8) & 0xf) /* Tx FIFO level */
#define SSP_SSSR_RFL(x) (((x) >> 12) & 0xf)/* Rx FIFO level */
#define SSP_SSITR_TTFS (1U << 5)/* Test Tx FIFO service */
#define SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */
#define SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */
/*
* Peripheral Bus Interface Unit
*/
#define PBIU_PBCR 0x00 /* PBIU Control Register */
#define PBIU_PBBAR0 0x08 /* PBIU Base Address Register 0 */
#define PBIU_PBLR0 0x0c /* PBIU Limit Register 0 */
#define PBIU_PBBAR1 0x10 /* PBIU Base Address Register 1 */
#define PBIU_PBLR1 0x14 /* PBIU Limit Register 1 */
#define PBIU_PBBAR2 0x18 /* PBIU Base Address Register 2 */
#define PBIU_PBLR2 0x1c /* PBIU Limit Register 2 */
#define PBIU_PBBAR3 0x20 /* PBIU Base Address Register 3 */
#define PBIU_PBLR3 0x24 /* PBIU Limit Register 3 */
#define PBIU_PBBAR4 0x28 /* PBIU Base Address Register 4 */
#define PBIU_PBLR4 0x2c /* PBIU Limit Register 4 */
#define PBIU_PBBAR5 0x30 /* PBIU Base Address Register 5 */
#define PBIU_PBLR5 0x34 /* PBIU Limit Register 5 */
#define PBIU_DSCR 0x38 /* PBIU Drive Strength Control Reg. */
#define PBIU_MBR0 0x40 /* PBIU Memory-less Boot Reg. 0 */
#define PBIU_MBR1 0x60 /* PBIU Memory-less Boot Reg. 1 */
#define PBIU_MBR2 0x64 /* PBIU Memory-less Boot Reg. 2 */
#define PBIU_PBCR_PBIEN (1 << 0)
#define PBIU_PBCR_PBI100 (1 << 1)
#define PBIU_PBCR_PBI66 (2 << 1)
#define PBIU_PBCR_PBI33 (3 << 1)
#define PBIU_PBCR_PBBEN (1 << 3)
#define PBIU_PBARx_WIDTH8 (0 << 0)
#define PBIU_PBARx_WIDTH16 (1 << 0)
#define PBIU_PBARx_WIDTH32 (2 << 0)
#define PBIU_PBARx_ADWAIT4 (0 << 2)
#define PBIU_PBARx_ADWAIT8 (1 << 2)
#define PBIU_PBARx_ADWAIT12 (2 << 2)
#define PBIU_PBARx_ADWAIT16 (3 << 2)
#define PBIU_PBARx_ADWAIT20 (4 << 2)
#define PBIU_PBARx_RCWAIT1 (0 << 6)
#define PBIU_PBARx_RCWAIT4 (1 << 6)
#define PBIU_PBARx_RCWAIT8 (2 << 6)
#define PBIU_PBARx_RCWAIT12 (3 << 6)
#define PBIU_PBARx_RCWAIT16 (4 << 6)
#define PBIU_PBARx_RCWAIT20 (5 << 6)
#define PBIU_PBARx_FWE (1 << 9)
#define PBIU_BASE_MASK 0xfffff000U
#define PBIU_PBLRx_SIZE(x) (~((x) - 1))
/*
* Messaging Unit
*/
#define MU_IMR0 0x0010 /* MU Inbound Message Register 0 */
#define MU_IMR1 0x0014 /* MU Inbound Message Register 1 */
#define MU_OMR0 0x0018 /* MU Outbound Message Register 0 */
#define MU_OMR1 0x001c /* MU Outbound Message Register 1 */
#define MU_IDR 0x0020 /* MU Inbound Doorbell Register */
#define MU_IISR 0x0024 /* MU Inbound Interrupt Status Reg */
#define MU_IIMR 0x0028 /* MU Inbound Interrupt Mask Reg */
#define MU_ODR 0x002c /* MU Outbound Doorbell Register */
#define MU_OISR 0x0030 /* MU Outbound Interrupt Status Reg */
#define MU_OIMR 0x0034 /* MU Outbound Interrupt Mask Reg */
#define MU_MUCR 0x0050 /* MU Configuration Register */
#define MU_QBAR 0x0054 /* MU Queue Base Address Register */
#define MU_IFHPR 0x0060 /* MU Inbound Free Head Pointer Reg */
#define MU_IFTPR 0x0064 /* MU Inbound Free Tail Pointer Reg */
#define MU_IPHPR 0x0068 /* MU Inbound Post Head Pointer Reg */
#define MU_IPTPR 0x006c /* MU Inbound Post Tail Pointer Reg */
#define MU_OFHPR 0x0070 /* MU Outbound Free Head Pointer Reg */
#define MU_OFTPR 0x0074 /* MU Outbound Free Tail Pointer Reg */
#define MU_OPHPR 0x0078 /* MU Outbound Post Head Pointer Reg */
#define MU_OPTPR 0x007c /* MU Outbound Post Tail Pointer Reg */
#define MU_IAR 0x0080 /* MU Index Address Register */
#define MU_IIMR_IRI (1 << 6) /* Index Register Interrupt */
#define MU_IIMR_OFQFI (1 << 5) /* Outbound Free Queue Full Int. */
#define MU_IIMR_IPQI (1 << 4) /* Inbound Post Queue Interrupt */
#define MU_IIMR_EDI (1 << 3) /* Error Doorbell Interrupt */
#define MU_IIMR_IDI (1 << 2) /* Inbound Doorbell Interrupt */
#define MU_IIMR_IM1I (1 << 1) /* Inbound Message 1 Interrupt */
#define MU_IIMR_IM0I (1 << 0) /* Inbound Message 0 Interrupt */
#endif /* _ARM_XSCALE_I80321REG_H_ */

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/* $NetBSD: i80321var.h,v 1.8 2003/10/06 16:06:06 thorpej Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _ARM_XSCALE_I80321VAR_H_
#define _ARM_XSCALE_I80321VAR_H_
#include <sys/queue.h>
#include <dev/pci/pcivar.h>
/*
* There are roughly 32 interrupt sources.
*/
#define NIRQ 32
extern struct bus_space i80321_bs_tag;
struct i80321_softc {
device_t dev;
bus_space_tag_t sc_st;
bus_space_handle_t sc_sh;
/* Handles for the various subregions. */
bus_space_handle_t sc_atu_sh;
bus_space_handle_t sc_mcu_sh;
int sc_is_host;
/*
* We expect the board-specific front-end to have already mapped
* the PCI I/O space .. it is only 64K, and I/O mappings tend to
* be smaller than a page size, so it's generally more efficient
* to map them all into virtual space in one fell swoop.
*/
vm_offset_t sc_iow_vaddr; /* I/O window vaddr */
/*
* Variables that define the Inbound windows. The base address of
* 0-2 are configured by a host via BARs. The xlate variable
* defines the start of the local address space that it maps to.
* The size variable defines the byte size.
*
* The first 3 windows are for incoming PCI memory read/write
* cycles from a host. The 4th window, not configured by the
* host (as it outside the normal BAR range) is the inbound
* window for PCI devices controlled by the i80321.
*/
struct {
uint32_t iwin_base_hi;
uint32_t iwin_base_lo;
uint32_t iwin_xlate;
uint32_t iwin_size;
} sc_iwin[4];
/*
* Variables that define the Outbound windows.
*/
struct {
uint32_t owin_xlate_lo;
uint32_t owin_xlate_hi;
} sc_owin[2];
/*
* This is the PCI address that the Outbound I/O
* window maps to.
*/
uint32_t sc_ioout_xlate;
/* Bus space, DMA, and PCI tags for the PCI bus (private devices). */
struct bus_space sc_pci_iot;
struct bus_space sc_pci_memt;
/* GPIO state */
uint8_t sc_gpio_dir; /* GPIO pin direction (1 == output) */
uint8_t sc_gpio_val; /* GPIO output pin value */
};
void i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t,
vm_paddr_t *, vm_size_t *);
void i80321_attach(struct i80321_softc *);
void i80321_calibrate_delay(void);
void i80321_bs_init(bus_space_tag_t, void *);
void i80321_io_bs_init(bus_space_tag_t, void *);
void i80321_mem_bs_init(bus_space_tag_t, void *);
#endif /* _ARM_XSCALE_I80321VAR_H_ */

460
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/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* machdep.c
*
* Machine dependant functions for kernel setup
*
* This file needs a lot of work.
*
* Created : 17/09/94
*/
#include "opt_msgbuf.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sysproto.h>
#include <sys/signalvar.h>
#include <sys/imgact.h>
#include <sys/kernel.h>
#include <sys/ktr.h>
#include <sys/linker.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/pcpu.h>
#include <sys/proc.h>
#include <sys/ptrace.h>
#include <sys/cons.h>
#include <sys/bio.h>
#include <sys/bus.h>
#include <sys/buf.h>
#include <sys/exec.h>
#include <sys/kdb.h>
#include <sys/msgbuf.h>
#include <machine/reg.h>
#include <machine/cpu.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm.h>
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_pager.h>
#include <vm/vm_map.h>
#include <vm/vnode_pager.h>
#include <machine/pmap.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
#include <machine/machdep.h>
#include <machine/metadata.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <sys/reboot.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/iq80321reg.h>
#include <arm/xscale/i80321/obiovar.h>
#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
#define KERNEL_PT_KERNEL 1 /* Page table for mapping kernel */
#define KERNEL_PT_KERNEL_NUM 4
/* L2 table for mapping i80321 */
#define KERNEL_PT_IOPXS (KERNEL_PT_KERNEL + KERNEL_PT_KERNEL_NUM)
#define KERNEL_PT_VMDATA (KERNEL_PT_IOPXS + 1)
#define KERNEL_PT_VMDATA_NUM 4
#define NUM_KERNEL_PTS (KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM)
/* Define various stack sizes in pages */
#define IRQ_STACK_SIZE 1
#define ABT_STACK_SIZE 1
#ifdef IPKDB
#define UND_STACK_SIZE 2
#else
#define UND_STACK_SIZE 1
#endif
#define KERNEL_VM_BASE (KERNBASE + 0x00c00000)
#define KERNEL_VM_SIZE 0x05000000
extern u_int data_abort_handler_address;
extern u_int prefetch_abort_handler_address;
extern u_int undefined_handler_address;
struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
extern void *_end;
extern vm_offset_t sa1_cache_clean_addr;
extern int *end;
struct pcpu __pcpu;
struct pcpu *pcpup = &__pcpu;
/* Physical and virtual addresses for some global pages */
vm_paddr_t phys_avail[10];
vm_paddr_t physical_start;
vm_paddr_t physical_end;
vm_offset_t physical_pages;
vm_offset_t clean_sva, clean_eva;
struct pv_addr systempage;
struct pv_addr msgbufpv;
struct pv_addr irqstack;
struct pv_addr undstack;
struct pv_addr abtstack;
struct pv_addr kernelstack;
struct pv_addr minidataclean;
void enable_mmu(vm_offset_t);
static struct trapframe proc0_tf;
#define IQ80321_OBIO_BASE 0xfe800000UL
#define IQ80321_OBIO_SIZE 0x00100000UL
/* Static device mappings. */
static const struct pmap_devmap iq80321_devmap[] = {
/*
* Map the on-board devices VA == PA so that we can access them
* with the MMU on or off.
*/
{
IQ80321_OBIO_BASE,
IQ80321_OBIO_BASE,
IQ80321_OBIO_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
IQ80321_IOW_VBASE,
VERDE_OUT_XLATE_IO_WIN0_BASE,
VERDE_OUT_XLATE_IO_WIN_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
IQ80321_80321_VBASE,
VERDE_PMMR_BASE,
VERDE_PMMR_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
#if 0
{
0x80000000,
0x80000000,
0x08000000,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
#endif
{
0,
0,
0,
0,
0,
}
};
#define SDRAM_START 0xa0000000
void DO_corb(void);
extern vm_offset_t xscale_cache_clean_addr;
void *
initarm(void *arg, void *arg2)
{
struct pcpu *pc;
struct pv_addr kernel_l1pt;
struct pv_addr proc0_uarea;
struct pv_addr altkern[KERNEL_PT_KERNEL_NUM];
int loop;
u_int kerneldatasize, symbolsize;
u_int l1pagetable;
vm_offset_t freemempos;
vm_offset_t afterkern;
int i = 0;
uint32_t fake_preload[35];
uint32_t memsize, memstart;
i80321_calibrate_delay();
cninit();
set_cpufuncs();
/*
* Fetch the SDRAM start/size from the i80321 SDRAM configration
* registers.
*/
i80321_sdram_bounds(&obio_bs_tag, VERDE_PMMR_BASE + VERDE_MCU_BASE,
&memstart, &memsize);
fake_preload[i++] = MODINFO_NAME;
fake_preload[i++] = strlen("elf kernel") + 1;
strcpy((char*)&fake_preload[i++], "elf kernel");
i += 2;
fake_preload[i++] = MODINFO_TYPE;
fake_preload[i++] = strlen("elf kernel") + 1;
strcpy((char*)&fake_preload[i++], "elf kernel");
i += 2;
fake_preload[i++] = MODINFO_ADDR;
fake_preload[i++] = sizeof(vm_offset_t);
fake_preload[i++] = KERNBASE;
fake_preload[i++] = MODINFO_SIZE;
fake_preload[i++] = sizeof(uint32_t);
fake_preload[i++] = (uint32_t)&end - KERNBASE;
fake_preload[i++] = 0;
fake_preload[i] = 0;
preload_metadata = (void *)fake_preload;
physmem = memsize / PAGE_SIZE;
pc = &__pcpu;
pcpu_init(pc, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
physical_start = (vm_offset_t) SDRAM_START;
physical_end = (vm_offset_t) &end + SDRAM_START - 0xc0000000;
afterkern = round_page((vm_offset_t)&end);
#define KERNEL_TEXT_BASE (KERNBASE + 0x00200000)
kerneldatasize = (u_int32_t)&end - (u_int32_t)KERNEL_TEXT_BASE;
symbolsize = 0;
freemempos = 0xa0200000;
/* Define a macro to simplify memory allocation */
#define valloc_pages(var, np) \
alloc_pages((var).pv_pa, (np)); \
(var).pv_va = (var).pv_pa + 0x20000000;
#define alloc_pages(var, np) \
freemempos -= (np * PAGE_SIZE); \
(var) = freemempos; \
memset((char *)(var), 0, ((np) * PAGE_SIZE));
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
freemempos -= PAGE_SIZE;
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
valloc_pages(kernel_pt_table[loop],
L2_TABLE_SIZE / PAGE_SIZE);
}
for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++) {
valloc_pages(altkern[loop], L2_TABLE_SIZE / PAGE_SIZE);
}
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
valloc_pages(systempage, 1);
/* Allocate stacks for all modes */
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, KSTACK_PAGES);
valloc_pages(minidataclean, 1);
valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE);
/*
* Allocate memory for the l1 and l2 page tables. The scheme to avoid
* wasting memory by allocating the l1pt on the first 16k memory was
* taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
* this to work (which is supposed to be the case).
*/
/* Allocate pages for process 0 kernel stack and uarea */
valloc_pages(proc0_uarea, UAREA_PAGES);
/*
* Now we start construction of the L1 page table
* We start by mapping the L2 page tables into the L1.
* This means that we can replace L1 mappings later on if necessary
*/
l1pagetable = kernel_l1pt.pv_pa;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00400000 - 1),
&kernel_pt_table[KERNEL_PT_SYS]);
for (i = 0; i < KERNEL_PT_KERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, KERNBASE + i * 0x00400000,
&kernel_pt_table[KERNEL_PT_KERNEL + i]);
pmap_link_l2pt(l1pagetable, 0xa0000000 + i * 0x00400000,
&altkern[i]);
}
for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; ++loop)
pmap_link_l2pt(l1pagetable, KERNBASE + (KERNEL_PT_KERNEL_NUM + loop) * 0x00400000,
&kernel_pt_table[KERNEL_PT_VMDATA + loop]);
pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE,
&kernel_pt_table[KERNEL_PT_IOPXS]);
pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000,
(((uint32_t)(&end) - KERNBASE - 0x200000) + PAGE_SHIFT) & ~PAGE_SHIFT,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, KERNPHYSADDR, KERNPHYSADDR,
(((uint32_t)(&end) - KERNBASE - 0x200000) + PAGE_SHIFT) & ~PAGE_SHIFT, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
/* Map the stack pages */
pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, proc0_uarea.pv_va, proc0_uarea.pv_pa,
UAREA_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
MSGBUF_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
}
for (loop = 0; loop < 4; loop++) {
pmap_map_chunk(l1pagetable, altkern[loop].pv_va,
altkern[loop].pv_pa, L2_TABLE_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
}
/* Map the Mini-Data cache clean area. */
xscale_setup_minidata(l1pagetable, minidataclean.pv_va,
minidataclean.pv_pa);
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_devmap_bootstrap(l1pagetable, iq80321_devmap);
/*
* Give the XScale global cache clean code an appropriately
* sized chunk of unmapped VA space starting at 0xff000000
* (our device mappings end before this address).
*/
xscale_cache_clean_addr = 0xff000000U;
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
set_stackptr(PSR_IRQ32_MODE,
irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE,
abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_UND32_MODE,
undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross reloations of the kernel thus
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
/* Set stack for exception handlers */
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address = (u_int)undefinedinstruction_bounce;
undefined_init();
proc_linkup(&proc0, &ksegrp0, &thread0);
proc0.p_uarea = (struct user *) proc0_uarea.pv_va;
thread0.td_kstack = kernelstack.pv_va;
thread0.td_pcb = (struct pcb *)
(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
thread0.td_pcb->pcb_flags = 0;
thread0.td_frame = &proc0_tf;
pcpup->pc_curpcb = thread0.td_pcb;
/* Enable MMU, I-cache, D-cache, write buffer. */
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
pmap_curmaxkvaddr = afterkern;
pmap_curmaxkvaddr &= 0xfff00000;
pmap_curmaxkvaddr += 0x00100000;
pmap_bootstrap(pmap_curmaxkvaddr,
0xd0000000, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, MSGBUF_SIZE);
mutex_init();
phys_avail[0] = SDRAM_START;
phys_avail[1] = round_page(freemempos);
phys_avail[2] = round_page(virtual_avail - KERNBASE + SDRAM_START);
phys_avail[3] = trunc_page(0xa0000000 + memsize - 1);
phys_avail[4] = 0;
phys_avail[5] = 0;
/* Do basic tuning, hz etc */
init_param1();
init_param2(physmem);
avail_end = 0xa0000000 + memsize - 1;
kdb_init();
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP));
}

328
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/* $NetBSD: i80321_mainbus.c,v 1.13 2003/12/17 22:03:24 abs Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* IQ80321 front-end for the i80321 I/O Processor. We take care
* of setting up the i80321 memory map, PCI interrupt routing, etc.,
* which are all specific to the board the i80321 is wired up to.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/malloc.h>
#define __RMAN_RESOURCE_VISIBLE
#include <sys/rman.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/iq80321reg.h>
#include <arm/xscale/i80321/iq80321var.h>
#include <arm/xscale/i80321/i80321_intr.h>
#include <dev/pci/pcireg.h>
int iq80321_probe(device_t);
void iq80321_identify(driver_t *, device_t);
int iq80321_attach(device_t);
int
iq80321_probe(device_t dev)
{
device_set_desc(dev, "Intel 80321");
return (0);
}
void
iq80321_identify(driver_t *driver, device_t parent)
{
BUS_ADD_CHILD(parent, 0, "iq", 0);
}
static struct arm32_dma_range i80321_dr;
static int dma_range_init = 0;
struct arm32_dma_range *
bus_dma_get_range(void)
{
if (dma_range_init == 0)
return (NULL);
return (&i80321_dr);
}
int
bus_dma_get_range_nb(void)
{
if (dma_range_init == 0)
return (0);
return (1);
}
#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
void pmap_kenter(vm_offset_t, vm_offset_t);
int
iq80321_attach(device_t dev)
{
struct i80321_softc *sc = device_get_softc(dev);
int b0u, b0l, b1u, b1l;
vm_paddr_t memstart = 0;
vm_size_t memsize = 0;
int busno;
/*
* Fill in the space tag for the i80321's own devices,
* and hand-craft the space handle for it (the device
* was mapped during early bootstrap).
*/
i80321_bs_init(&i80321_bs_tag, sc);
sc->sc_st = &i80321_bs_tag;
sc->sc_sh = IQ80321_80321_VBASE;
sc->dev = dev;
sc->sc_is_host = 1;
/*
* Slice off a subregion for the Memory Controller -- we need it
* here in order read the memory size.
*/
if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE,
VERDE_MCU_SIZE, &sc->sc_mcu_sh))
panic("%s: unable to subregion MCU registers",
device_get_name(dev));
if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE,
VERDE_ATU_SIZE, &sc->sc_atu_sh))
panic("%s: unable to subregion ATU registers",
device_get_name(dev));
/*
* We have mapped the the PCI I/O windows in the early
* bootstrap phase.
*/
sc->sc_iow_vaddr = IQ80321_IOW_VBASE;
/*
* Check the configuration of the ATU to see if another BIOS
* has configured us. If a PC BIOS didn't configure us, then:
* IQ80321: BAR0 00000000.0000000c BAR1 is 00000000.8000000c.
* IQ31244: BAR0 00000000.00000004 BAR1 is 00000000.0000000c.
* If a BIOS has configured us, at least one of those should be
* different. This is pretty fragile, but it's not clear what
* would work better.
*/
b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_MAPS+0x0);
b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_MAPS+0x4);
b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_MAPS+0x8);
b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_MAPS+0xc);
#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
b0l &= PCI_MAPREG_MEM_ADDR_MASK;
b0u &= PCI_MAPREG_MEM_ADDR_MASK;
b1l &= PCI_MAPREG_MEM_ADDR_MASK;
b1u &= PCI_MAPREG_MEM_ADDR_MASK;
if ((b0u != b1u) || (b0l != 0) || ((b1l & ~0x80000000U) != 0))
sc->sc_is_host = 0;
else
sc->sc_is_host = 1;
i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize);
/*
* We set up the Inbound Windows as follows:
*
* 0 Access to i80321 PMMRs
*
* 1 Reserve space for private devices
*
* 2 RAM access
*
* 3 Unused.
*
* This chunk needs to be customized for each IOP321 application.
*/
#if 0
sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE;
sc->sc_iwin[0].iwin_base_hi = 0;
sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE;
sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE;
#endif
if (sc->sc_is_host) {
/* Map PCI:Local 1:1. */
sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
PCI_MAPREG_MEM_PREFETCHABLE_MASK |
PCI_MAPREG_MEM_TYPE_64BIT;
sc->sc_iwin[1].iwin_base_hi = 0;
} else {
sc->sc_iwin[1].iwin_base_lo = 0;
sc->sc_iwin[1].iwin_base_hi = 0;
}
sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
if (sc->sc_is_host) {
sc->sc_iwin[2].iwin_base_lo = memstart |
PCI_MAPREG_MEM_PREFETCHABLE_MASK |
PCI_MAPREG_MEM_TYPE_64BIT;
sc->sc_iwin[2].iwin_base_hi = 0;
} else {
sc->sc_iwin[2].iwin_base_lo = 0;
sc->sc_iwin[2].iwin_base_hi = 0;
}
sc->sc_iwin[2].iwin_xlate = memstart;
sc->sc_iwin[2].iwin_size = memsize;
if (sc->sc_is_host) {
sc->sc_iwin[3].iwin_base_lo = 0 |
PCI_MAPREG_MEM_PREFETCHABLE_MASK |
PCI_MAPREG_MEM_TYPE_64BIT;
} else {
sc->sc_iwin[3].iwin_base_lo = 0;
}
sc->sc_iwin[3].iwin_base_hi = 0;
sc->sc_iwin[3].iwin_xlate = 0;
sc->sc_iwin[3].iwin_size = 0;
/*
* We set up the Outbound Windows as follows:
*
* 0 Access to private PCI space.
*
* 1 Unused.
*/
#define PCI_MAPREG_MEM_ADDR(x) ((x) & 0xfffffff0)
sc->sc_owin[0].owin_xlate_lo =
PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
/*
* Set the Secondary Outbound I/O window to map
* to PCI address 0 for all 64K of the I/O space.
*/
sc->sc_ioout_xlate = 0;
i80321_attach(sc);
i80321_dr.dr_sysbase = sc->sc_iwin[2].iwin_xlate;
i80321_dr.dr_busbase = PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo);
i80321_dr.dr_len = sc->sc_iwin[2].iwin_size;
dma_range_init = 1;
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
device_add_child(dev, "obio", 0);
device_add_child(dev, "itimer", 0);
device_add_child(dev, "pcib", busno);
bus_generic_probe(dev);
bus_generic_attach(dev);
return (0);
}
void
arm_mask_irqs(int nb)
{
intr_enabled &= ~nb;
i80321_set_intrmask();
}
void
arm_unmask_irqs(int nb)
{
intr_enabled |= nb;
i80321_set_intrmask();
}
void
cpu_reset()
{
(void) disable_interrupts(I32_bit|F32_bit);
*(__volatile uint32_t *)(IQ80321_80321_VBASE + VERDE_ATU_BASE +
ATU_PCSR) = PCSR_RIB | PCSR_RPB;
printf("Reset failed :'(\n");
for(;;);
}
static struct resource *
iq80321_alloc_resource(device_t dev, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags)
{
if (type == SYS_RES_IRQ) {
struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK);
res->r_start = start;
res->r_end = end;
return (res);
}
return (NULL);
}
static int
iq80321_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_intr_t *intr, void *arg,
void **cookiep)
{
BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, intr, arg,
cookiep);
intr_enabled |= 1 << ires->r_start;
i80321_set_intrmask();
return (0);
}
static device_method_t iq80321_methods[] = {
DEVMETHOD(device_probe, iq80321_probe),
DEVMETHOD(device_attach, iq80321_attach),
DEVMETHOD(device_identify, iq80321_identify),
DEVMETHOD(bus_alloc_resource, iq80321_alloc_resource),
DEVMETHOD(bus_setup_intr, iq80321_setup_intr),
{0, 0},
};
static driver_t iq80321_driver = {
"iq",
iq80321_methods,
sizeof(struct i80321_softc),
};
static devclass_t iq80321_devclass;
DRIVER_MODULE(iq, nexus, iq80321_driver, iq80321_devclass, 0, 0);

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/* $NetBSD: iq80321reg.h,v 1.4 2003/05/14 19:46:39 thorpej Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _IQ80321REG_H_
#define _IQ80321REG_H_
/*
* Memory map and register definitions for the Intel IQ80321
* Evaluation Board.
*/
/*
* The memory map of the IQ80321 looks like so:
*
* ------------------------------
* Intel 80321 IOP Reserved
* FFFF E900 ------------------------------
* Peripheral Memory Mapped
* Registers
* FFFF E000 ------------------------------
* On-board devices
* FE80 0000 ------------------------------
* SDRAM
* A000 0000 ------------------------------
* Reserved
* 9100 0000 ------------------------------
* Flash
* 9080 0000 ------------------------------
* Reserved
* 9002 0000 ------------------------------
* ATU Outbound Transaction
* Windows
* 8000 0000 ------------------------------
* ATU Outbound Direct
* Addressing Windows
* 0000 1000 ------------------------------
* Initialization Boot Code
* from Flash
* 0000 0000 ------------------------------
*/
/*
* We allocate a page table for VA 0xfe400000 (4MB) and map the
* PCI I/O space (64K) and i80321 memory-mapped registers (4K) there.
*/
#define IQ80321_IOPXS_VBASE 0xfe400000UL
#define IQ80321_IOW_VBASE IQ80321_IOPXS_VBASE
#define IQ80321_80321_VBASE (IQ80321_IOW_VBASE + \
VERDE_OUT_XLATE_IO_WIN_SIZE)
/*
* The IQ80321 on-board devices are mapped VA==PA during bootstrap.
* Conveniently, the size of the on-board register space is 1 section
* mapping.
*/
#define IQ80321_OBIO_BASE 0xfe800000UL
#define IQ80321_OBIO_SIZE 0x00100000UL /* 1MB */
#define IQ80321_UART1 0xfe800000UL /* TI 16550 */
#define IQ80321_7SEG_MSB 0xfe840000UL
#define IQ80321_7SEG_LSB 0xfe850000UL
#define IQ80321_ROT_SWITCH 0xfe8d0000UL
#define IQ80321_BATTERY_STAT 0xfe8f0000UL
#define BATTERY_STAT_PRES (1U << 0)
#define BATTERY_STAT_CHRG (1U << 1)
#define BATTERY_STAT_DISCHRG (1U << 2)
#endif /* _IQ80321REG_H_ */

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/* $NetBSD: iq80321var.h,v 1.1 2002/03/27 21:51:30 thorpej Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _IQ80321_IQ80321VAR_H_
#define _IQ80321_IQ80321VAR_H_
#include <dev/pci/pcivar.h>
void iq80321_7seg(char, char);
void iq80321_7seg_snake(void);
#if 0
void iq80321_pci_init(pci_chipset_tag_t, void *);
#endif
#endif /* _IQ80321_IQ80321VAR_H_ */

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/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */
/*
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* On-board device autoconfiguration support for Intel IQ80321
* evaluation boards.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#define __RMAN_RESOURCE_VISIBLE
#include <sys/rman.h>
#include <sys/malloc.h>
#include <machine/bus.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/iq80321reg.h>
#include <arm/xscale/i80321/obiovar.h>
int obio_probe(device_t);
int obio_attach(device_t);
int
obio_probe(device_t dev)
{
return (0);
}
int
obio_attach(device_t dev)
{
struct obio_softc *sc = device_get_softc(dev);
sc->oba_st = &obio_bs_tag;
sc->oba_addr = IQ80321_OBIO_BASE;
sc->oba_size = IQ80321_OBIO_SIZE;
sc->oba_rman.rm_type = RMAN_ARRAY;
sc->oba_rman.rm_descr = "OBIO I/O";
if (rman_init(&sc->oba_rman) != 0 ||
rman_manage_region(&sc->oba_rman,
sc->oba_addr, sc->oba_addr + sc->oba_size) != 0)
panic("obio_attach: failed to set up I/O rman");
device_add_child(dev, "uart", 0);
bus_generic_probe(dev);
bus_generic_attach(dev);
return (0);
}
static struct resource *
obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags)
{
struct resource *rv;
struct rman *rm;
bus_space_tag_t bt;
bus_space_handle_t bh;
struct obio_softc *sc = device_get_softc(bus);
if (type == SYS_RES_IRQ) {
rv = malloc(sizeof(*rv), M_DEVBUF, M_WAITOK);
rv->r_start = 28;
rv->r_end = 28;
rv->r_rid = *rid;
return (rv);
}
switch (type) {
case SYS_RES_MEMORY:
return (NULL);
case SYS_RES_IOPORT:
rm = &sc->oba_rman;
bt = sc->oba_st;
bh = sc->oba_addr;
break;
default:
return (NULL);
}
start = bh;
rv = rman_reserve_resource(rm, start, end, count, flags, child);
if (rv == NULL)
return (NULL);
rman_set_bustag(rv, bt);
rman_set_bushandle(rv, bh);
if (0) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
return (rv);
}
static int
obio_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
return (0);
}
static device_method_t obio_methods[] = {
DEVMETHOD(device_probe, obio_probe),
DEVMETHOD(device_attach, obio_attach),
DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
DEVMETHOD(bus_activate_resource, obio_activate_resource),
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
{0, 0},
};
static driver_t obio_driver = {
"obio",
obio_methods,
sizeof(struct obio_softc),
};
static devclass_t obio_devclass;
DRIVER_MODULE(obio, iq, obio_driver, obio_devclass, 0, 0);

226
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/* $NetBSD: obio_space.c,v 1.6 2003/07/15 00:25:05 lukem Exp $ */
/*
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* bus_space functions for IQ80321 on-board devices
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <machine/pcb.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_kern.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
/* Prototypes for all the bus_space structure functions */
bs_protos(obio);
bs_protos(generic);
bs_protos(generic_armv4);
/*
* The obio bus space tag. This is constant for all instances, so
* we never have to explicitly "create" it.
*/
struct bus_space obio_bs_tag = {
/* cookie */
(void *) 0,
/* mapping/unmapping */
obio_bs_map,
obio_bs_unmap,
obio_bs_subregion,
/* allocation/deallocation */
obio_bs_alloc,
obio_bs_free,
/* barrier */
obio_bs_barrier,
/* read (single) */
generic_bs_r_1,
generic_armv4_bs_r_2,
generic_bs_r_4,
NULL,
/* read multiple */
generic_bs_rm_1,
NULL,
NULL,
NULL,
/* read region */
generic_bs_rr_1,
NULL,
NULL,
NULL,
/* write (single) */
generic_bs_w_1,
generic_armv4_bs_w_2,
generic_bs_w_4,
NULL,
/* write multiple */
generic_bs_wm_1,
NULL,
NULL,
NULL,
/* write region */
NULL,
NULL,
NULL,
NULL,
/* set multiple */
NULL,
NULL,
NULL,
NULL,
/* set region */
NULL,
NULL,
NULL,
NULL,
/* copy */
NULL,
NULL,
NULL,
NULL,
};
int
obio_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
bus_space_handle_t *bshp)
{
const struct pmap_devmap *pd;
vm_paddr_t startpa, endpa, pa, offset;
vm_offset_t va;
pt_entry_t *pte;
if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) {
/* Device was statically mapped. */
*bshp = pd->pd_va + (bpa - pd->pd_pa);
return (0);
}
endpa = round_page(bpa + size);
offset = bpa & PAGE_MASK;
startpa = trunc_page(bpa);
va = kmem_alloc(kernel_map, endpa - startpa);
if (va == 0)
return (ENOMEM);
*bshp = va + offset;
for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
pmap_kenter(va, pa);
pte = vtopte(va);
*pte &= ~L2_S_CACHE_MASK;
PTE_SYNC(pte);
}
pmap_update(pmap_kernel());
return (0);
}
int
obio_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, bus_size_t size,
bus_size_t alignment, bus_size_t boundary, int flags, bus_addr_t *bpap,
bus_space_handle_t *bshp)
{
panic("obio_bs_alloc(): not implemented");
}
void
obio_bs_unmap(void *t, bus_size_t size)
{
vm_offset_t va, endva;
if (pmap_devmap_find_va((vm_offset_t)t, size) != NULL) {
/* Device was statically mapped; nothing to do. */
return;
}
endva = round_page((vm_offset_t)t + size);
va = trunc_page((vm_offset_t)t);
while (va < endva) {
pmap_kremove(va);
va += PAGE_SIZE;
}
kmem_free(kernel_map, va, endva - va);
}
void
obio_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{
panic("obio_bs_free(): not implemented");
}
int
obio_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t size, bus_space_handle_t *nbshp)
{
*nbshp = bsh + offset;
return (0);
}
void
obio_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t len, int flags)
{
/* Nothing to do. */
}

57
sys/arm/xscale/i80321/obiovar.h Normal file
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/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _IQ80321_OBIOVAR_H_
#define _IQ80321_OBIOVAR_H_
#ifdef __RMAN_RESOURCE_VISIBLE
struct obio_softc {
bus_space_tag_t oba_st; /* bus space tag */
bus_addr_t oba_addr; /* address of device */
bus_size_t oba_size; /* size of device */
int oba_width; /* bus width */
int oba_irq; /* XINT interrupt bit # */
struct rman oba_rman;
};
#endif /* __RMAN_RESOURCE_VISIBLE */
extern struct bus_space obio_bs_tag;
#endif /* _IQ80321_OBIOVAR_H_ */

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sys/arm/xscale/i80321/std.i80321 Normal file
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#XScale i80321 generic configuration
#$FreeBSD$
files "../xscale/i80321/files.i80321"
cpu CPU_XSCALE_80321
makeoptions KERNPHYSADDR=0x00200000
makeoptions KERNVIRTADDR=0xc0200000

4
sys/arm/xscale/i80321/std.iq31244 Normal file
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#IQ31244 board configuration
#$FreeBSD$
include "../xscale/i80321/std.i80321"
files "../xscale/i80321/files.iq31244"

77
sys/arm/xscale/i80321/uart_bus_i80321.c Normal file
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/*
* Copyright (c) 2004 Olivier Houchard. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h>
#include <dev/pci/pcivar.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_cpu.h>
#include "uart_if.h"
static int uart_i80321_probe(device_t dev);
static device_method_t uart_i80321_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, uart_i80321_probe),
DEVMETHOD(device_attach, uart_bus_attach),
DEVMETHOD(device_detach, uart_bus_detach),
{ 0, 0 }
};
static driver_t uart_i80321_driver = {
uart_driver_name,
uart_i80321_methods,
sizeof(struct uart_softc),
};
extern struct uart_class uart_i8251_class;
extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
static int
uart_i80321_probe(device_t dev)
{
struct uart_softc *sc;
sc = device_get_softc(dev);
sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
sc->sc_class = &uart_i8251_class;
bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
return(uart_bus_probe(dev, 0, 0, 0, 0));
}
DRIVER_MODULE(uart, obio, uart_i80321_driver, uart_devclass, 0, 0);

74
sys/arm/xscale/i80321/uart_cpu_i80321.c Normal file
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/*
* Copyright (c) 2003 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/cons.h>
#include <machine/bus.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_cpu.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/obiovar.h>
bus_space_tag_t uart_bus_space_io;
bus_space_tag_t uart_bus_space_mem;
int
uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
{
return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
}
extern int got_mmu;
void
DO_corb(void);
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
di->ops = uart_i8251_ops;
di->bas.chan = 0;
di->bas.bst = &obio_bs_tag;
di->bas.regshft = 0;
di->bas.rclk = 0;
di->baudrate = 115200;
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
uart_bus_space_io = &obio_bs_tag;
uart_bus_space_mem = NULL;
#if 0
bus_space_map(di->bas.bst, 0xfe800000, 8, 0, &di->bas.bsh);
#endif
di->bas.bsh = 0xfe800000;
return (0);
}