diff --git a/sys/dev/agp/agp_intel.c b/sys/dev/agp/agp_intel.c
index 2166b2f59140..42c8b0d8bb90 100644
--- a/sys/dev/agp/agp_intel.c
+++ b/sys/dev/agp/agp_intel.c
@@ -157,15 +157,8 @@ agp_intel_commit_gatt(device_t dev)
 		pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
 	}
 
-	/* Enable things, clear errors etc. */
+	/* Enable aperture accesses. */
 	switch (type) {
-	case 0x1a218086: /* i840 */
-	case 0x25308086: /* i850 */
-	case 0x25318086: /* i860 */
-		pci_write_config(dev, AGP_INTEL_MCHCFG,
-				 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
-				  | (1 << 9)), 2);
-		break;
 	case 0x25008086: /* i820 */
 	case 0x25018086: /* i820 */
 		pci_write_config(dev, AGP_INTEL_I820_RDCR,
@@ -173,23 +166,31 @@ agp_intel_commit_gatt(device_t dev)
 				  | (1 << 1)), 1);
 		break;
 	case 0x1a308086: /* i845 */
+	case 0x25608086: /* i845G */
 	case 0x33408086: /* i855 */
 	case 0x35808086: /* i855GM */
-	case 0x255d8086: /* E7205 */
-	case 0x25508086: /* E7505 */
 	case 0x25708086: /* i865 */
 	case 0x25788086: /* i875P */
-	case 0x25608086: /* i845G */
-		pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
-				 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
+		pci_write_config(dev, AGP_INTEL_I845_AGPM,
+				 (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1)
 				  | (1 << 1)), 1);
 		break;
+	case 0x1a218086: /* i840 */
+	case 0x25308086: /* i850 */
+	case 0x25318086: /* i860 */
+	case 0x255d8086: /* E7205 */
+	case 0x25508086: /* E7505 */
+		pci_write_config(dev, AGP_INTEL_MCHCFG,
+				 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
+				  | (1 << 9)), 2);
+		break;
 	default: /* Intel Generic (maybe) */
 		pci_write_config(dev, AGP_INTEL_NBXCFG,
 				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
 				  & ~(1 << 10)) | (1 << 9), 4);
 	}
 
+	/* Clear errors. */
 	switch (type) {
 	case 0x1a218086: /* i840 */
 		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
@@ -197,14 +198,14 @@ agp_intel_commit_gatt(device_t dev)
 	case 0x25008086: /* i820 */
 	case 0x25018086: /* i820 */
 	case 0x1a308086: /* i845 */
+	case 0x25608086: /* i845G */
 	case 0x25308086: /* i850 */
 	case 0x33408086: /* i855 */
-	case 0x255d8086: /* E7205 */
-	case 0x25508086: /* E7505 */
 	case 0x25318086: /* i860 */
 	case 0x25708086: /* i865 */
 	case 0x25788086: /* i875P */
-	case 0x25608086: /* i845G */
+	case 0x255d8086: /* E7205 */
+	case 0x25508086: /* E7505 */
 		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
 		break;
 	default: /* Intel Generic (maybe) */
@@ -259,6 +260,7 @@ static int
 agp_intel_detach(device_t dev)
 {
 	struct agp_intel_softc *sc;
+	u_int32_t reg;
 	int error;
 
 	sc = device_get_softc(dev);
@@ -267,48 +269,37 @@ agp_intel_detach(device_t dev)
 	if (error)
 		return (error);
 
+	/* Disable aperture accesses. */
 	switch (pci_get_devid(dev)) {
-	case 0x1a218086: /* i840 */
-	case 0x25308086: /* i850 */
-	case 0x25318086: /* i860 */
-		printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
-				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
-				& ~(1 << 9)));
-		pci_write_config(dev, AGP_INTEL_MCHCFG,
-				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
-				& ~(1 << 9)), 2);
-		/* FALLTHRU */
 	case 0x25008086: /* i820 */
 	case 0x25018086: /* i820 */
-		printf("%s: set RDCR to %x\n", __func__, (unsigned)
-				(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
-				& ~(1 << 1)));
-		pci_write_config(dev, AGP_INTEL_I820_RDCR,
-				(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
-				& ~(1 << 1)), 1);
-		/* FALLTHRU */
+		reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1);
+		printf("%s: set RDCR to %02x\n", __func__, reg & 0xff);
+		pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1);
+		break;
 	case 0x1a308086: /* i845 */
 	case 0x25608086: /* i845G */
 	case 0x33408086: /* i855 */
 	case 0x35808086: /* i855GM */
-	case 0x255d8086: /* E7205 */
-	case 0x25508086: /* E7505 */
 	case 0x25708086: /* i865 */
 	case 0x25788086: /* i875P */
-		printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
-				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
-				& ~(1 << 1)));
-		pci_write_config(dev, AGP_INTEL_MCHCFG,
-				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
-				& ~(1 << 1)), 1);
-		/* FALLTHRU */
+		reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1);
+		printf("%s: set AGPM to %02x\n", __func__, reg & 0xff);
+		pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1);
+		break;
+	case 0x1a218086: /* i840 */
+	case 0x25308086: /* i850 */
+	case 0x25318086: /* i860 */
+	case 0x255d8086: /* E7205 */
+	case 0x25508086: /* E7505 */
+		reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9);
+		printf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff);
+		pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2);
+		break;
 	default: /* Intel Generic (maybe) */
-		printf("%s: set NBXCFG to %x\n", __func__,
-				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
-				  & ~(1 << 9)));
-		pci_write_config(dev, AGP_INTEL_NBXCFG,
-				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
-				  & ~(1 << 9)), 4);
+		reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9);
+		printf("%s: set NBXCFG to %08x\n", __func__, reg);
+		pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4);
 	}
 	pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
 	AGP_SET_APERTURE(dev, sc->initial_aperture);
diff --git a/sys/dev/agp/agpreg.h b/sys/dev/agp/agpreg.h
index 7786efe5fa52..1914dc4923cd 100644
--- a/sys/dev/agp/agpreg.h
+++ b/sys/dev/agp/agpreg.h
@@ -73,11 +73,11 @@
 #define AGP_INTEL_ATTBASE	0xb8
 
 /*
- * Config offsets for Intel i820/i840/i845/i850/i860/i865 AGP chipsets.
+ * Config offsets for Intel i8xx/E7xxx AGP chipsets.
  */
 #define AGP_INTEL_MCHCFG	0x50
 #define AGP_INTEL_I820_RDCR	0x51
-#define AGP_INTEL_I845_MCHCFG	0x51
+#define AGP_INTEL_I845_AGPM	0x51
 #define AGP_INTEL_I8XX_ERRSTS	0xc8
 
 /*
diff --git a/sys/pci/agp_intel.c b/sys/pci/agp_intel.c
index 2166b2f59140..42c8b0d8bb90 100644
--- a/sys/pci/agp_intel.c
+++ b/sys/pci/agp_intel.c
@@ -157,15 +157,8 @@ agp_intel_commit_gatt(device_t dev)
 		pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
 	}
 
-	/* Enable things, clear errors etc. */
+	/* Enable aperture accesses. */
 	switch (type) {
-	case 0x1a218086: /* i840 */
-	case 0x25308086: /* i850 */
-	case 0x25318086: /* i860 */
-		pci_write_config(dev, AGP_INTEL_MCHCFG,
-				 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
-				  | (1 << 9)), 2);
-		break;
 	case 0x25008086: /* i820 */
 	case 0x25018086: /* i820 */
 		pci_write_config(dev, AGP_INTEL_I820_RDCR,
@@ -173,23 +166,31 @@ agp_intel_commit_gatt(device_t dev)
 				  | (1 << 1)), 1);
 		break;
 	case 0x1a308086: /* i845 */
+	case 0x25608086: /* i845G */
 	case 0x33408086: /* i855 */
 	case 0x35808086: /* i855GM */
-	case 0x255d8086: /* E7205 */
-	case 0x25508086: /* E7505 */
 	case 0x25708086: /* i865 */
 	case 0x25788086: /* i875P */
-	case 0x25608086: /* i845G */
-		pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
-				 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
+		pci_write_config(dev, AGP_INTEL_I845_AGPM,
+				 (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1)
 				  | (1 << 1)), 1);
 		break;
+	case 0x1a218086: /* i840 */
+	case 0x25308086: /* i850 */
+	case 0x25318086: /* i860 */
+	case 0x255d8086: /* E7205 */
+	case 0x25508086: /* E7505 */
+		pci_write_config(dev, AGP_INTEL_MCHCFG,
+				 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
+				  | (1 << 9)), 2);
+		break;
 	default: /* Intel Generic (maybe) */
 		pci_write_config(dev, AGP_INTEL_NBXCFG,
 				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
 				  & ~(1 << 10)) | (1 << 9), 4);
 	}
 
+	/* Clear errors. */
 	switch (type) {
 	case 0x1a218086: /* i840 */
 		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
@@ -197,14 +198,14 @@ agp_intel_commit_gatt(device_t dev)
 	case 0x25008086: /* i820 */
 	case 0x25018086: /* i820 */
 	case 0x1a308086: /* i845 */
+	case 0x25608086: /* i845G */
 	case 0x25308086: /* i850 */
 	case 0x33408086: /* i855 */
-	case 0x255d8086: /* E7205 */
-	case 0x25508086: /* E7505 */
 	case 0x25318086: /* i860 */
 	case 0x25708086: /* i865 */
 	case 0x25788086: /* i875P */
-	case 0x25608086: /* i845G */
+	case 0x255d8086: /* E7205 */
+	case 0x25508086: /* E7505 */
 		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
 		break;
 	default: /* Intel Generic (maybe) */
@@ -259,6 +260,7 @@ static int
 agp_intel_detach(device_t dev)
 {
 	struct agp_intel_softc *sc;
+	u_int32_t reg;
 	int error;
 
 	sc = device_get_softc(dev);
@@ -267,48 +269,37 @@ agp_intel_detach(device_t dev)
 	if (error)
 		return (error);
 
+	/* Disable aperture accesses. */
 	switch (pci_get_devid(dev)) {
-	case 0x1a218086: /* i840 */
-	case 0x25308086: /* i850 */
-	case 0x25318086: /* i860 */
-		printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
-				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
-				& ~(1 << 9)));
-		pci_write_config(dev, AGP_INTEL_MCHCFG,
-				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
-				& ~(1 << 9)), 2);
-		/* FALLTHRU */
 	case 0x25008086: /* i820 */
 	case 0x25018086: /* i820 */
-		printf("%s: set RDCR to %x\n", __func__, (unsigned)
-				(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
-				& ~(1 << 1)));
-		pci_write_config(dev, AGP_INTEL_I820_RDCR,
-				(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
-				& ~(1 << 1)), 1);
-		/* FALLTHRU */
+		reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1);
+		printf("%s: set RDCR to %02x\n", __func__, reg & 0xff);
+		pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1);
+		break;
 	case 0x1a308086: /* i845 */
 	case 0x25608086: /* i845G */
 	case 0x33408086: /* i855 */
 	case 0x35808086: /* i855GM */
-	case 0x255d8086: /* E7205 */
-	case 0x25508086: /* E7505 */
 	case 0x25708086: /* i865 */
 	case 0x25788086: /* i875P */
-		printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
-				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
-				& ~(1 << 1)));
-		pci_write_config(dev, AGP_INTEL_MCHCFG,
-				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
-				& ~(1 << 1)), 1);
-		/* FALLTHRU */
+		reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1);
+		printf("%s: set AGPM to %02x\n", __func__, reg & 0xff);
+		pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1);
+		break;
+	case 0x1a218086: /* i840 */
+	case 0x25308086: /* i850 */
+	case 0x25318086: /* i860 */
+	case 0x255d8086: /* E7205 */
+	case 0x25508086: /* E7505 */
+		reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9);
+		printf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff);
+		pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2);
+		break;
 	default: /* Intel Generic (maybe) */
-		printf("%s: set NBXCFG to %x\n", __func__,
-				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
-				  & ~(1 << 9)));
-		pci_write_config(dev, AGP_INTEL_NBXCFG,
-				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
-				  & ~(1 << 9)), 4);
+		reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9);
+		printf("%s: set NBXCFG to %08x\n", __func__, reg);
+		pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4);
 	}
 	pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
 	AGP_SET_APERTURE(dev, sc->initial_aperture);
diff --git a/sys/pci/agpreg.h b/sys/pci/agpreg.h
index 7786efe5fa52..1914dc4923cd 100644
--- a/sys/pci/agpreg.h
+++ b/sys/pci/agpreg.h
@@ -73,11 +73,11 @@
 #define AGP_INTEL_ATTBASE	0xb8
 
 /*
- * Config offsets for Intel i820/i840/i845/i850/i860/i865 AGP chipsets.
+ * Config offsets for Intel i8xx/E7xxx AGP chipsets.
  */
 #define AGP_INTEL_MCHCFG	0x50
 #define AGP_INTEL_I820_RDCR	0x51
-#define AGP_INTEL_I845_MCHCFG	0x51
+#define AGP_INTEL_I845_AGPM	0x51
 #define AGP_INTEL_I8XX_ERRSTS	0xc8
 
 /*