o) Program the Lanner MR-320 for 32-bit mode, too.
o) Give a virtual address for I/O ports on n64. o) On the Portwell CAM-0100, return the right IRQ for the on-board SATA. o) Except on bridges, only set PORTEN and MEMEN on devices that have I/O or memory BARs respectively. o) Disable PORTEN and MEMEN while reprogramming BARs. o) On the Lanner MR-955, set the Tx DMA power register for the on-board Promise SATA controller.
This commit is contained in:
Juli Mallett
parent
9e1bef6f31
commit
a71199dab4
@ -92,7 +92,7 @@ static void octopci_write_config(device_t, u_int, u_int, u_int, u_int,
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uint32_t, int);
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static int octopci_route_interrupt(device_t, device_t, int);
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static void octopci_init_bar(device_t, unsigned, unsigned, unsigned, unsigned);
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static void octopci_init_bar(device_t, unsigned, unsigned, unsigned, unsigned, uint8_t *);
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static unsigned octopci_init_device(device_t, unsigned, unsigned, unsigned, unsigned);
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static unsigned octopci_init_bus(device_t, unsigned);
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static uint64_t octopci_cs_addr(unsigned, unsigned, unsigned, unsigned);
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@ -148,6 +148,7 @@ octopci_attach(device_t dev)
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*/
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switch (cvmx_sysinfo_get()->board_type) {
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#if defined(OCTEON_VENDOR_LANNER)
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case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
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case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
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/* 32-bit PCI-X */
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cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x0);
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@ -422,14 +423,14 @@ octopci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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break;
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case SYS_RES_IOPORT:
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rman_set_bushandle(res, CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_PCI, CVMX_OCT_SUBDID_PCI_IO)) + rman_get_start(res));
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#if __mips_n64
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rman_set_virtual(res, (void *)rman_get_bushandle(res));
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#else
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/*
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* XXX
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* We should just disallow use of io ports on !n64 since without
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* 64-bit PTEs we can't even do a 32-bit virtual address
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* mapped to them.
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* We can't access ports via a 32-bit pointer.
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*/
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#if 0
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rman_set_virtual(res, (void *)rman_get_bushandle(res));
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rman_set_virtual(res, NULL);
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#endif
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break;
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}
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@ -549,8 +550,19 @@ octopci_route_interrupt(device_t dev, device_t child, int pin)
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slot = pci_get_slot(child);
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func = pci_get_function(child);
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#if defined(OCTEON_VENDOR_LANNER)
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/*
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* Board types we have to know at compile-time.
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*/
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#if defined(OCTEON_BOARD_CAPK_0100ND)
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if (bus == 0 && slot == 12 && func == 0)
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return (CVMX_IRQ_PCI_INT2);
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#endif
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/*
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* For board types we can determine at runtime.
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*/
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switch (cvmx_sysinfo_get()->board_type) {
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#if defined(OCTEON_VENDOR_LANNER)
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case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
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return (CVMX_IRQ_PCI_INT0 + pin - 1);
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case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
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@ -562,10 +574,10 @@ octopci_route_interrupt(device_t dev, device_t child, int pin)
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return (CVMX_IRQ_PCI_INT0 + (irq & 3));
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}
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break;
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#endif
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default:
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break;
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}
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#endif
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irq = slot + pin - 3;
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@ -573,7 +585,7 @@ octopci_route_interrupt(device_t dev, device_t child, int pin)
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}
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static void
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octopci_init_bar(device_t dev, unsigned b, unsigned s, unsigned f, unsigned barnum)
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octopci_init_bar(device_t dev, unsigned b, unsigned s, unsigned f, unsigned barnum, uint8_t *commandp)
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{
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struct octopci_softc *sc;
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uint32_t bar;
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@ -603,6 +615,11 @@ octopci_init_bar(device_t dev, unsigned b, unsigned s, unsigned f, unsigned barn
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octopci_write_config(dev, b, s, f, PCIR_BAR(barnum),
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CVMX_OCT_PCI_IO_BASE + sc->sc_io_next, 4);
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sc->sc_io_next += size;
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/*
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* Enable I/O ports.
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*/
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*commandp |= PCIM_CMD_PORTEN;
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} else {
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size = ~(bar & (uint32_t)PCIM_BAR_MEM_BASE) + 1;
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@ -615,6 +632,11 @@ octopci_init_bar(device_t dev, unsigned b, unsigned s, unsigned f, unsigned barn
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octopci_write_config(dev, b, s, f, PCIR_BAR(barnum),
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CVMX_OCT_PCI_MEM1_BASE + sc->sc_mem1_next, 4);
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sc->sc_mem1_next += size;
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/*
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* Enable memory access.
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*/
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*commandp |= PCIM_CMD_MEMEN;
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}
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}
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@ -630,6 +652,13 @@ octopci_init_device(device_t dev, unsigned b, unsigned s, unsigned f, unsigned s
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/* Read header type (again.) */
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hdrtype = octopci_read_config(dev, b, s, f, PCIR_HDRTYPE, 1);
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/*
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* Disable memory and I/O while programming BARs.
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*/
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command = octopci_read_config(dev, b, s, f, PCIR_COMMAND, 1);
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command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
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octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
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/* Program BARs. */
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switch (hdrtype & PCIM_HDRTYPE) {
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case PCIM_HDRTYPE_NORMAL:
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@ -648,14 +677,12 @@ octopci_init_device(device_t dev, unsigned b, unsigned s, unsigned f, unsigned s
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}
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for (barnum = 0; barnum < bars; barnum++)
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octopci_init_bar(dev, b, s, f, barnum);
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/* Enable memory and I/O. */
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command = octopci_read_config(dev, b, s, f, PCIR_COMMAND, 1);
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command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
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octopci_init_bar(dev, b, s, f, barnum, &command);
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/* Enable bus mastering. */
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command |= PCIM_CMD_BUSMASTEREN;
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/* Enable whatever facilities the BARs require. */
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octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
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/*
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@ -668,6 +695,38 @@ octopci_init_device(device_t dev, unsigned b, unsigned s, unsigned f, unsigned s
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/* Set latency timer. */
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octopci_write_config(dev, b, s, f, PCIR_LATTIMER, 48, 1);
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/* Board-specific or device-specific fixups and workarounds. */
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switch (cvmx_sysinfo_get()->board_type) {
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#if defined(OCTEON_VENDOR_LANNER)
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case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
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if (b == 1 && s == 7 && f == 0) {
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bus_addr_t busaddr, unitbusaddr;
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uint32_t bar;
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uint32_t tmp;
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unsigned unit;
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/*
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* Set Tx DMA power.
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*/
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bar = octopci_read_config(dev, b, s, f,
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PCIR_BAR(3), 4);
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busaddr = CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_PCI,
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CVMX_OCT_SUBDID_PCI_MEM1));
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busaddr += (bar & (uint32_t)PCIM_BAR_MEM_BASE);
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for (unit = 0; unit < 4; unit++) {
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unitbusaddr = busaddr + 0x430 + (unit << 8);
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tmp = le32toh(cvmx_read64_uint32(unitbusaddr));
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tmp &= ~0x700;
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tmp |= 0x300;
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cvmx_write64_uint32(unitbusaddr, htole32(tmp));
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}
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}
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break;
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#endif
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default:
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break;
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}
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/* Configure PCI-PCI bridges. */
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class = octopci_read_config(dev, b, s, f, PCIR_CLASS, 1);
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if (class != PCIC_BRIDGE)
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@ -677,6 +736,10 @@ octopci_init_device(device_t dev, unsigned b, unsigned s, unsigned f, unsigned s
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if (subclass != PCIS_BRIDGE_PCI)
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return (secbus);
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/* Enable memory and I/O access. */
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command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
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octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
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/* Enable errors and parity checking. Do a bus reset. */
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brctl = octopci_read_config(dev, b, s, f, PCIR_BRIDGECTL_1, 1);
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brctl |= PCIB_BCR_PERR_ENABLE | PCIB_BCR_SERR_ENABLE;
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