Add stubs for RISC-V ISA so libunwind can be compiled.
Reviewed by: emaste Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D5035
This commit is contained in:
br
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87eab6d83d
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a75e74c454
@ -295,6 +295,77 @@ enum {
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UNW_PPC_SPEFSCR = 112
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};
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// 64-bit RISC-V registers
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enum {
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UNW_RISCV_X0 = 0,
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UNW_RISCV_X1 = 1,
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UNW_RISCV_RA = 1,
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UNW_RISCV_X2 = 2,
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UNW_RISCV_SP = 2,
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UNW_RISCV_X3 = 3,
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UNW_RISCV_X4 = 4,
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UNW_RISCV_X5 = 5,
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UNW_RISCV_X6 = 6,
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UNW_RISCV_X7 = 7,
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UNW_RISCV_X8 = 8,
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UNW_RISCV_X9 = 9,
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UNW_RISCV_X10 = 10,
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UNW_RISCV_X11 = 11,
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UNW_RISCV_X12 = 12,
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UNW_RISCV_X13 = 13,
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UNW_RISCV_X14 = 14,
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UNW_RISCV_X15 = 15,
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UNW_RISCV_X16 = 16,
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UNW_RISCV_X17 = 17,
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UNW_RISCV_X18 = 18,
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UNW_RISCV_X19 = 19,
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UNW_RISCV_X20 = 20,
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UNW_RISCV_X21 = 21,
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UNW_RISCV_X22 = 22,
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UNW_RISCV_X23 = 23,
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UNW_RISCV_X24 = 24,
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UNW_RISCV_X25 = 25,
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UNW_RISCV_X26 = 26,
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UNW_RISCV_X27 = 27,
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UNW_RISCV_X28 = 28,
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UNW_RISCV_X29 = 29,
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UNW_RISCV_X30 = 30,
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UNW_RISCV_X31 = 31,
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// reserved block
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UNW_RISCV_D0 = 64,
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UNW_RISCV_D1 = 65,
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UNW_RISCV_D2 = 66,
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UNW_RISCV_D3 = 67,
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UNW_RISCV_D4 = 68,
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UNW_RISCV_D5 = 69,
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UNW_RISCV_D6 = 70,
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UNW_RISCV_D7 = 71,
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UNW_RISCV_D8 = 72,
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UNW_RISCV_D9 = 73,
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UNW_RISCV_D10 = 74,
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UNW_RISCV_D11 = 75,
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UNW_RISCV_D12 = 76,
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UNW_RISCV_D13 = 77,
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UNW_RISCV_D14 = 78,
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UNW_RISCV_D15 = 79,
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UNW_RISCV_D16 = 80,
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UNW_RISCV_D17 = 81,
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UNW_RISCV_D18 = 82,
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UNW_RISCV_D19 = 83,
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UNW_RISCV_D20 = 84,
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UNW_RISCV_D21 = 85,
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UNW_RISCV_D22 = 86,
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UNW_RISCV_D23 = 87,
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UNW_RISCV_D24 = 88,
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UNW_RISCV_D25 = 89,
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UNW_RISCV_D26 = 90,
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UNW_RISCV_D27 = 91,
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UNW_RISCV_D28 = 92,
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UNW_RISCV_D29 = 93,
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UNW_RISCV_D30 = 94,
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UNW_RISCV_D31 = 95,
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};
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// 64-bit ARM64 registers
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enum {
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UNW_ARM64_X0 = 0,
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@ -1024,6 +1024,264 @@ inline const char *Registers_ppc::getRegisterName(int regNum) {
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}
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/// Registers_riscv holds the register state of a thread in a 64-bit RISC-V
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/// process.
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class _LIBUNWIND_HIDDEN Registers_riscv {
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public:
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Registers_riscv();
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Registers_riscv(const void *registers);
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bool validRegister(int num) const;
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uint64_t getRegister(int num) const;
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void setRegister(int num, uint64_t value);
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bool validFloatRegister(int num) const;
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double getFloatRegister(int num) const;
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void setFloatRegister(int num, double value);
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bool validVectorRegister(int num) const;
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v128 getVectorRegister(int num) const;
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void setVectorRegister(int num, v128 value);
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const char *getRegisterName(int num);
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void jumpto();
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static int lastDwarfRegNum() { return 95; }
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uint64_t getSP() const { return _registers.__x[2]; }
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void setSP(uint64_t value) { _registers.__x[2] = value; }
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uint64_t getIP() const { return _registers.__x[1]; }
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void setIP(uint64_t value) { _registers.__x[1] = value; }
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private:
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struct GPRs {
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uint64_t __x[32]; // x0-x31
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};
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GPRs _registers;
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double _vectorHalfRegisters[32];
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// Currently only the lower double in 128-bit vectore registers
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// is perserved during unwinding. We could define new register
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// numbers (> 96) which mean whole vector registers, then this
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// struct would need to change to contain whole vector registers.
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};
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inline Registers_riscv::Registers_riscv(const void *registers) {
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static_assert(sizeof(Registers_riscv) < sizeof(unw_context_t),
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"riscv registers do not fit into unw_context_t");
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memcpy(&_registers, registers, sizeof(_registers));
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static_assert(sizeof(GPRs) == 0x100,
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"expected VFP registers to be at offset 256");
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memcpy(_vectorHalfRegisters,
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static_cast<const uint8_t *>(registers) + sizeof(GPRs),
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sizeof(_vectorHalfRegisters));
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}
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inline Registers_riscv::Registers_riscv() {
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memset(&_registers, 0, sizeof(_registers));
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memset(&_vectorHalfRegisters, 0, sizeof(_vectorHalfRegisters));
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}
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inline bool Registers_riscv::validRegister(int regNum) const {
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if (regNum == UNW_REG_IP)
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return true;
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if (regNum == UNW_REG_SP)
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return true;
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if (regNum < 0)
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return false;
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if (regNum > 95)
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return false;
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if ((regNum > 31) && (regNum < 64))
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return false;
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return true;
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}
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inline uint64_t Registers_riscv::getRegister(int regNum) const {
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if (regNum == UNW_REG_IP)
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return _registers.__x[1];
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if (regNum == UNW_REG_SP)
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return _registers.__x[2];
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if ((regNum >= 0) && (regNum < 32))
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return _registers.__x[regNum];
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_LIBUNWIND_ABORT("unsupported riscv register");
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}
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inline void Registers_riscv::setRegister(int regNum, uint64_t value) {
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if (regNum == UNW_REG_IP)
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_registers.__x[1] = value;
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else if (regNum == UNW_REG_SP)
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_registers.__x[2] = value;
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else if ((regNum >= 0) && (regNum < 32))
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_registers.__x[regNum] = value;
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else
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_LIBUNWIND_ABORT("unsupported riscv register");
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}
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inline const char *Registers_riscv::getRegisterName(int regNum) {
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switch (regNum) {
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case UNW_REG_IP:
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return "ra";
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case UNW_REG_SP:
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return "sp";
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case UNW_RISCV_X0:
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return "x0";
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case UNW_RISCV_X1:
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return "ra";
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case UNW_RISCV_X2:
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return "sp";
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case UNW_RISCV_X3:
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return "x3";
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case UNW_RISCV_X4:
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return "x4";
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case UNW_RISCV_X5:
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return "x5";
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case UNW_RISCV_X6:
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return "x6";
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case UNW_RISCV_X7:
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return "x7";
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case UNW_RISCV_X8:
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return "x8";
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case UNW_RISCV_X9:
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return "x9";
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case UNW_RISCV_X10:
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return "x10";
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case UNW_RISCV_X11:
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return "x11";
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case UNW_RISCV_X12:
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return "x12";
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case UNW_RISCV_X13:
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return "x13";
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case UNW_RISCV_X14:
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return "x14";
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case UNW_RISCV_X15:
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return "x15";
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case UNW_RISCV_X16:
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return "x16";
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case UNW_RISCV_X17:
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return "x17";
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case UNW_RISCV_X18:
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return "x18";
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case UNW_RISCV_X19:
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return "x19";
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case UNW_RISCV_X20:
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return "x20";
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case UNW_RISCV_X21:
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return "x21";
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case UNW_RISCV_X22:
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return "x22";
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case UNW_RISCV_X23:
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return "x23";
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case UNW_RISCV_X24:
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return "x24";
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case UNW_RISCV_X25:
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return "x25";
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case UNW_RISCV_X26:
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return "x26";
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case UNW_RISCV_X27:
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return "x27";
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case UNW_RISCV_X28:
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return "x28";
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case UNW_RISCV_X29:
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return "x29";
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case UNW_RISCV_X30:
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return "x30";
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case UNW_RISCV_X31:
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return "x31";
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case UNW_RISCV_D0:
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return "d0";
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case UNW_RISCV_D1:
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return "d1";
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case UNW_RISCV_D2:
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return "d2";
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case UNW_RISCV_D3:
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return "d3";
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case UNW_RISCV_D4:
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return "d4";
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case UNW_RISCV_D5:
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return "d5";
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case UNW_RISCV_D6:
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return "d6";
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case UNW_RISCV_D7:
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return "d7";
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case UNW_RISCV_D8:
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return "d8";
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case UNW_RISCV_D9:
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return "d9";
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case UNW_RISCV_D10:
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return "d10";
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case UNW_RISCV_D11:
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return "d11";
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case UNW_RISCV_D12:
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return "d12";
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case UNW_RISCV_D13:
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return "d13";
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case UNW_RISCV_D14:
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return "d14";
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case UNW_RISCV_D15:
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return "d15";
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case UNW_RISCV_D16:
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return "d16";
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case UNW_RISCV_D17:
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return "d17";
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case UNW_RISCV_D18:
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return "d18";
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case UNW_RISCV_D19:
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return "d19";
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case UNW_RISCV_D20:
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return "d20";
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case UNW_RISCV_D21:
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return "d21";
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case UNW_RISCV_D22:
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return "d22";
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case UNW_RISCV_D23:
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return "d23";
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case UNW_RISCV_D24:
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return "d24";
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case UNW_RISCV_D25:
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return "d25";
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case UNW_RISCV_D26:
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return "d26";
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case UNW_RISCV_D27:
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return "d27";
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case UNW_RISCV_D28:
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return "d28";
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case UNW_RISCV_D29:
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return "d29";
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case UNW_RISCV_D30:
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return "d30";
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case UNW_RISCV_D31:
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return "d31";
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default:
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return "unknown register";
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}
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}
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inline bool Registers_riscv::validFloatRegister(int regNum) const {
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if (regNum < UNW_RISCV_D0)
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return false;
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if (regNum > UNW_RISCV_D31)
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return false;
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return true;
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}
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inline double Registers_riscv::getFloatRegister(int regNum) const {
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assert(validFloatRegister(regNum));
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return _vectorHalfRegisters[regNum - UNW_RISCV_D0];
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}
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inline void Registers_riscv::setFloatRegister(int regNum, double value) {
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assert(validFloatRegister(regNum));
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_vectorHalfRegisters[regNum - UNW_RISCV_D0] = value;
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}
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inline bool Registers_riscv::validVectorRegister(int) const {
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return false;
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}
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inline v128 Registers_riscv::getVectorRegister(int) const {
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_LIBUNWIND_ABORT("no riscv vector register support yet");
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}
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inline void Registers_riscv::setVectorRegister(int, v128) {
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_LIBUNWIND_ABORT("no riscv vector register support yet");
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}
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/// Registers_arm64 holds the register state of a thread in a 64-bit arm
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/// process.
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@ -562,6 +562,10 @@ class UnwindCursor : public AbstractUnwindCursor{
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compact_unwind_encoding_t dwarfEncoding(Registers_or1k &) const {
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return 0;
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}
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compact_unwind_encoding_t dwarfEncoding(Registers_riscv &) const {
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return 0;
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}
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#endif // _LIBUNWIND_SUPPORT_DWARF_UNWIND
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@ -478,4 +478,8 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind14Registers_or1k6jumptoEv)
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l.jr r9
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l.nop
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#elif defined(__riscv__)
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/* RISCVTODO */
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#endif
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@ -463,4 +463,9 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
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l.sw 116(r3), r29
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l.sw 120(r3), r30
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l.sw 124(r3), r31
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#elif defined(__riscv__)
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/* RISCVTODO */
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#endif
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@ -74,7 +74,8 @@
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#define _LIBUNWIND_BUILD_ZERO_COST_APIS (defined(__i386__) || \
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defined(__x86_64__) || \
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defined(__arm__) || \
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defined(__aarch64__))
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defined(__aarch64__) || \
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defined(__riscv__))
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#define _LIBUNWIND_BUILD_SJLJ_APIS 0
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#define _LIBUNWIND_SUPPORT_FRAME_APIS (defined(__i386__) || \
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defined(__x86_64__))
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@ -66,6 +66,9 @@ _LIBUNWIND_EXPORT int unw_init_local(unw_cursor_t *cursor,
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context, LocalAddressSpace::sThisAddressSpace);
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#elif defined(__mips__)
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#warning The MIPS architecture is not supported.
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#elif defined(__riscv__)
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new ((void *)cursor) UnwindCursor<LocalAddressSpace, Registers_riscv>(
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context, LocalAddressSpace::sThisAddressSpace);
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#else
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#error Architecture not supported
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#endif
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