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powerpc: Add a couple missing isyncs

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mtmsr and mtsr require context synchronizing instructions to follow.  Without
a CSI, there's a chance for a machine check exception.  This reportedly does
occur on a MPC750 (PowerMac G3).

Reported by:	Mark Millard
This commit is contained in:
jhibbits 2019-04-24 02:51:58 +00:00
parent 21f6670fd2
commit a8ca8ce89b
1 changed files with 2 additions and 1 deletions
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3
sys/powerpc/aim/trap_subr32.S
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@ -68,7 +68,7 @@
lwzu sr,PM_SR(pmap); \ lwzu sr,PM_SR(pmap); \
RESTORE_SRS(pmap,sr) \ RESTORE_SRS(pmap,sr) \
/* Restore SR 12 */ \ /* Restore SR 12 */ \
lwz sr,12*4(pmap); mtsr 12,sr lwz sr,12*4(pmap); mtsr 12,sr; isync
/* /*
* Kernel SRs are loaded directly from kernel_pmap_ * Kernel SRs are loaded directly from kernel_pmap_
@ -799,6 +799,7 @@ CNAME(trapexit):
mfmsr %r3 mfmsr %r3
andi. %r3,%r3,~PSL_EE@l andi. %r3,%r3,~PSL_EE@l
mtmsr %r3 mtmsr %r3
isync
/* Test AST pending: */ /* Test AST pending: */
lwz %r5,FRAME_SRR1+8(%r1) lwz %r5,FRAME_SRR1+8(%r1)
mtcr %r5 mtcr %r5