Adjust the padding to account for the change of size of the MI part
of struct pcpu.
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@ -74,7 +74,7 @@ struct pmap;
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u_int pc_kwbuf_full; \
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struct rwindow pc_tsbwbuf[2]; \
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uint16_t pc_cpulist[MAXCPU]; \
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uint64_t pad[9];
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uint64_t pad[4];
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/* XXX SUN4V_FIXME - as we access the *_ra and *_size fields in quick
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* succession we _really_ want them to be L1 cache line size aligned
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