Remove badly broken pcic driver for NEWCARD
This commit is contained in:
Warner Losh
parent
1b868fa919
commit
a9a74ddc37
File diff suppressed because it is too large
Load Diff
@ -1,406 +0,0 @@
|
||||
/* $NetBSD: i82365_isasubr.c,v 1.3 1999/10/15 06:07:27 haya Exp $ */
|
||||
/* $NetBSD: i82365_isa.c,v 1.11 1998/06/09 07:25:00 thorpej Exp $ */
|
||||
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
/*
|
||||
* Copyright (c) 1998 Bill Sommerfeld. All rights reserved.
|
||||
* Copyright (c) 1997 Marc Horowitz. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Marc Horowitz.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/queue.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include <sys/bus.h>
|
||||
#include <machine/bus.h>
|
||||
#include <sys/rman.h>
|
||||
#include <machine/resource.h>
|
||||
|
||||
#include <isa/isavar.h>
|
||||
|
||||
#include <dev/pccard/pccardreg.h>
|
||||
#include <dev/pccard/pccardvar.h>
|
||||
|
||||
#include <dev/pcic/i82365reg.h>
|
||||
#include <dev/pcic/i82365var.h>
|
||||
|
||||
#include "power_if.h"
|
||||
#include "card_if.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Configurable parameters.
|
||||
*****************************************************************************/
|
||||
|
||||
/*
|
||||
* Default I/O allocation range. If both are set to non-zero, these
|
||||
* values will be used instead. Otherwise, the code attempts to probe
|
||||
* the bus width. Systems with 10 address bits should use 0x300 and 0xff.
|
||||
* Systems with 12 address bits (most) should use 0x400 and 0xbff.
|
||||
*/
|
||||
|
||||
#ifndef PCIC_ISA_ALLOC_IOBASE
|
||||
#define PCIC_ISA_ALLOC_IOBASE 0
|
||||
#endif
|
||||
|
||||
#ifndef PCIC_ISA_ALLOC_IOSIZE
|
||||
#define PCIC_ISA_ALLOC_IOSIZE 0
|
||||
#endif
|
||||
|
||||
int pcic_isa_alloc_iobase = PCIC_ISA_ALLOC_IOBASE;
|
||||
int pcic_isa_alloc_iosize = PCIC_ISA_ALLOC_IOSIZE;
|
||||
|
||||
|
||||
/*
|
||||
* Default IRQ allocation bitmask. This defines the range of allowable
|
||||
* IRQs for PCCARD slots. Useful if order of probing would screw up other
|
||||
* devices, or if PCIC hardware/cards have trouble with certain interrupt
|
||||
* lines.
|
||||
*
|
||||
* We disable IRQ 10 by default, since some common laptops (namely, the
|
||||
* NEC Versa series) reserve IRQ 10 for the docking station SCSI interface.
|
||||
*/
|
||||
|
||||
#ifndef PCIC_ISA_INTR_ALLOC_MASK
|
||||
#define PCIC_ISA_INTR_ALLOC_MASK 0xfbff
|
||||
#endif
|
||||
|
||||
int pcic_isa_intr_alloc_mask = PCIC_ISA_INTR_ALLOC_MASK;
|
||||
|
||||
/*****************************************************************************
|
||||
* End of configurable parameters.
|
||||
*****************************************************************************/
|
||||
|
||||
#define PCICISADEBUG 1
|
||||
|
||||
#ifdef PCICISADEBUG
|
||||
int pcicisa_debug = PCICISADEBUG;
|
||||
#define DPRINTF(arg) if (pcicisa_debug) printf arg;
|
||||
#define DEVPRINTF(arg) if (pcicisa_debug) device_printf arg;
|
||||
#else
|
||||
#define DPRINTF(arg)
|
||||
#define DEVPRINTF(arg)
|
||||
#endif
|
||||
|
||||
static struct isa_pnp_id pcic_ids[] = {
|
||||
{PCIC_PNP_ACTIONTEC, NULL}, /* AEI0218 */
|
||||
{PCIC_PNP_IBM3765, NULL}, /* IBM3765 */
|
||||
{PCIC_PNP_82365, NULL}, /* PNP0E00 */
|
||||
{PCIC_PNP_CL_PD6720, NULL}, /* PNP0E01 */
|
||||
{PCIC_PNP_VLSI_82C146, NULL}, /* PNP0E02 */
|
||||
{PCIC_PNP_82365_CARDBUS, NULL}, /* PNP0E03 */
|
||||
{PCIC_PNP_SCM_SWAPBOX, NULL}, /* SCM0469 */
|
||||
{0}
|
||||
};
|
||||
|
||||
static void
|
||||
pcic_isa_bus_width_probe (device_t dev)
|
||||
{
|
||||
struct pcic_softc *sc = PCIC_SOFTC(dev);
|
||||
bus_space_handle_t ioh_high;
|
||||
int i, iobuswidth, tmp1, tmp2;
|
||||
int rid;
|
||||
u_long base;
|
||||
u_int32_t length;
|
||||
bus_space_tag_t iot;
|
||||
bus_space_handle_t ioh;
|
||||
struct resource *r;
|
||||
|
||||
base = rman_get_start(sc->port_res);
|
||||
length = rman_get_size(sc->port_res);
|
||||
iot = sc->iot;
|
||||
ioh = sc->ioh;
|
||||
|
||||
/*
|
||||
* figure out how wide the isa bus is. Do this by checking if the
|
||||
* pcic controller is mirrored 0x400 above where we expect it to be.
|
||||
*/
|
||||
|
||||
iobuswidth = 12;
|
||||
rid = 1;
|
||||
r = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, base + 0x400,
|
||||
base + 0x400 + length, length, RF_ACTIVE);
|
||||
if (!r) {
|
||||
printf("Can't allocated mirror area for pcic bus width probe\n");
|
||||
return;
|
||||
}
|
||||
ioh_high = rman_get_bushandle(r);
|
||||
for (i = 0; i < PCIC_NSLOTS; i++) {
|
||||
if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) {
|
||||
/*
|
||||
* read the ident flags from the normal space and
|
||||
* from the mirror, and compare them
|
||||
*/
|
||||
|
||||
bus_space_write_1(iot, ioh, PCIC_REG_INDEX,
|
||||
sc->handle[i].sock + PCIC_IDENT);
|
||||
tmp1 = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
|
||||
|
||||
bus_space_write_1(iot, ioh_high, PCIC_REG_INDEX,
|
||||
sc->handle[i].sock + PCIC_IDENT);
|
||||
tmp2 = bus_space_read_1(iot, ioh_high, PCIC_REG_DATA);
|
||||
|
||||
if (tmp1 == tmp2)
|
||||
iobuswidth = 10;
|
||||
}
|
||||
}
|
||||
bus_release_resource(dev, SYS_RES_IOPORT, rid, r);
|
||||
|
||||
/*
|
||||
* XXX mycroft recommends I/O space range 0x400-0xfff . I should put
|
||||
* this in a header somewhere
|
||||
*/
|
||||
|
||||
/*
|
||||
* XXX some hardware doesn't seem to grok addresses in 0x400 range--
|
||||
* apparently missing a bit or more of address lines. (e.g.
|
||||
* CIRRUS_PD672X with Linksys EthernetCard ne2000 clone in TI
|
||||
* TravelMate 5000--not clear which is at fault)
|
||||
*
|
||||
* Add a kludge to detect 10 bit wide buses and deal with them,
|
||||
* and also a config file option to override the probe.
|
||||
*/
|
||||
|
||||
if (iobuswidth == 10) {
|
||||
sc->iobase = 0x300;
|
||||
sc->iosize = 0x0ff;
|
||||
} else {
|
||||
#if 0
|
||||
/*
|
||||
* This is what we'd like to use, but...
|
||||
*/
|
||||
sc->iobase = 0x400;
|
||||
sc->iosize = 0xbff;
|
||||
#else
|
||||
/*
|
||||
* ...the above bus width probe doesn't always work.
|
||||
* So, experimentation has shown the following range
|
||||
* to not lose on systems that 0x300-0x3ff loses on
|
||||
* (e.g. the NEC Versa 6030X).
|
||||
*/
|
||||
sc->iobase = 0x330;
|
||||
sc->iosize = 0x0cf;
|
||||
#endif
|
||||
}
|
||||
|
||||
DEVPRINTF((dev, "bus_space_alloc range 0x%04lx-0x%04lx (probed)\n",
|
||||
(long) sc->iobase, (long) sc->iobase + sc->iosize));
|
||||
|
||||
if (pcic_isa_alloc_iobase && pcic_isa_alloc_iosize) {
|
||||
sc->iobase = pcic_isa_alloc_iobase;
|
||||
sc->iosize = pcic_isa_alloc_iosize;
|
||||
|
||||
DEVPRINTF((dev, "bus_space_alloc range 0x%04lx-0x%04lx "
|
||||
"(config override)\n", (long) sc->iobase,
|
||||
(long) sc->iobase + sc->iosize));
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
static int
|
||||
pcic_isa_check(device_t dev, u_int16_t addr)
|
||||
{
|
||||
bus_space_tag_t iot;
|
||||
bus_space_handle_t ioh;
|
||||
int val, found;
|
||||
int rid;
|
||||
struct resource *res;
|
||||
|
||||
rid = 0;
|
||||
res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, addr, addr,
|
||||
PCIC_IOSIZE, RF_ACTIVE);
|
||||
if (!res)
|
||||
return(ENXIO);
|
||||
iot = rman_get_bustag(res);
|
||||
ioh = rman_get_bushandle(res);
|
||||
found = 0;
|
||||
|
||||
/*
|
||||
* this could be done with a loop, but it would violate the
|
||||
* abstraction
|
||||
*/
|
||||
bus_space_write_1(iot, ioh, PCIC_REG_INDEX, C0SA + PCIC_IDENT);
|
||||
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
|
||||
if (pcic_ident_ok(val))
|
||||
found++;
|
||||
|
||||
bus_space_write_1(iot, ioh, PCIC_REG_INDEX, C0SB + PCIC_IDENT);
|
||||
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
|
||||
if (pcic_ident_ok(val))
|
||||
found++;
|
||||
|
||||
bus_space_write_1(iot, ioh, PCIC_REG_INDEX, C1SA + PCIC_IDENT);
|
||||
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
|
||||
if (pcic_ident_ok(val))
|
||||
found++;
|
||||
|
||||
bus_space_write_1(iot, ioh, PCIC_REG_INDEX, C1SB + PCIC_IDENT);
|
||||
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
|
||||
if (pcic_ident_ok(val))
|
||||
found++;
|
||||
|
||||
bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
|
||||
|
||||
return (found);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int
|
||||
pcic_isa_probe(device_t dev)
|
||||
{
|
||||
int error;
|
||||
struct resource *res;
|
||||
int rid;
|
||||
int i;
|
||||
u_long mem;
|
||||
|
||||
/* Check isapnp ids */
|
||||
error = ISA_PNP_PROBE(device_get_parent(dev), dev, pcic_ids);
|
||||
if (error == ENXIO)
|
||||
return (ENXIO);
|
||||
|
||||
/* If we had some other problem. */
|
||||
if (!(error == 0 || error == ENOENT))
|
||||
return (error);
|
||||
|
||||
/* If we have the resources we need then we're good to go. */
|
||||
if (bus_get_resource_start(dev, SYS_RES_IOPORT, 0) == 0)
|
||||
return (ENXIO);
|
||||
rid = 0;
|
||||
res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
|
||||
if (res == NULL) {
|
||||
/*
|
||||
* No IRQ specified, find one. This can be due to the PnP
|
||||
* data not specifying any IRQ
|
||||
*/
|
||||
for (i = 0; i < 16; i++) {
|
||||
if (((1 << i) & PCIC_INTR_IRQ_VALIDMASK) == 0)
|
||||
continue;
|
||||
res = bus_alloc_resource(dev, SYS_RES_IRQ,
|
||||
&rid, i, i, 1, RF_ACTIVE);
|
||||
if (res != NULL)
|
||||
break;
|
||||
}
|
||||
if (res == NULL)
|
||||
return (ENXIO);
|
||||
mem = rman_get_start(res);
|
||||
bus_release_resource(dev, SYS_RES_IRQ, rid, res);
|
||||
bus_set_resource(dev, SYS_RES_IRQ, 0, i, 1);
|
||||
} else {
|
||||
bus_release_resource(dev, SYS_RES_IRQ, rid, res);
|
||||
}
|
||||
/* XXX This might not be needed in future, get it directly from
|
||||
* XXX parent */
|
||||
rid = 0;
|
||||
res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0,
|
||||
1 << 13, RF_ACTIVE);
|
||||
if (res == NULL) {
|
||||
/*
|
||||
* We failed to get memory. Since this XXX comment above
|
||||
* indicates that this is transient, we try to get a hunk
|
||||
* of memory in the isa hole. Sure would be nice if there
|
||||
* were some MI constants for this.
|
||||
*/
|
||||
res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
|
||||
0xa0000, 0xdffff, 1 << 13, RF_ACTIVE);
|
||||
if (res != NULL) {
|
||||
mem = rman_get_start(res);
|
||||
bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
|
||||
bus_set_resource(dev, SYS_RES_MEMORY, 0, mem, 1 << 13);
|
||||
}
|
||||
} else {
|
||||
bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
|
||||
}
|
||||
if (res == NULL) {
|
||||
device_printf(dev, "Cannot allocate mem\n");
|
||||
return ENOMEM;
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
pcic_isa_attach(device_t dev)
|
||||
{
|
||||
int err = 0;
|
||||
|
||||
if ((err = pcic_attach(dev)) == 0)
|
||||
pcic_isa_bus_width_probe (dev);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
pcic_isa_detach(device_t dev)
|
||||
{
|
||||
pcic_detach(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static device_method_t pcic_isa_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, pcic_isa_probe),
|
||||
DEVMETHOD(device_attach, pcic_isa_attach),
|
||||
DEVMETHOD(device_detach, pcic_isa_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
DEVMETHOD(device_suspend, pcic_suspend),
|
||||
DEVMETHOD(device_resume, pcic_resume),
|
||||
|
||||
/* Bus Interface */
|
||||
DEVMETHOD(bus_driver_added, bus_generic_driver_added),
|
||||
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
||||
DEVMETHOD(bus_alloc_resource, pcic_alloc_resource),
|
||||
DEVMETHOD(bus_release_resource, pcic_release_resource),
|
||||
DEVMETHOD(bus_activate_resource, pcic_activate_resource),
|
||||
DEVMETHOD(bus_deactivate_resource, pcic_deactivate_resource),
|
||||
DEVMETHOD(bus_setup_intr, pcic_setup_intr),
|
||||
DEVMETHOD(bus_teardown_intr, pcic_teardown_intr),
|
||||
|
||||
/* pccard/cardbus interface */
|
||||
DEVMETHOD(card_set_res_flags, pcic_set_res_flags),
|
||||
DEVMETHOD(card_set_memory_offset, pcic_set_memory_offset),
|
||||
|
||||
/* Power Interface */
|
||||
DEVMETHOD(power_enable_socket, pcic_enable_socket),
|
||||
DEVMETHOD(power_disable_socket, pcic_disable_socket),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t pcic_driver = {
|
||||
"pcic",
|
||||
pcic_isa_methods,
|
||||
sizeof(struct pcic_softc)
|
||||
};
|
||||
|
||||
static devclass_t pcic_devclass;
|
||||
|
||||
DRIVER_MODULE(pcic, isa, pcic_driver, pcic_devclass, 0, 0);
|
||||
MODULE_DEPEND(pcic, pccard, 1, 1, 1);
|
||||
@ -1,365 +0,0 @@
|
||||
/* $NetBSD: i82365reg.h,v 1.3 1998/12/20 17:53:28 nathanw Exp $ */
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Marc Horowitz. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Marc Horowitz.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* All information is from the intel 82365sl PC Card Interface Controller
|
||||
* (PCIC) data sheet, marked "preliminary". Order number 290423-002, January
|
||||
* 1993.
|
||||
*/
|
||||
|
||||
#define PCIC_IOSIZE 2
|
||||
|
||||
#define PCIC_REG_INDEX 0
|
||||
#define PCIC_REG_DATA 1
|
||||
|
||||
/*
|
||||
* I/o ports
|
||||
*/
|
||||
#define PCIC_INDEX0 0x3e0
|
||||
|
||||
/*
|
||||
* The PCIC allows two chips to share the same address. In order not to run
|
||||
* afoul of the netbsd device model, this driver will treat those chips as
|
||||
* the same device.
|
||||
*/
|
||||
|
||||
#define PCIC_CHIP0_BASE 0x00
|
||||
#define PCIC_CHIP1_BASE 0x80
|
||||
|
||||
/* Each PCIC chip can drive two sockets */
|
||||
|
||||
#define PCIC_SOCKETA_INDEX 0x00
|
||||
#define PCIC_SOCKETB_INDEX 0x40
|
||||
|
||||
/* general setup registers */
|
||||
|
||||
#define PCIC_IDENT 0x00 /* RO */
|
||||
#define PCIC_IDENT_IFTYPE_MASK 0xC0
|
||||
#define PCIC_IDENT_IFTYPE_IO_ONLY 0x00
|
||||
#define PCIC_IDENT_IFTYPE_MEM_ONLY 0x40
|
||||
#define PCIC_IDENT_IFTYPE_MEM_AND_IO 0x80
|
||||
#define PCIC_IDENT_IFTYPE_RESERVED 0xC0
|
||||
#define PCIC_IDENT_ZERO 0x30
|
||||
#define PCIC_IDENT_REV_MASK 0x0F
|
||||
#define PCIC_IDENT_REV_I82365SLR0 0x02
|
||||
#define PCIC_IDENT_REV_I82365SLR1 0x03
|
||||
|
||||
#define PCIC_IF_STATUS 0x01 /* RO */
|
||||
#define PCIC_IF_STATUS_GPI 0x80 /* General Purpose Input */
|
||||
#define PCIC_IF_STATUS_POWERACTIVE 0x40
|
||||
#define PCIC_IF_STATUS_READY 0x20 /* really READY/!BUSY */
|
||||
#define PCIC_IF_STATUS_MEM_WP 0x10
|
||||
#define PCIC_IF_STATUS_CARDDETECT_MASK 0x0C
|
||||
#define PCIC_IF_STATUS_CARDDETECT_PRESENT 0x0C
|
||||
#define PCIC_IF_STATUS_BATTERY_MASK 0x03
|
||||
#define PCIC_IF_STATUS_BATTERY_DEAD1 0x00
|
||||
#define PCIC_IF_STATUS_BATTERY_DEAD2 0x01
|
||||
#define PCIC_IF_STATUS_BATTERY_WARNING 0x02
|
||||
#define PCIC_IF_STATUS_BATTERY_GOOD 0x03
|
||||
|
||||
#define PCIC_PWRCTL 0x02 /* RW */
|
||||
#define PCIC_PWRCTL_OE 0x80 /* output enable */
|
||||
#define PCIC_PWRCTL_DISABLE_RESETDRV 0x40
|
||||
#define PCIC_PWRCTL_AUTOSWITCH_ENABLE 0x20
|
||||
#define PCIC_PWRCTL_PWR_ENABLE 0x10
|
||||
#define PCIC_PWRCTL_VPP2_MASK 0x0C
|
||||
/* XXX these are a little unclear from the data sheet */
|
||||
#define PCIC_PWRCTL_VPP2_RESERVED 0x0C
|
||||
#define PCIC_PWRCTL_VPP2_EN1 0x08
|
||||
#define PCIC_PWRCTL_VPP2_EN0 0x04
|
||||
#define PCIC_PWRCTL_VPP2_ENX 0x00
|
||||
#define PCIC_PWRCTL_VPP1_MASK 0x03
|
||||
/* XXX these are a little unclear from the data sheet */
|
||||
#define PCIC_PWRCTL_VPP1_RESERVED 0x03
|
||||
#define PCIC_PWRCTL_VPP1_EN1 0x02
|
||||
#define PCIC_PWRCTL_VPP1_EN0 0x01
|
||||
#define PCIC_PWRCTL_VPP1_ENX 0x00
|
||||
|
||||
#define PCIC_CSC 0x04 /* RW */
|
||||
#define PCIC_CSC_ZERO 0xE0
|
||||
#define PCIC_CSC_GPI 0x10
|
||||
#define PCIC_CSC_CD 0x08 /* Card Detect Change */
|
||||
#define PCIC_CSC_READY 0x04
|
||||
#define PCIC_CSC_BATTWARN 0x02
|
||||
#define PCIC_CSC_BATTDEAD 0x01 /* for memory cards */
|
||||
#define PCIC_CSC_RI 0x01 /* for i/o cards */
|
||||
|
||||
#define PCIC_ADDRWIN_ENABLE 0x06 /* RW */
|
||||
#define PCIC_ADDRWIN_ENABLE_IO1 0x80
|
||||
#define PCIC_ADDRWIN_ENABLE_IO0 0x40
|
||||
#define PCIC_ADDRWIN_ENABLE_MEMCS16 0x20 /* rtfds if you care */
|
||||
#define PCIC_ADDRWIN_ENABLE_MEM4 0x10
|
||||
#define PCIC_ADDRWIN_ENABLE_MEM3 0x08
|
||||
#define PCIC_ADDRWIN_ENABLE_MEM2 0x04
|
||||
#define PCIC_ADDRWIN_ENABLE_MEM1 0x02
|
||||
#define PCIC_ADDRWIN_ENABLE_MEM0 0x01
|
||||
|
||||
#define PCIC_CARD_DETECT 0x16 /* RW */
|
||||
#define PCIC_CARD_DETECT_RESERVED 0xC0
|
||||
#define PCIC_CARD_DETECT_SW_INTR 0x20
|
||||
#define PCIC_CARD_DETECT_RESUME_ENABLE 0x10
|
||||
#define PCIC_CARD_DETECT_GPI_TRANSCTL 0x08
|
||||
#define PCIC_CARD_DETECT_GPI_ENABLE 0x04
|
||||
#define PCIC_CARD_DETECT_CFGRST_ENABLE 0x02
|
||||
#define PCIC_CARD_DETECT_MEMDLY_INHIBIT 0x01
|
||||
|
||||
/* interrupt registers */
|
||||
|
||||
#define PCIC_INTR 0x03 /* RW */
|
||||
#define PCIC_INTR_RI_ENABLE 0x80
|
||||
#define PCIC_INTR_RESET 0x40 /* active low (zero) */
|
||||
#define PCIC_INTR_CARDTYPE_MASK 0x20
|
||||
#define PCIC_INTR_CARDTYPE_IO 0x20
|
||||
#define PCIC_INTR_CARDTYPE_MEM 0x00
|
||||
#define PCIC_INTR_ENABLE 0x10
|
||||
#define PCIC_INTR_IRQ_MASK 0x0F
|
||||
#define PCIC_INTR_IRQ_SHIFT 0
|
||||
#define PCIC_INTR_IRQ_NONE 0x00
|
||||
#define PCIC_INTR_IRQ_RESERVED1 0x01
|
||||
#define PCIC_INTR_IRQ_RESERVED2 0x02
|
||||
#define PCIC_INTR_IRQ3 0x03
|
||||
#define PCIC_INTR_IRQ4 0x04
|
||||
#define PCIC_INTR_IRQ5 0x05
|
||||
#define PCIC_INTR_IRQ_RESERVED6 0x06
|
||||
#define PCIC_INTR_IRQ7 0x07
|
||||
#define PCIC_INTR_IRQ_RESERVED8 0x08
|
||||
#define PCIC_INTR_IRQ9 0x09
|
||||
#define PCIC_INTR_IRQ10 0x0A
|
||||
#define PCIC_INTR_IRQ11 0x0B
|
||||
#define PCIC_INTR_IRQ12 0x0C
|
||||
#define PCIC_INTR_IRQ_RESERVED13 0x0D
|
||||
#define PCIC_INTR_IRQ14 0x0E
|
||||
#define PCIC_INTR_IRQ15 0x0F
|
||||
|
||||
#define PCIC_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */
|
||||
|
||||
#define PCIC_CSC_INTR 0x05 /* RW */
|
||||
#define PCIC_CSC_INTR_IRQ_MASK 0xF0
|
||||
#define PCIC_CSC_INTR_IRQ_SHIFT 4
|
||||
#define PCIC_CSC_INTR_IRQ_NONE 0x00
|
||||
#define PCIC_CSC_INTR_IRQ_RESERVED1 0x10
|
||||
#define PCIC_CSC_INTR_IRQ_RESERVED2 0x20
|
||||
#define PCIC_CSC_INTR_IRQ3 0x30
|
||||
#define PCIC_CSC_INTR_IRQ4 0x40
|
||||
#define PCIC_CSC_INTR_IRQ5 0x50
|
||||
#define PCIC_CSC_INTR_IRQ_RESERVED6 0x60
|
||||
#define PCIC_CSC_INTR_IRQ7 0x70
|
||||
#define PCIC_CSC_INTR_IRQ_RESERVED8 0x80
|
||||
#define PCIC_CSC_INTR_IRQ9 0x90
|
||||
#define PCIC_CSC_INTR_IRQ10 0xA0
|
||||
#define PCIC_CSC_INTR_IRQ11 0xB0
|
||||
#define PCIC_CSC_INTR_IRQ12 0xC0
|
||||
#define PCIC_CSC_INTR_IRQ_RESERVED13 0xD0
|
||||
#define PCIC_CSC_INTR_IRQ14 0xE0
|
||||
#define PCIC_CSC_INTR_IRQ15 0xF0
|
||||
#define PCIC_CSC_INTR_CD_ENABLE 0x08
|
||||
#define PCIC_CSC_INTR_READY_ENABLE 0x04
|
||||
#define PCIC_CSC_INTR_BATTWARN_ENABLE 0x02
|
||||
#define PCIC_CSC_INTR_BATTDEAD_ENABLE 0x01 /* for memory cards */
|
||||
#define PCIC_CSC_INTR_RI_ENABLE 0x01 /* for I/O cards */
|
||||
|
||||
#define PCIC_CSC_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
#define PCIC_IO_WINS 2
|
||||
|
||||
#define PCIC_IOCTL 0x07 /* RW */
|
||||
#define PCIC_IOCTL_IO1_WAITSTATE 0x80
|
||||
#define PCIC_IOCTL_IO1_ZEROWAIT 0x40
|
||||
#define PCIC_IOCTL_IO1_IOCS16SRC_MASK 0x20
|
||||
#define PCIC_IOCTL_IO1_IOCS16SRC_CARD 0x20
|
||||
#define PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE 0x00
|
||||
#define PCIC_IOCTL_IO1_DATASIZE_MASK 0x10
|
||||
#define PCIC_IOCTL_IO1_DATASIZE_16BIT 0x10
|
||||
#define PCIC_IOCTL_IO1_DATASIZE_8BIT 0x00
|
||||
#define PCIC_IOCTL_IO0_WAITSTATE 0x08
|
||||
#define PCIC_IOCTL_IO0_ZEROWAIT 0x04
|
||||
#define PCIC_IOCTL_IO0_IOCS16SRC_MASK 0x02
|
||||
#define PCIC_IOCTL_IO0_IOCS16SRC_CARD 0x02
|
||||
#define PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE 0x00
|
||||
#define PCIC_IOCTL_IO0_DATASIZE_MASK 0x01
|
||||
#define PCIC_IOCTL_IO0_DATASIZE_16BIT 0x01
|
||||
#define PCIC_IOCTL_IO0_DATASIZE_8BIT 0x00
|
||||
|
||||
#define PCIC_IOADDR0_START_LSB 0x08
|
||||
#define PCIC_IOADDR0_START_MSB 0x09
|
||||
#define PCIC_IOADDR0_STOP_LSB 0x0A
|
||||
#define PCIC_IOADDR0_STOP_MSB 0x0B
|
||||
#define PCIC_IOADDR1_START_LSB 0x0C
|
||||
#define PCIC_IOADDR1_START_MSB 0x0D
|
||||
#define PCIC_IOADDR1_STOP_LSB 0x0E
|
||||
#define PCIC_IOADDR1_STOP_MSB 0x0F
|
||||
|
||||
/* memory registers */
|
||||
|
||||
/*
|
||||
* memory window addresses refer to bits A23-A12 of the ISA system memory
|
||||
* address. This is a shift of 12 bits. The LSB contains A19-A12, and the
|
||||
* MSB contains A23-A20, plus some other bits.
|
||||
*/
|
||||
|
||||
#define PCIC_MEM_WINS 5
|
||||
|
||||
#define PCIC_MEM_SHIFT 12
|
||||
#define PCIC_MEM_PAGESIZE (1<<PCIC_MEM_SHIFT)
|
||||
|
||||
#define PCIC_SYSMEM_ADDRX_SHIFT PCIC_MEM_SHIFT
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK 0x80
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT 0x80
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT 0x00
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT 0x40
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK 0x30
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK 0x0F
|
||||
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK 0xC0
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0 0x00
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1 0x40
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2 0x80
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3 0xC0
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK 0x0F
|
||||
|
||||
/*
|
||||
* The card side of a memory mapping consists of bits A19-A12 of the card
|
||||
* memory address in the LSB, and A25-A20 plus some other bits in the MSB.
|
||||
* Again, the shift is 12 bits.
|
||||
*/
|
||||
|
||||
#define PCIC_CARDMEM_ADDRX_SHIFT PCIC_MEM_SHIFT
|
||||
#define PCIC_CARDMEM_ADDRX_MSB_WP 0x80
|
||||
#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK 0x40
|
||||
#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR 0x40
|
||||
#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON 0x00
|
||||
#define PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK 0x3F
|
||||
|
||||
#define PCIC_SYSMEM_ADDR0_START_LSB 0x10
|
||||
#define PCIC_SYSMEM_ADDR0_START_MSB 0x11
|
||||
#define PCIC_SYSMEM_ADDR0_STOP_LSB 0x12
|
||||
#define PCIC_SYSMEM_ADDR0_STOP_MSB 0x13
|
||||
|
||||
#define PCIC_CARDMEM_ADDR0_LSB 0x14
|
||||
#define PCIC_CARDMEM_ADDR0_MSB 0x15
|
||||
|
||||
/* #define PCIC_RESERVED 0x17 */
|
||||
|
||||
#define PCIC_SYSMEM_ADDR1_START_LSB 0x18
|
||||
#define PCIC_SYSMEM_ADDR1_START_MSB 0x19
|
||||
#define PCIC_SYSMEM_ADDR1_STOP_LSB 0x1A
|
||||
#define PCIC_SYSMEM_ADDR1_STOP_MSB 0x1B
|
||||
|
||||
#define PCIC_CARDMEM_ADDR1_LSB 0x1C
|
||||
#define PCIC_CARDMEM_ADDR1_MSB 0x1D
|
||||
|
||||
#define PCIC_SYSMEM_ADDR2_START_LSB 0x20
|
||||
#define PCIC_SYSMEM_ADDR2_START_MSB 0x21
|
||||
#define PCIC_SYSMEM_ADDR2_STOP_LSB 0x22
|
||||
#define PCIC_SYSMEM_ADDR2_STOP_MSB 0x23
|
||||
|
||||
#define PCIC_CARDMEM_ADDR2_LSB 0x24
|
||||
#define PCIC_CARDMEM_ADDR2_MSB 0x25
|
||||
|
||||
/* #define PCIC_RESERVED 0x26 */
|
||||
/* #define PCIC_RESERVED 0x27 */
|
||||
|
||||
#define PCIC_SYSMEM_ADDR3_START_LSB 0x28
|
||||
#define PCIC_SYSMEM_ADDR3_START_MSB 0x29
|
||||
#define PCIC_SYSMEM_ADDR3_STOP_LSB 0x2A
|
||||
#define PCIC_SYSMEM_ADDR3_STOP_MSB 0x2B
|
||||
|
||||
#define PCIC_CARDMEM_ADDR3_LSB 0x2C
|
||||
#define PCIC_CARDMEM_ADDR3_MSB 0x2D
|
||||
|
||||
/* #define PCIC_RESERVED 0x2E */
|
||||
/* #define PCIC_RESERVED 0x2F */
|
||||
|
||||
#define PCIC_SYSMEM_ADDR4_START_LSB 0x30
|
||||
#define PCIC_SYSMEM_ADDR4_START_MSB 0x31
|
||||
#define PCIC_SYSMEM_ADDR4_STOP_LSB 0x32
|
||||
#define PCIC_SYSMEM_ADDR4_STOP_MSB 0x33
|
||||
|
||||
#define PCIC_CARDMEM_ADDR4_LSB 0x34
|
||||
#define PCIC_CARDMEM_ADDR4_MSB 0x35
|
||||
|
||||
/* #define PCIC_RESERVED 0x36 */
|
||||
/* #define PCIC_RESERVED 0x37 */
|
||||
/* #define PCIC_RESERVED 0x38 */
|
||||
/* #define PCIC_RESERVED 0x39 */
|
||||
/* #define PCIC_RESERVED 0x3A */
|
||||
/* #define PCIC_RESERVED 0x3B */
|
||||
/* #define PCIC_RESERVED 0x3C */
|
||||
/* #define PCIC_RESERVED 0x3D */
|
||||
/* #define PCIC_RESERVED 0x3E */
|
||||
/* #define PCIC_RESERVED 0x3F */
|
||||
|
||||
/* cardbus extensions - memory window page registers */
|
||||
|
||||
#define PCIC_MEMREG_WIN_SHIFT 24
|
||||
#define PCIC_SYSMEM_ADDR0_WIN 0x40
|
||||
#define PCIC_SYSMEM_ADDR1_WIN 0x41
|
||||
#define PCIC_SYSMEM_ADDR2_WIN 0x42
|
||||
#define PCIC_SYSMEM_ADDR3_WIN 0x43
|
||||
#define PCIC_SYSMEM_ADDR4_WIN 0x44
|
||||
|
||||
/* vendor-specific registers */
|
||||
|
||||
#define PCIC_INTEL_GLOBAL_CTL 0x1E /* RW */
|
||||
#define PCIC_INTEL_GLOBAL_CTL_RESERVED 0xF0
|
||||
#define PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE 0x08
|
||||
#define PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK 0x04
|
||||
#define PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE 0x02
|
||||
#define PCIC_INTEL_GLOBAL_CTL_POWERDOWN 0x01
|
||||
|
||||
#define PCIC_CIRRUS_MISC_CTL_2 0x1E
|
||||
#define PCIC_CIRRUS_MISC_CTL_2_SUSPEND 0x04
|
||||
|
||||
#define PCIC_CIRRUS_CHIP_INFO 0x1F
|
||||
#define PCIC_CIRRUS_CHIP_INFO_CHIP_ID 0xC0
|
||||
#define PCIC_CIRRUS_CHIP_INFO_SLOTS 0x20
|
||||
#define PCIC_CIRRUS_CHIP_INFO_REV 0x1F
|
||||
|
||||
#define PCIC_CIRRUS_EXTENDED_INDEX 0x2E
|
||||
#define PCIC_CIRRUS_EXTENDED_DATA 0x2F
|
||||
#define PCIC_CIRRUS_EXT_CONTROL_1 0x03
|
||||
#define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18
|
||||
|
||||
/* Plug and play */
|
||||
#define PCIC_PNP_ACTIONTEC 0x1802A904 /* AEI0218 */
|
||||
#define PCIC_PNP_IBM3765 0x65374d24 /* IBM3765 */
|
||||
#define PCIC_PNP_82365 0x000ED041 /* PNP0E00 */
|
||||
#define PCIC_PNP_CL_PD6720 0x010ED041 /* PNP0E01 */
|
||||
#define PCIC_PNP_VLSI_82C146 0x020ED041 /* PNP0E02 */
|
||||
#define PCIC_PNP_82365_CARDBUS 0x030ED041 /* PNP0E03 */
|
||||
#define PCIC_PNP_SCM_SWAPBOX 0x69046d4c /* SMC0469 */
|
||||
|
||||
/* C-Bus PnP Definitions */
|
||||
#define PCIC_NEC_PC9801_102 0x9180a3b8 /* NEC8091 PC-9801-102 */
|
||||
#define PCIC_NEC_PC9821RA_E01 0x2181a3b8 /* NEC8121 PC-9821RA-E01 */
|
||||
@ -1,168 +0,0 @@
|
||||
/* $NetBSD: i82365var.h,v 1.8 1999/10/15 06:07:27 haya Exp $ */
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Marc Horowitz. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Marc Horowitz.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <dev/pccard/pccardreg.h>
|
||||
|
||||
#include <dev/pcic/i82365reg.h>
|
||||
|
||||
struct proc;
|
||||
|
||||
struct pcic_event {
|
||||
STAILQ_ENTRY(pcic_event) pe_q;
|
||||
int pe_type;
|
||||
};
|
||||
|
||||
/* pe_type */
|
||||
#define PCIC_EVENT_INSERTION 0
|
||||
#define PCIC_EVENT_REMOVAL 1
|
||||
|
||||
struct proc;
|
||||
|
||||
struct pcic_handle {
|
||||
void *sc;
|
||||
device_t dev;
|
||||
bus_space_tag_t ph_bus_t; /* I/O or MEM? I don't mind */
|
||||
bus_space_handle_t ph_bus_h;
|
||||
u_int8_t (*ph_read)(struct pcic_handle*, int);
|
||||
void (*ph_write)(struct pcic_handle *, int, u_int8_t);
|
||||
|
||||
int vendor;
|
||||
int sock;
|
||||
int flags;
|
||||
int laststate;
|
||||
int memalloc;
|
||||
struct pccard_mem_handle mem[PCIC_MEM_WINS]; /* XXX BAD XXX */
|
||||
int ioalloc;
|
||||
struct pccard_io_handle io[PCIC_IO_WINS]; /* XXX BAD XXX */
|
||||
int ih_irq;
|
||||
|
||||
int shutdown;
|
||||
struct proc *event_thread;
|
||||
STAILQ_HEAD(, pcic_event) events;
|
||||
};
|
||||
|
||||
#define PCIC_FLAG_SOCKETP 0x0001
|
||||
#define PCIC_FLAG_CARDP 0x0002
|
||||
|
||||
#define PCIC_LASTSTATE_PRESENT 0x0002
|
||||
#define PCIC_LASTSTATE_HALF 0x0001
|
||||
#define PCIC_LASTSTATE_EMPTY 0x0000
|
||||
|
||||
#define C0SA PCIC_CHIP0_BASE+PCIC_SOCKETA_INDEX
|
||||
#define C0SB PCIC_CHIP0_BASE+PCIC_SOCKETB_INDEX
|
||||
#define C1SA PCIC_CHIP1_BASE+PCIC_SOCKETA_INDEX
|
||||
#define C1SB PCIC_CHIP1_BASE+PCIC_SOCKETB_INDEX
|
||||
|
||||
/*
|
||||
* This is sort of arbitrary. It merely needs to be "enough". It can be
|
||||
* overridden in the conf file, anyway.
|
||||
*/
|
||||
|
||||
#define PCIC_MEM_PAGES 4
|
||||
#define PCIC_MEMSIZE PCIC_MEM_PAGES*PCIC_MEM_PAGESIZE
|
||||
|
||||
#define PCIC_NSLOTS 4
|
||||
|
||||
struct pcic_softc {
|
||||
device_t dev;
|
||||
|
||||
bus_space_tag_t memt;
|
||||
bus_space_handle_t memh;
|
||||
bus_space_tag_t iot;
|
||||
bus_space_handle_t ioh;
|
||||
|
||||
void *intrhand;
|
||||
struct resource *irq_res;
|
||||
int irq_rid;
|
||||
struct resource *mem_res;
|
||||
int mem_rid;
|
||||
struct resource *port_res;
|
||||
int port_rid;
|
||||
|
||||
#define PCIC_MAX_MEM_PAGES (8 * sizeof(int))
|
||||
|
||||
/* used by memory window mapping functions */
|
||||
bus_addr_t membase;
|
||||
|
||||
/*
|
||||
* used by io window mapping functions. These can actually overlap
|
||||
* with another pcic, since the underlying extent mapper will deal
|
||||
* with individual allocations. This is here to deal with the fact
|
||||
* that different busses have different real widths (different pc
|
||||
* hardware seems to use 10 or 12 bits for the I/O bus).
|
||||
*/
|
||||
bus_addr_t iobase;
|
||||
bus_addr_t iosize;
|
||||
|
||||
int irq;
|
||||
void *ih;
|
||||
|
||||
struct pcic_handle handle[PCIC_NSLOTS];
|
||||
};
|
||||
|
||||
|
||||
int pcic_ident_ok(int);
|
||||
int pcic_vendor(struct pcic_handle *);
|
||||
char *pcic_vendor_to_string(int);
|
||||
|
||||
int pcic_attach(device_t dev);
|
||||
|
||||
#define pcic_read(h, idx) (*(h)->ph_read)((h), (idx))
|
||||
#define pcic_write(h, idx, data) (*(h)->ph_write)((h), (idx), (data))
|
||||
|
||||
/*
|
||||
* bus/device/etc routines
|
||||
*/
|
||||
int pcic_activate_resource(device_t dev, device_t child, int type, int rid,
|
||||
struct resource *r);
|
||||
struct resource *pcic_alloc_resource(device_t dev, device_t child, int type,
|
||||
int *rid, u_long start, u_long end, u_long count, u_int flags);
|
||||
void pcic_deactivate(device_t dev);
|
||||
int pcic_deactivate_resource(device_t dev, device_t child, int type, int rid,
|
||||
struct resource *r);
|
||||
int pcic_detach(device_t dev);
|
||||
int pcic_release_resource(device_t dev, device_t child, int type, int rid,
|
||||
struct resource *r);
|
||||
int pcic_setup_intr(device_t dev, device_t child, struct resource *irq,
|
||||
int flags, driver_intr_t intr, void *arg, void **cookiep);
|
||||
int pcic_teardown_intr(device_t dev, device_t child, struct resource *irq,
|
||||
void *cookiep);
|
||||
int pcic_suspend(device_t dev);
|
||||
int pcic_resume(device_t dev);
|
||||
int pcic_enable_socket(device_t dev, device_t child);
|
||||
int pcic_disable_socket(device_t dev, device_t child);
|
||||
int pcic_set_res_flags(device_t dev, device_t child, int type, int rid,
|
||||
u_int32_t flags);
|
||||
int pcic_set_memory_offset(device_t dev, device_t child, int rid,
|
||||
u_int32_t offset, u_int32_t *deltap);
|
||||
|
||||
#define PCIC_SOFTC(d) (struct pcic_softc *) device_get_softc(d)
|
||||
Loading…
Reference in New Issue
Block a user