- Support for multiple PD6832 controllers. Each found 6832 is assigned
and initializes the next two ports in order starting at 03e0. This also patches pcic_p.h to reduce the I/O ports mapped from 4 to 2. Submitted by: Ted Faber <faber@ISI.EDU>
This commit is contained in:
Nate Williams
parent
a798ce2eac
commit
a9b9e46550
@ -37,6 +37,7 @@
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <pci/pcic_p.h>
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#include <pccard/i82365.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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@ -134,6 +135,19 @@ pd6832_legacy_init(pcici_t tag, int unit)
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{
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u_long bcr; /* to set interrupts */
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u_short io_port; /* the io_port to map this slot on */
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static int num6832 = 0; /* The number of 6832s initialized */
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/*
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* Some BIOS leave the legacy address uninitialized. This
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* insures that the PD6832 puts itself where the driver will
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* look. We assume that multiple 6832's should be laid out
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* sequentially. We only initialize the first socket's legacy port,
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* the other is a dummy.
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*/
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io_port = PCIC_INDEX_0 + num6832 * CLPD6832_NUM_REGS;
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if (unit == 0)
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pci_conf_write(tag, CLPD6832_LEGACY_16BIT_IOADDR,
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io_port & ~PCI_MAP_IO);
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/*
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* I think this should be a call to pci_map_port, but that
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@ -152,7 +166,7 @@ pd6832_legacy_init(pcici_t tag, int unit)
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pci_conf_write(tag, CLPD6832_IO_LIMIT0,
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(io_port + CLPD6832_NUM_REGS) | 1);
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pci_conf_write(tag, CLPD6832_IO_BASE1, (io_port +0x20) | 1);
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pci_conf_write(tag, CLPD6832_IO_BASE1, (io_port + 0x20) | 1);
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pci_conf_write(tag, CLPD6832_IO_LIMIT1, io_port | 1 );
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/*
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@ -170,8 +184,12 @@ pd6832_legacy_init(pcici_t tag, int unit)
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bcr |= (CLPD6832_BCR_ISA_IRQ|CLPD6832_BCR_MGMT_IRQ_ENA);
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pci_conf_write(tag, CLPD6832_BRIDGE_CONTROL, bcr);
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/* After initializing 2 sockets, the chip is fully configured */
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if (unit == 1)
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num6832++;
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if (bootverbose)
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printf("CardBus: Legacy PC-card 16bit I/O address [0x%x]\n",
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io_port);
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io_port);
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}
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#endif /* NPCI > 0 */
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@ -26,7 +26,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id$
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* $Id: pcic_p.h,v 1.2 1997/12/02 22:13:59 nate Exp $
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*/
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/* PCI/CardBus Device IDs */
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@ -49,6 +49,6 @@
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#define CLPD6832_BCR_MGMT_IRQ_ENA 0x08000000
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#define CLPD6832_BCR_ISA_IRQ 0x00800000
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#define CLPD6832_COMMAND_DEFAULTS 0x00000045
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#define CLPD6832_NUM_REGS 4
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#define CLPD6832_NUM_REGS 2
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/* End of CL-PD6832 defines */
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@ -37,6 +37,7 @@
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <pci/pcic_p.h>
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#include <pccard/i82365.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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@ -134,6 +135,19 @@ pd6832_legacy_init(pcici_t tag, int unit)
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{
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u_long bcr; /* to set interrupts */
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u_short io_port; /* the io_port to map this slot on */
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static int num6832 = 0; /* The number of 6832s initialized */
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/*
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* Some BIOS leave the legacy address uninitialized. This
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* insures that the PD6832 puts itself where the driver will
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* look. We assume that multiple 6832's should be laid out
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* sequentially. We only initialize the first socket's legacy port,
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* the other is a dummy.
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*/
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io_port = PCIC_INDEX_0 + num6832 * CLPD6832_NUM_REGS;
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if (unit == 0)
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pci_conf_write(tag, CLPD6832_LEGACY_16BIT_IOADDR,
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io_port & ~PCI_MAP_IO);
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/*
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* I think this should be a call to pci_map_port, but that
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@ -152,7 +166,7 @@ pd6832_legacy_init(pcici_t tag, int unit)
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pci_conf_write(tag, CLPD6832_IO_LIMIT0,
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(io_port + CLPD6832_NUM_REGS) | 1);
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pci_conf_write(tag, CLPD6832_IO_BASE1, (io_port +0x20) | 1);
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pci_conf_write(tag, CLPD6832_IO_BASE1, (io_port + 0x20) | 1);
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pci_conf_write(tag, CLPD6832_IO_LIMIT1, io_port | 1 );
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/*
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@ -170,8 +184,12 @@ pd6832_legacy_init(pcici_t tag, int unit)
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bcr |= (CLPD6832_BCR_ISA_IRQ|CLPD6832_BCR_MGMT_IRQ_ENA);
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pci_conf_write(tag, CLPD6832_BRIDGE_CONTROL, bcr);
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/* After initializing 2 sockets, the chip is fully configured */
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if (unit == 1)
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num6832++;
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if (bootverbose)
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printf("CardBus: Legacy PC-card 16bit I/O address [0x%x]\n",
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io_port);
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io_port);
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}
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#endif /* NPCI > 0 */
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@ -26,7 +26,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id$
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* $Id: pcic_p.h,v 1.2 1997/12/02 22:13:59 nate Exp $
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*/
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/* PCI/CardBus Device IDs */
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@ -49,6 +49,6 @@
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#define CLPD6832_BCR_MGMT_IRQ_ENA 0x08000000
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#define CLPD6832_BCR_ISA_IRQ 0x00800000
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#define CLPD6832_COMMAND_DEFAULTS 0x00000045
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#define CLPD6832_NUM_REGS 4
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#define CLPD6832_NUM_REGS 2
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/* End of CL-PD6832 defines */
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