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bhnd: clean up empty lines in .c and .h files

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This commit is contained in:
Mateusz Guzik 2020-09-01 21:43:05 +00:00
parent b410de8ad2
commit ab3fad6ea2
83 changed files with 199 additions and 393 deletions
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15
sys/dev/bhnd/bcma/bcma.c
View File

@ -140,10 +140,10 @@ bcma_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
{
const struct bcma_devinfo *dinfo;
const struct bhnd_core_info *ci;
dinfo = device_get_ivars(child);
ci = &dinfo->corecfg->core_info;
switch (index) {
case BHND_IVAR_VENDOR:
*result = ci->vendor;
@ -500,7 +500,7 @@ bcma_get_region_count(device_t dev, device_t child, bhnd_port_type type,
dinfo = device_get_ivars(child);
ports = bcma_corecfg_get_port_list(dinfo->corecfg, type);
STAILQ_FOREACH(port, ports, sp_link) {
if (port->sp_num == port_num)
return (port->sp_num_maps);
@ -518,7 +518,7 @@ bcma_get_port_rid(device_t dev, device_t child, bhnd_port_type port_type,
struct bcma_map *map;
struct bcma_sport_list *ports;
struct bcma_sport *port;
dinfo = device_get_ivars(child);
ports = bcma_corecfg_get_port_list(dinfo->corecfg, port_type);
@ -584,7 +584,7 @@ bcma_get_region_addr(device_t dev, device_t child, bhnd_port_type port_type,
struct bcma_map *map;
struct bcma_sport_list *ports;
struct bcma_sport *port;
dinfo = device_get_ivars(child);
ports = bcma_corecfg_get_port_list(dinfo->corecfg, port_type);
@ -710,7 +710,7 @@ bcma_add_children(device_t bus)
/* EOF while parsing cores is expected */
if (error == ENOENT)
error = 0;
cleanup:
bhnd_erom_free(erom);
@ -723,13 +723,12 @@ bcma_add_children(device_t bus)
return (error);
}
static device_method_t bcma_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, bcma_probe),
DEVMETHOD(device_attach, bcma_attach),
DEVMETHOD(device_detach, bcma_detach),
/* Bus interface */
DEVMETHOD(bus_add_child, bcma_add_child),
DEVMETHOD(bus_child_deleted, bcma_child_deleted),

6
sys/dev/bhnd/bcma/bcma_bhndb.c
View File

@ -99,7 +99,7 @@ bcma_bhndb_suspend_child(device_t dev, device_t child)
if (device_get_parent(child) != dev)
BUS_SUSPEND_CHILD(device_get_parent(dev), child);
if (device_is_suspended(child))
return (EBUSY);
@ -113,7 +113,7 @@ bcma_bhndb_suspend_child(device_t dev, device_t child)
if (dinfo->res_agent != NULL)
BHNDB_SUSPEND_RESOURCE(device_get_parent(dev), dev,
SYS_RES_MEMORY, dinfo->res_agent->res);
return (0);
}
@ -169,7 +169,7 @@ DEFINE_CLASS_2(bhnd, bcma_bhndb_driver, bcma_bhndb_methods,
sizeof(struct bcma_softc), bhnd_bhndb_driver, bcma_driver);
DRIVER_MODULE(bcma_bhndb, bhndb, bcma_bhndb_driver, bhnd_devclass, NULL, NULL);
MODULE_VERSION(bcma_bhndb, 1);
MODULE_DEPEND(bcma_bhndb, bcma, 1, 1, 1);
MODULE_DEPEND(bcma_bhndb, bhnd, 1, 1, 1);

1
sys/dev/bhnd/bcma/bcma_dmp.h
View File

@ -219,7 +219,6 @@
#define BCMA_DMP_COMPONENTID2 0xff8
#define BCMA_DMP_COMPONENTID3 0xffc
/* OOBSEL(IN|OUT) */
#define BCMA_DMP_OOBSEL_MASK 0xFF /**< OOB selector mask */
#define BCMA_DMP_OOBSEL_EN (1<<7) /**< OOB selector enable bit */

25
sys/dev/bhnd/bcma/bcma_erom.c
View File

@ -79,7 +79,6 @@ static int bcma_erom_seek_next(struct bcma_erom *erom,
static int bcma_erom_region_to_port_type(struct bcma_erom *erom,
uint8_t region_type, bhnd_port_type *port_type);
static int bcma_erom_peek32(struct bcma_erom *erom,
uint32_t *entry);
@ -302,7 +301,7 @@ bcma_erom_lookup_core_addr(bhnd_erom_t *erom, const struct bhnd_core_match *desc
/* Otherwise, seek to next block of region records */
while (1) {
uint8_t next_type, next_port;
if ((error = bcma_erom_skip_sport_region(sc)))
return (error);
@ -676,7 +675,7 @@ bcma_erom_seek_matching_core(struct bcma_erom *sc,
/* Save the core offset */
core_offset = bcma_erom_tell(sc);
/* Parse the core */
if ((error = bcma_erom_parse_core(sc, &ec)))
return (error);
@ -744,11 +743,11 @@ bcma_erom_parse_core(struct bcma_erom *erom, struct bcma_erom_core *core)
/* Parse CoreDescA */
if ((error = bcma_erom_read32(erom, &entry)))
return (error);
/* Handle EOF */
if (entry == BCMA_EROM_TABLE_EOF)
return (ENOENT);
if (!BCMA_EROM_ENTRY_IS(entry, CORE)) {
EROM_LOG(erom, "Unexpected EROM entry 0x%x (type=%s)\n",
entry, bcma_erom_entry_type_name(entry));
@ -758,7 +757,7 @@ bcma_erom_parse_core(struct bcma_erom *erom, struct bcma_erom_core *core)
core->vendor = BCMA_EROM_GET_ATTR(entry, COREA_DESIGNER);
core->device = BCMA_EROM_GET_ATTR(entry, COREA_ID);
/* Parse CoreDescB */
if ((error = bcma_erom_read32(erom, &entry)))
return (error);
@ -794,7 +793,7 @@ bcma_erom_parse_mport(struct bcma_erom *erom, struct bcma_erom_mport *mport)
/* Parse the master port descriptor */
if ((error = bcma_erom_read32(erom, &entry)))
return (error);
if (!BCMA_EROM_ENTRY_IS(entry, MPORT))
return (EINVAL);
@ -957,7 +956,7 @@ bcma_erom_corecfg_fill_port_regions(struct bcma_erom *erom,
/* Fetch the list to be populated */
sports = bcma_corecfg_get_port_list(corecfg, port_type);
/* Allocate a new port descriptor */
sport = bcma_alloc_sport(port_num, port_type);
if (sport == NULL)
@ -1109,7 +1108,7 @@ bcma_erom_next_corecfg(struct bcma_erom *erom, struct bcma_corecfg **result)
core.device, core.rev);
if (cfg == NULL)
return (ENOMEM);
/* These are 5-bit values in the EROM table, and should never be able
* to overflow BCMA_PID_MAX. */
KASSERT(core.num_mport <= BCMA_PID_MAX, ("unsupported mport count"));
@ -1135,7 +1134,7 @@ bcma_erom_next_corecfg(struct bcma_erom *erom, struct bcma_corecfg **result)
for (uint8_t i = 0; i < core.num_mport; i++) {
struct bcma_mport *mport;
struct bcma_erom_mport mpd;
/* Parse the master port descriptor */
error = bcma_erom_parse_mport(erom, &mpd);
if (error)
@ -1154,7 +1153,6 @@ bcma_erom_next_corecfg(struct bcma_erom *erom, struct bcma_corecfg **result)
/* Update dinfo */
STAILQ_INSERT_TAIL(&cfg->master_ports, mport, mp_link);
}
/*
* Determine whether this is a bridge device; if so, we can
@ -1184,7 +1182,7 @@ bcma_erom_next_corecfg(struct bcma_erom *erom, struct bcma_corecfg **result)
cfg->num_bridge_ports = 0;
}
}
/* Device/bridge port descriptors */
for (uint8_t sp_num = 0; sp_num < core.num_dport; sp_num++) {
error = bcma_erom_corecfg_fill_port_regions(erom, cfg, sp_num,
@ -1203,7 +1201,6 @@ bcma_erom_next_corecfg(struct bcma_erom *erom, struct bcma_corecfg **result)
goto failed;
}
/* Wrapper (aka device management) descriptors (for slave ports). */
for (uint8_t i = 0; i < core.num_swrap; i++) {
/* Slave wrapper ports are not numbered distinctly from master
@ -1250,7 +1247,7 @@ bcma_erom_next_corecfg(struct bcma_erom *erom, struct bcma_corecfg **result)
*result = cfg;
return (0);
failed:
if (cfg != NULL)
bcma_free_corecfg(cfg);

1
sys/dev/bhnd/bcma/bcma_eromreg.h
View File

@ -105,7 +105,6 @@
#define BCMA_EROM_MPORT_ID_MASK 0x000000F0 /* AXI master ID (unique per master). */
#define BCMA_EROM_MPORT_ID_SHIFT 4
/* EROM Slave Port MMIO Region Descriptor */
#define BCMA_EROM_REGION_BASE_MASK 0xFFFFF000 /* region base address */
#define BCMA_EROM_REGION_BASE_SHIFT 0

20
sys/dev/bhnd/bcma/bcma_subr.c
View File

@ -81,7 +81,7 @@ bcma_alloc_corecfg(u_int core_index, int core_unit, uint16_t vendor,
.core_idx = core_index,
.unit = core_unit
};
STAILQ_INIT(&cfg->master_ports);
cfg->num_master_ports = 0;
@ -111,7 +111,7 @@ bcma_free_corecfg(struct bcma_corecfg *corecfg)
STAILQ_FOREACH_SAFE(mport, &corecfg->master_ports, mp_link, mnext) {
free(mport, M_BHND);
}
STAILQ_FOREACH_SAFE(sport, &corecfg->dev_ports, sp_link, snext) {
bcma_free_sport(sport);
}
@ -119,7 +119,7 @@ bcma_free_corecfg(struct bcma_corecfg *corecfg)
STAILQ_FOREACH_SAFE(sport, &corecfg->bridge_ports, sp_link, snext) {
bcma_free_sport(sport);
}
STAILQ_FOREACH_SAFE(sport, &corecfg->wrapper_ports, sp_link, snext) {
bcma_free_sport(sport);
}
@ -198,8 +198,6 @@ bcma_dinfo_init_port_resource_info(device_t bus, struct bcma_devinfo *dinfo,
}
}
/**
* Allocate the per-core agent register block for a device info structure.
*
@ -297,7 +295,7 @@ bcma_dinfo_init_intrs(device_t bus, device_t child,
if (dinfo->num_intrs == UINT_MAX)
return (ENOMEM);
selout = bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_OOBSELOUT(
BCMA_OOB_BANK_INTR, sel));
@ -330,7 +328,7 @@ struct bcma_devinfo *
bcma_alloc_dinfo(device_t bus)
{
struct bcma_devinfo *dinfo;
dinfo = malloc(sizeof(struct bcma_devinfo), M_BHND, M_NOWAIT|M_ZERO);
if (dinfo == NULL)
return (NULL);
@ -406,7 +404,7 @@ bcma_init_dinfo(device_t bus, device_t child, struct bcma_devinfo *dinfo,
}
intr->i_mapped = true;
/* Add to resource list */
intr->i_rid = resource_list_add_next(&dinfo->resources,
SYS_RES_IRQ, intr->i_irq, intr->i_irq, 1);
@ -459,7 +457,6 @@ bcma_free_dinfo(device_t bus, device_t child, struct bcma_devinfo *dinfo)
free(dinfo, M_BHND);
}
/**
* Allocate and initialize a new interrupt descriptor.
*
@ -517,11 +514,11 @@ struct bcma_sport *
bcma_alloc_sport(bcma_pid_t port_num, bhnd_port_type port_type)
{
struct bcma_sport *sport;
sport = malloc(sizeof(struct bcma_sport), M_BHND, M_NOWAIT);
if (sport == NULL)
return NULL;
sport->sp_num = port_num;
sport->sp_type = port_type;
sport->sp_num_maps = 0;
@ -546,7 +543,6 @@ bcma_free_sport(struct bcma_sport *sport) {
free(sport, M_BHND);
}
/**
* Given a bcma(4) child's device info, spin waiting for the device's DMP
* resetstatus register to clear.

6
sys/dev/bhnd/bcma/bcmavar.h
View File

@ -62,7 +62,6 @@
#define BCMA_DINFO_COREIDX(_dinfo) \
((_dinfo)->corecfg->core_info.core_idx)
/** BCMA port identifier. */
typedef u_int bcma_pid_t;
#define BCMA_PID_MAX UINT_MAX /**< Maximum bcma_pid_t value */
@ -165,10 +164,10 @@ struct bcma_corecfg {
u_long num_dev_ports; /**< number of device slave port descriptors. */
struct bcma_sport_list dev_ports; /**< device port descriptors */
u_long num_bridge_ports; /**< number of bridge slave port descriptors. */
struct bcma_sport_list bridge_ports; /**< bridge port descriptors */
u_long num_wrapper_ports; /**< number of wrapper slave port descriptors. */
struct bcma_sport_list wrapper_ports; /**< wrapper port descriptors */
};
@ -190,7 +189,6 @@ struct bcma_devinfo {
void *pmu_info; /**< Bus-managed PMU state, or NULL */
};
/** BMCA per-instance state */
struct bcma_softc {
struct bhnd_softc bhnd_sc; /**< bhnd state */

15
sys/dev/bhnd/bhnd.c
View File

@ -90,7 +90,6 @@ static const struct bhnd_nomatch {
{ BHND_MFGID_ARM, BHND_COREID_PL301, true },
{ BHND_MFGID_ARM, BHND_COREID_APB_BRIDGE, true },
{ BHND_MFGID_ARM, BHND_COREID_AXI_UNMAPPED, false },
{ BHND_MFGID_INVALID, BHND_COREID_INVALID, false }
};
@ -491,7 +490,7 @@ bhnd_generic_release_pmu(device_t dev, device_t child)
device_t pmu_dev;
GIANT_REQUIRED; /* for newbus */
sc = device_get_softc(dev);
if (device_get_parent(child) != dev)
@ -756,7 +755,6 @@ bhnd_generic_release_ext_rsrc(device_t dev, device_t child, u_int rsrc)
if ((clkctl = bhnd_get_pmu_info(child)) == NULL)
panic("no active PMU allocation");
BHND_ASSERT_CLKCTL_AVAIL(clkctl);
sc = device_get_softc(dev);
@ -844,8 +842,7 @@ bhnd_generic_print_child(device_t dev, device_t child)
retval += bus_print_child_header(dev, child);
rl = BUS_GET_RESOURCE_LIST(dev, child);
if (rl != NULL) {
retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY,
"%#jx");
@ -889,7 +886,7 @@ bhnd_generic_probe_nomatch(device_t dev, device_t child)
report = true;
break;
}
if (!report)
return;
@ -935,13 +932,12 @@ bhnd_child_location_str(device_t dev, device_t child, char *buf,
{
bhnd_addr_t addr;
bhnd_size_t size;
if (device_get_parent(child) != dev) {
return (BUS_CHILD_LOCATION_STR(device_get_parent(dev), child,
buf, buflen));
}
if (bhnd_get_region_addr(child, BHND_PORT_DEVICE, 0, 0, &addr, &size)) {
/* No device default port/region */
if (buflen > 0)
@ -1010,7 +1006,6 @@ bhnd_generic_resume_child(device_t dev, device_t child)
return bus_generic_resume_child(dev, child);
}
/**
* Default bhnd(4) bus driver implementation of BUS_SETUP_INTR().
*
@ -1176,7 +1171,7 @@ static device_method_t bhnd_methods[] = {
DEVMETHOD(bhnd_bus_write_multi_1, bhnd_write_multi_1),
DEVMETHOD(bhnd_bus_write_multi_2, bhnd_write_multi_2),
DEVMETHOD(bhnd_bus_write_multi_4, bhnd_write_multi_4),
DEVMETHOD(bhnd_bus_read_multi_stream_1, bhnd_read_multi_stream_1),
DEVMETHOD(bhnd_bus_read_multi_stream_2, bhnd_read_multi_stream_2),
DEVMETHOD(bhnd_bus_read_multi_stream_4, bhnd_read_multi_stream_4),

7
sys/dev/bhnd/bhnd.h
View File

@ -108,7 +108,6 @@ enum {
};
/**
* Per-core IOCTL flags common to all bhnd(4) cores.
*/
@ -207,7 +206,6 @@ struct bhnd_board_info {
uint32_t board_flags3; /**< Board flags 3 (see BHND_BFL3_*) */
};
/**
* Chip Identification
*
@ -307,7 +305,6 @@ struct bhnd_dma_translation {
*/
uint32_t flags;
};
#define BHND_DMA_TRANSLATION_TABLE_END { 0, 0, 0, 0 }
#define BHND_DMA_IS_TRANSLATION_TABLE_END(_dt) \
@ -377,7 +374,6 @@ struct bhnd_device_quirk {
#define BHND_BOARD_QUIRK(_board, _flags) \
{{ BHND_MATCH_BOARD_TYPE(_board) }, \
(_flags) }
#define BHND_DEVICE_QUIRK_END { { BHND_MATCH_ANY }, 0 }
#define BHND_DEVICE_QUIRK_IS_END(_q) \
(((_q)->desc.m.match_flags == 0) && (_q)->quirks == 0)
@ -409,7 +405,6 @@ struct bhnd_device {
#define BHND_DEVICE(_vendor, _device, _desc, _quirks, ...) \
_BHND_DEVICE(_vendor, _device, _desc, _quirks, \
## __VA_ARGS__, 0)
#define BHND_DEVICE_END { { BHND_MATCH_ANY }, NULL, NULL, 0 }
#define BHND_DEVICE_IS_END(_d) \
(BHND_MATCH_IS_ANY(&(_d)->core) && (_d)->desc == NULL)
@ -764,7 +759,6 @@ bhnd_get_chipid(device_t dev) {
return (BHND_BUS_GET_CHIPID(device_get_parent(dev), dev));
};
/**
* Read the current value of a bhnd(4) device's per-core I/O control register.
*
@ -1310,7 +1304,6 @@ bhnd_alloc_resource(device_t dev, int type, int *rid, rman_res_t start,
start, end, count, flags);
}
/**
* Allocate a resource from a device's parent bhnd(4) bus, using the
* resource's default start, end, and count values.

1
sys/dev/bhnd/bhnd_debug.h
View File

@ -108,7 +108,6 @@
} while(0);
#endif /* BHND_LOGGING > BHND_INFO_LEVEL */
#define _BHND_RAWPRINTFN printf(
#define _BHND_DEVPRINTFN(dev) device_printf(dev,

1
sys/dev/bhnd/bhnd_erom.c
View File

@ -312,7 +312,6 @@ bhnd_erom_read_chipid(struct bhnd_erom_io *eio, struct bhnd_chipid *cid)
return (0);
}
/**
* Attempt to map @p size bytes at @p addr, replacing any existing
* @p eio mapping.

1
sys/dev/bhnd/bhnd_erom.h
View File

@ -90,7 +90,6 @@ struct bhnd_erom {
KOBJ_FIELDS;
};
/** Number of additional bytes to reserve for statically allocated
* bhnd_erom instances. */
#define BHND_EROM_STATIC_BYTES 64

2
sys/dev/bhnd/bhnd_eromvar.h
View File

@ -59,11 +59,9 @@ typedef uint32_t (bhnd_erom_io_read_t)(struct bhnd_erom_io *eio,
/** @see bhnd_erom_io_fini() */
typedef void (bhnd_erom_io_fini_t)(struct bhnd_erom_io *eio);
int bhnd_erom_read_chipid(struct bhnd_erom_io *eio,
struct bhnd_chipid *cid);
/**
* Abstract EROM bus I/O support.
*/

20
sys/dev/bhnd/bhnd_ids.h
View File

@ -67,7 +67,6 @@
*/
#define OCP_VENDOR_BCM 0x4243 /**< Broadcom OCP vendor id */
/* PCI vendor IDs */
#define PCI_VENDOR_ASUSTEK 0x1043
#define PCI_VENDOR_EPIGRAM 0xfeda
@ -88,15 +87,12 @@
#define PCI_VENDOR_RICOH 0x1180 /* Ricoh */
#define PCI_VENDOR_JMICRON 0x197b
/* PCMCIA vendor IDs */
#define PCMCIA_VENDOR_BROADCOM 0x02d0
/* SDIO vendor IDs */
#define SDIO_VENDOR_BROADCOM 0x00BF
/* USB dongle VID/PIDs */
#define USB_VID_BROADCOM 0x0a5c
#define USB_PID_BCM4328 0xbd12
@ -119,11 +115,9 @@
#define USB_PID_BCM_DNGL_BDC 0x0bdc /* BDC USB device controller IP? */
#define USB_PID_BCM_DNGL_JTAG 0x4a44
/* HW USB BLOCK [CPULESS USB] PIDs */
#define USB_PID_CCM_HWUSB_43239 43239
/* PCI Device IDs */
#define PCI_DEVID_BCM4210 0x1072 /* never used */
#define PCI_DEVID_BCM4230 0x1086 /* never used */
@ -228,14 +222,12 @@
#define PCI_DEVID_PCIXX21_FLASHMEDIA0 0x8033 /* TI PCI xx21 Standard Host Controller */
#define PCI_DEVID_PCIXX21_SDIOH0 0x8034 /* TI PCI xx21 Standard Host Controller */
/* PCI Subsystem Vendor IDs */
#define PCI_SUBVENDOR_BCM943228HMB 0x0607
#define PCI_SUBVENDOR_BCM94313HMGBL 0x0608
#define PCI_SUBVENDOR_BCM94313HMG 0x0609
#define PCI_SUBVENDOR_BCM943142HM 0x0611
/* PCI Subsystem Device IDs */
#define PCI_SUBDEVID_BCM43143_D11N2G 0x4366 /* 43143 802.11n 2.4G device */
@ -296,7 +288,6 @@
#define PCI_SUBDEVID_BCM_R5C822_SDIOH 0x0822 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */
#define PCI_SUBDEVID_BCM_JMICRON_SDIOH 0x2381 /* JMicron Standard SDIO Host Controller */
/* Broadcom ChipCommon Chip IDs */
#define BHND_CHIPID_BCM4306 0x4306 /* 4306 chipcommon chipid */
#define BHND_CHIPID_BCM4311 0x4311 /* 4311 PCIe 802.11a/b/g */
@ -381,7 +372,6 @@
#define BHND_CHIPID_BCM5357 0x5357 /* 5357 chipcommon chipid */
#define BHND_CHIPID_BCM53572 53572 /* 53572 chipcommon chipid */
/* Broadcom ChipCommon Package IDs */
#define BHND_PKGID_BCM4303 2 /* 4303 package id */
#define BHND_PKGID_BCM4309 1 /* 4309 package id */
@ -522,8 +512,6 @@
#define BHND_COREID_4706_GMAC 0x52d /* Gigabit MAC core */
#define BHND_COREID_AMEMC 0x52e /* DDR1/2 cadence/denali memory controller core */
/* ARM PrimeCell Peripherial IDs. These were derived from inspection of the
* PrimeCell-compatible BCM4331 cores, but due to lack of documentation, the
* surmised core name/description may be incorrect. */
@ -593,7 +581,6 @@
*/
#define BHND_BFL_EXTLNA_TX 0x20000000 /* Temp boardflag to indicate to */
/* Boardflags2 */
#define BHND_BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
#define BHND_BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
@ -642,7 +629,6 @@
#define BHND_BFL2_LNA1BYPFORTR2G 0x40000000 /* acphy, enable lna1 bypass for clip gain, 2g */
#define BHND_BFL2_LNA1BYPFORTR5G 0x80000000 /* acphy, enable lna1 bypass for clip gain, 5g */
/* SROM 11 - 11ac boardflag definitions */
#define BHND_BFL_SROM11_BTCOEX 0x00000001 /* Board supports BTCOEX */
#define BHND_BFL_SROM11_WLAN_BT_SH_XTL 0x00000002 /* bluetooth and wlan share same crystal */
@ -653,7 +639,6 @@
#define BHND_BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */
#define BHND_BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */
/* Boardflags3 */
#define BHND_BFL3_FEMCTRL_SUB 0x00000007 /* acphy, subrevs of femctrl on top of srom_femctrl */
#define BHND_BFL3_RCAL_WAR 0x00000008 /* acphy, rcal war active on this board (4335a0) */
@ -680,7 +665,6 @@
#define BHND_BFL3_EN_NONBRCM_TXBF 0x10000000 /* acphy, enable non-brcm TXBF */
#define BHND_BFL3_EN_P2PLINK_TXBF 0x20000000 /* acphy, enable TXBF in p2p links */
/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
#define BHND_GPIO_BOARD_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */
#define BHND_GPIO_BOARD_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */
@ -730,7 +714,6 @@
#define BHND_BOARD_BU2050 0x041f
#define BHND_BOARD_BCM94309G 0x0421
#define BHND_BOARD_BU4704 0x0423
@ -738,7 +721,6 @@
#define BHND_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */
#define BHND_BOARD_BCM94702MN 0x0428
/* BCM4702 1U CompactPCI Board */
@ -762,8 +744,6 @@
/* 11a-only minipci */
#define BHND_BOARD_BCM94308MP 0x0430
#define BHND_BOARD_BU4712 0x0444
#define BHND_BOARD_BU4712SD 0x045d
#define BHND_BOARD_BU4712L 0x045f

7
sys/dev/bhnd/bhnd_match.h
View File

@ -50,7 +50,7 @@ struct bhnd_hwrev_match {
#define _BHND_COPY_MATCH_FIELD(_src, _name) \
.m.match._name = (_src)->m.match._name, \
._name = (_src)->_name
/* Set match field @p _name with @p _value */
#define _BHND_SET_MATCH_FIELD(_name, _value) \
.m.match._name = 1, ._name = _value
@ -112,7 +112,7 @@ struct bhnd_core_match {
flags_unused:2;
} match;
} m;
uint16_t core_vendor; /**< required JEP106 device vendor */
uint16_t core_id; /**< required core ID */
struct bhnd_hwrev_match core_rev; /**< matching core revisions. */
@ -261,7 +261,6 @@ struct bhnd_board_match {
#define BHND_MATCH_BOARD(_vend, _type) \
BHND_MATCH_BOARD_VENDOR(_vend), BHND_MATCH_BOARD_TYPE(_type)
/**
* A bhnd(4) device match descriptor.
*
@ -292,7 +291,7 @@ struct bhnd_device_match {
flags_unused:15;
} match;
} m;
uint16_t core_vendor; /**< required JEP106 device vendor */
uint16_t core_id; /**< required core ID */
struct bhnd_hwrev_match core_rev; /**< matching core revisions. */

2
sys/dev/bhnd/bhnd_private.h
View File

@ -96,7 +96,7 @@ struct bhnd_core_clkctl {
#define BHND_CLKCTL_WRITE_4(_clkctl, _val) \
bhnd_bus_write_4((_clkctl)->cc_res, (_clkctl)->cc_res_offset, (_val))
#define BHND_CLKCTL_SET_4(_clkctl, _val, _mask) \
BHND_CLKCTL_WRITE_4((_clkctl), \
((_val) & (_mask)) | (BHND_CLKCTL_READ_4(_clkctl) & ~(_mask)))

22
sys/dev/bhnd/bhnd_subr.c
View File

@ -169,7 +169,6 @@ static const struct bhnd_core_desc {
"PL368 Device Management Interface" },
{ BHND_MFGID_ARM, BHND_PRIMEID_MWRAP, BHND_DEVCLASS_OTHER,
"PL369 Device Management Interface" },
{ 0, 0, 0, NULL }
};
@ -276,7 +275,7 @@ bhnd_find_core_desc(uint16_t vendor, uint16_t device)
return (&bhnd_core_descs[i]);
}
return (NULL);
}
@ -290,7 +289,7 @@ const char *
bhnd_find_core_name(uint16_t vendor, uint16_t device)
{
const struct bhnd_core_desc *desc;
if ((desc = bhnd_find_core_desc(vendor, device)) == NULL)
return ("unknown");
@ -307,7 +306,7 @@ bhnd_devclass_t
bhnd_find_core_class(uint16_t vendor, uint16_t device)
{
const struct bhnd_core_desc *desc;
if ((desc = bhnd_find_core_desc(vendor, device)) == NULL)
return (BHND_DEVCLASS_OTHER);
@ -654,7 +653,6 @@ bhnd_match_core(const struct bhnd_core_info *cores, u_int num_cores,
return (NULL);
}
/**
* Find the first core in @p cores with the given @p class.
*
@ -676,7 +674,6 @@ bhnd_find_core(const struct bhnd_core_info *cores, u_int num_cores,
return bhnd_match_core(cores, num_cores, &md);
}
/**
* Create an equality match descriptor for @p core.
*
@ -697,7 +694,6 @@ bhnd_core_get_match_desc(const struct bhnd_core_info *core)
});
}
/**
* Return true if the @p lhs is equal to @p rhs.
*
@ -942,7 +938,7 @@ bhnd_device_lookup(device_t dev, const struct bhnd_device *table,
/* hostb implies BHND_ATTACH_ADAPTER requirement */
if (dflags & BHND_DF_HOSTB)
dflags |= BHND_DF_ADAPTER;
if (dflags & BHND_DF_ADAPTER)
if (attach_type != BHND_ATTACH_ADAPTER)
continue;
@ -999,7 +995,6 @@ bhnd_device_quirks(device_t dev, const struct bhnd_device *table,
return (quirks);
}
/**
* Allocate bhnd(4) resources defined in @p rs from a parent bus.
*
@ -1444,7 +1439,6 @@ bhnd_nvram_getvar_int32(device_t dev, const char *name, int32_t *value)
return (bhnd_nvram_getvar_int(dev, name, value, sizeof(*value)));
}
/**
* Read an NVRAM variable's array value.
*
@ -1799,7 +1793,6 @@ bhnd_set_default_core_desc(device_t dev)
bhnd_set_custom_core_desc(dev, bhnd_get_device_name(dev));
}
/**
* Using the bhnd @p chip_id, populate the bhnd(4) bus @p dev's device
* description.
@ -1843,7 +1836,7 @@ bhnd_set_default_bus_desc(device_t dev, const struct bhnd_chipid *chip_id)
} else {
device_set_desc(dev, bus_name);
}
}
/**
@ -2236,7 +2229,7 @@ bhnd_bus_generic_alloc_resource(device_t dev, device_t child, int type,
br = malloc(sizeof(struct bhnd_resource), M_BHND, M_NOWAIT);
if (br == NULL)
goto failed;
br->direct = false;
br->res = res;
@ -2248,7 +2241,7 @@ bhnd_bus_generic_alloc_resource(device_t dev, device_t child, int type,
}
return (br);
failed:
if (res != NULL)
BUS_RELEASE_RESOURCE(dev, child, type, *rid, res);
@ -2276,7 +2269,6 @@ bhnd_bus_generic_release_resource(device_t dev, device_t child, int type,
return (0);
}
/**
* Helper function for implementing BHND_BUS_ACTIVATE_RESOURCE().
*

5
sys/dev/bhnd/bhnd_types.h
View File

@ -122,14 +122,14 @@ typedef enum {
* acceptable.
*/
BHND_CLOCK_ILP = (1 << 1),
/**
* Active Low-Power (ALP).
*
* Low-latency register access and low-rate DMA.
*/
BHND_CLOCK_ALP = (1 << 2),
/**
* High Throughput (HT).
*
@ -184,5 +184,4 @@ typedef uint64_t bhnd_addr_t;
typedef uint64_t bhnd_size_t;
#define BHND_SIZE_MAX UINT64_MAX /**< Maximum bhnd_size_t value */
#endif /* _BHND_BHND_TYPES_H_ */

2
sys/dev/bhnd/bhndb/bhnd_bhndb.c
View File

@ -72,7 +72,6 @@ bhnd_bhndb_get_attach_type(device_t dev, device_t child)
return (BHND_ATTACH_ADAPTER);
}
static bool
bhnd_bhndb_is_hw_disabled(device_t dev, device_t child)
{
@ -82,7 +81,6 @@ bhnd_bhndb_is_hw_disabled(device_t dev, device_t child)
return (BHNDB_IS_CORE_DISABLED(device_get_parent(dev), dev, &core));
}
static device_t
bhnd_bhndb_find_hostb_device(device_t dev)
{

26
sys/dev/bhnd/bhndb/bhndb.c
View File

@ -451,7 +451,7 @@ bhndb_init_region_cfg(struct bhndb_softc *sc, bhnd_erom_t *erom,
direct_msg = prio >= prio_min ? "direct" : "indirect";
type_msg = region->static_regwin ? "static" : "dynamic";
device_printf(sc->dev, "region 0x%llx+0x%llx priority "
"%u %s/%s",
(unsigned long long) region->addr,
@ -649,7 +649,7 @@ bhndb_generic_detach(device_t dev)
/* Clean up our driver state. */
bhndb_free_resources(sc->bus_res);
BHNDB_LOCK_DESTROY(sc);
return (0);
@ -690,7 +690,7 @@ bhndb_generic_resume(device_t dev)
error = 0;
for (size_t i = 0; i < bus_res->dwa_count; i++) {
dwa = &bus_res->dw_alloc[i];
/* Skip regions that were not previously used */
if (bhndb_dw_is_free(bus_res, dwa) && dwa->target == 0x0)
continue;
@ -858,7 +858,7 @@ bhndb_add_child(device_t dev, u_int order, const char *name, int unit)
{
struct bhndb_devinfo *dinfo;
device_t child;
child = device_add_child_ordered(dev, order, name, unit);
if (child == NULL)
return (NULL);
@ -1016,7 +1016,7 @@ bhndb_alloc_resource(device_t dev, device_t child, int type,
child);
if (rv == NULL)
return (NULL);
rman_set_rid(rv, *rid);
/* Activate */
@ -1099,7 +1099,7 @@ bhndb_adjust_resource(device_t dev, device_t child, int type,
struct rman *rm;
rman_res_t mstart, mend;
int error;
sc = device_get_softc(dev);
error = 0;
@ -1219,7 +1219,7 @@ bhndb_activate_static_region(struct bhndb_softc *sc,
bridge_res = bhndb_host_resource_for_regwin(sc->bus_res->res, win);
if (bridge_res == NULL)
return (ENXIO);
/* Calculate subregion offset within the parent resource */
parent_offset = r_start - region->addr;
parent_offset += win->win_offset;
@ -1340,7 +1340,7 @@ bhndb_try_activate_resource(struct bhndb_softc *sc, device_t child, int type,
/* Only MMIO resources can be mapped via register windows */
KASSERT(type == SYS_RES_MEMORY, ("invalid type: %d", type));
r_start = rman_get_start(r);
r_size = rman_get_size(r);
@ -1537,7 +1537,7 @@ bhndb_activate_bhnd_resource(device_t dev, device_t child,
KASSERT(!r->direct,
("direct flag set on inactive resource"));
KASSERT(!(rman_get_flags(r->res) & RF_ACTIVE),
("RF_ACTIVE set on inactive resource"));
@ -1769,7 +1769,7 @@ bhndb_io_resource(struct bhndb_softc *sc, bus_addr_t addr, bus_size_t size,
(unsigned long long) addr,
(unsigned long long) addr+size-1);
}
error = bhndb_dw_set_addr(sc->dev, sc->bus_res, dwa, addr,
size);
if (error) {
@ -2161,7 +2161,7 @@ bhndb_get_dma_translation(device_t dev, device_t child, u_int width,
masked = (dwin->addr_mask | dwin->addrext_mask) & addr_mask;
if (masked == 0)
continue;
/* Is this a better match? */
if (match == NULL || masked > match_addr_mask) {
match = dwin;
@ -2264,7 +2264,7 @@ static device_method_t bhndb_methods[] = {
DEVMETHOD(bhnd_bus_deregister_provider, bhnd_bus_generic_sr_deregister_provider),
DEVMETHOD(bhnd_bus_retain_provider, bhnd_bus_generic_sr_retain_provider),
DEVMETHOD(bhnd_bus_release_provider, bhnd_bus_generic_sr_release_provider),
DEVMETHOD(bhnd_bus_read_1, bhndb_bus_read_1),
DEVMETHOD(bhnd_bus_read_2, bhndb_bus_read_2),
DEVMETHOD(bhnd_bus_read_4, bhndb_bus_read_4),
@ -2285,7 +2285,7 @@ static device_method_t bhndb_methods[] = {
DEVMETHOD(bhnd_bus_write_multi_1, bhndb_bus_write_multi_1),
DEVMETHOD(bhnd_bus_write_multi_2, bhndb_bus_write_multi_2),
DEVMETHOD(bhnd_bus_write_multi_4, bhndb_bus_write_multi_4),
DEVMETHOD(bhnd_bus_read_multi_stream_1, bhndb_bus_read_multi_stream_1),
DEVMETHOD(bhnd_bus_read_multi_stream_2, bhndb_bus_read_multi_stream_2),
DEVMETHOD(bhnd_bus_read_multi_stream_4, bhndb_bus_read_multi_stream_4),

7
sys/dev/bhnd/bhndb/bhndb.h
View File

@ -74,14 +74,13 @@ struct bhndb_regwin {
bhndb_regwin_type_t win_type; /**< window type */
bus_size_t win_offset; /**< offset of the window within the resource */
bus_size_t win_size; /**< size of the window */
/** Resource identification */
struct {
int type; /**< resource type */
int rid; /**< resource id */
} res;
union {
/** Core-specific register window (BHNDB_REGWIN_T_CORE). */
struct {
@ -102,7 +101,6 @@ struct bhndb_regwin {
} dyn;
} d;
};
#define BHNDB_REGWIN_TABLE_END { BHNDB_REGWIN_T_INVALID, 0, 0, { 0, 0 } }
/**
@ -130,7 +128,6 @@ struct bhndb_hw {
const struct bhndb_hwcfg *cfg; /**< associated hardware configuration */
};
/**
* bhndb resource allocation priorities.
*/
@ -190,8 +187,6 @@ struct bhndb_hw_priority {
const struct bhndb_port_priority *ports; /**< port priorities */
u_int num_ports; /**< number of port priority records. */
};
#define BHNDB_HW_PRIORITY_TABLE_END { {}, BHNDB_PRIORITY_NONE, NULL, 0 }
#endif /* _BHND_BHNDB_H_ */

2
sys/dev/bhnd/bhndb/bhndb_hwdata.h
View File

@ -37,4 +37,4 @@
extern const struct bhndb_hw_priority bhndb_bcma_priority_table[];
extern const struct bhndb_hw_priority bhndb_siba_priority_table[];
#endif /* _BHND_BHNDB_HWDATA_H_ */
#endif /* _BHND_BHNDB_HWDATA_H_ */

5
sys/dev/bhnd/bhndb/bhndb_pci.c
View File

@ -181,7 +181,6 @@ struct bhndb_pci_probe {
struct bhndb_host_resources *hr; /**< backing host resources */
};
static struct bhndb_pci_quirk bhndb_pci_quirks[] = {
/* Backplane interrupt flags must be routed via siba-specific
* SIBA_CFG0_INTVEC configuration register; the BHNDB_PCI_INT_MASK
@ -853,7 +852,7 @@ bhndb_pci_resume(device_t dev)
int error;
sc = device_get_softc(dev);
/* Enable clocks (if supported by this hardware) */
if ((error = bhndb_enable_pci_clocks(sc->dev)))
return (error);
@ -869,7 +868,7 @@ bhndb_pci_suspend(device_t dev)
int error;
sc = device_get_softc(dev);
/* Disable clocks (if supported by this hardware) */
if ((error = bhndb_disable_pci_clocks(sc->dev)))
return (error);

6
sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c
View File

@ -70,7 +70,6 @@ static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3;
sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \
.cfg = &bhndb_pci_hwcfg_ ## _vers \
}
#define _BHNDB_HW_REQ_ARRAY(...) (struct bhnd_core_match[]) { __VA_ARGS__ }
/**
@ -108,7 +107,6 @@ const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = {
.dma_translations = NULL,
};
/**
* Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based
* PCI devices; this configuration is adequate for enumerating a bridged
@ -181,7 +179,7 @@ const struct bhndb_hw bhndb_pci_generic_hw_table[] = {
BHND_MATCH_CORE_UNIT (0)
}
),
/* PCI/V1 WLAN */
BHNDB_HW_MATCH("PCI/v1 WLAN", v1_pci,
/* PCI Core */
@ -258,7 +256,6 @@ const struct bhndb_hw bhndb_pci_generic_hw_table[] = {
}
),
/* PCIE/V3 WLAN */
BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3,
/* PCIe Gen2 Core */
@ -276,7 +273,6 @@ const struct bhndb_hw bhndb_pci_generic_hw_table[] = {
BHND_MATCH_CORE_UNIT (0)
}
),
{ NULL, NULL, 0, NULL }
};

2
sys/dev/bhnd/bhndb/bhndb_pci_hwdata.h
View File

@ -39,4 +39,4 @@ extern struct bhndb_hw bhndb_pci_generic_hw_table[];
extern const struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg;
extern const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg;
#endif /* _BHND_BHNDB_PCI_HWDATA_H_ */
#endif /* _BHND_BHNDB_PCI_HWDATA_H_ */

1
sys/dev/bhnd/bhndb/bhndb_pci_sprom.c
View File

@ -75,7 +75,6 @@ bhndb_pci_sprom_probe(device_t dev)
return (BUS_PROBE_NOWILDCARD);
}
static device_method_t bhndb_pci_sprom_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, bhndb_pci_sprom_probe),

1
sys/dev/bhnd/bhndb/bhndb_pcireg.h
View File

@ -205,7 +205,6 @@
#define BHNDB_PCI_SPROM_BACKPLANE_EN 0x40 /**< enable indirect backplane access (BHNDB_PCI_BACKPLANE_*) */
#define BHNDB_PCI_SPROM_OTPIN_USE 0x80 /**< device OTP in use */
/* PCI (non-PCIe) BHNDB_PCI_GPIO_OUTEN */
#define BHNDB_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
#define BHNDB_PCI_GPIO_HWRAD_OFF 0x20 /* PCI config space GPIO 13 for hw radio disable */

4
sys/dev/bhnd/bhndb/bhndb_private.h
View File

@ -143,7 +143,6 @@ const struct bhndb_port_priority *bhndb_hw_priorty_find_port(
bhnd_port_type port_type, u_int port,
u_int region);
/**
* Dynamic register window allocation reference.
*/
@ -198,7 +197,7 @@ struct bhndb_resources {
const struct bhndb_hwcfg *cfg; /**< hardware configuration */
struct bhndb_host_resources *res; /**< host resources, or NULL if not allocated */
struct rman ht_mem_rman; /**< host memory manager */
struct rman br_mem_rman; /**< bridged memory manager */
struct rman br_irq_rman; /**< bridged irq manager */
@ -269,7 +268,6 @@ bhndb_dw_is_free(struct bhndb_resources *br, struct bhndb_dw_alloc *dwa)
return (is_free);
}
#define BHNDB_LOCK_INIT(sc) \
mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
"bhndb resource allocator lock", MTX_DEF)

15
sys/dev/bhnd/bhndb/bhndb_subr.c
View File

@ -154,7 +154,7 @@ bhnd_generic_br_resume_child(device_t dev, device_t child)
struct resource_list *rl;
struct resource_list_entry *rle;
int error;
if (device_get_parent(child) != dev)
BUS_RESUME_CHILD(device_get_parent(dev), child);
@ -306,7 +306,6 @@ bhndb_alloc_resources(device_t dev, device_t parent_dev,
}
free_ht_mem = true;
/* Initialize resource manager for the bridged address space. */
r->br_mem_rman.rm_start = 0;
r->br_mem_rman.rm_end = BUS_SPACE_MAXADDR_32BIT;
@ -325,7 +324,6 @@ bhndb_alloc_resources(device_t dev, device_t parent_dev,
goto failed;
}
/* Initialize resource manager for the bridged interrupt controller. */
r->br_irq_rman.rm_start = 0;
r->br_irq_rman.rm_end = RM_MAX_END;
@ -352,7 +350,7 @@ bhndb_alloc_resources(device_t dev, device_t parent_dev,
device_printf(r->dev, "max dynamic regwin count exceeded\n");
goto failed;
}
/* Allocate the dynamic window allocation table. */
r->dw_alloc = malloc(sizeof(r->dw_alloc[0]) * r->dwa_count, M_BHND,
M_NOWAIT);
@ -615,7 +613,7 @@ bhndb_free_resources(struct bhndb_resources *br)
free(dwr, M_BHND);
}
}
/* Release bus regions */
STAILQ_FOREACH_SAFE(region, &br->bus_regions, link, r_next) {
STAILQ_REMOVE(&br->bus_regions, region, bhndb_region, link);
@ -780,7 +778,6 @@ bhndb_release_host_resources(struct bhndb_host_resources *hr)
free(hr, M_BHND);
}
/**
* Search @p cores for the core serving as the bhnd host bridge.
*
@ -1120,7 +1117,6 @@ bhndb_has_static_region_mapping(struct bhndb_resources *br,
/* Have we traversed a complete (if discontiguous) mapping? */
if (r_addr == addr + size)
return (true);
}
/* No complete mapping found */
@ -1286,7 +1282,7 @@ bhndb_dw_retain(struct bhndb_resources *br, struct bhndb_dw_alloc *dwa,
/* Update the free list */
bit_set(br->dwa_freelist, dwa->rnid);
return (0);
}
@ -1354,7 +1350,7 @@ bhndb_dw_set_addr(device_t dev, struct bhndb_resources *br,
/* Verify that the window is large enough for the full target */
if (rw->win_size - offset < size)
return (ENOMEM);
/* Update the window target */
error = BHNDB_SET_WINDOW_ADDR(dev, dwa->win, dwa->target);
if (error) {
@ -1630,7 +1626,6 @@ bhndb_hw_priority_find_core(const struct bhndb_hw_priority *table,
return (NULL);
}
/**
* Search for a port resource priority descriptor in @p table.
*

16
sys/dev/bhnd/cores/chipc/chipc.c
View File

@ -79,7 +79,6 @@ static const struct bhnd_device chipc_devices[] = {
BHND_DEVICE_END
};
/* Device quirks table */
static struct bhnd_device_quirk chipc_quirks[] = {
/* HND OTP controller revisions */
@ -90,7 +89,7 @@ static struct bhnd_device_quirk chipc_quirks[] = {
/* IPX OTP controller revisions */
BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX),
BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX),
BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM),
BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT),
BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE),
@ -225,7 +224,7 @@ chipc_attach(device_t dev)
goto failed;
return (0);
failed:
device_delete_children(sc->dev);
@ -521,7 +520,6 @@ chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps)
caps->flash_type = CHIPC_NFLASH_4706;
}
/* Determine NVRAM source. Must occur after the SPROM/OTP/flash
* capability flags have been populated. */
caps->nvram_src = chipc_find_nvram_src(sc, caps);
@ -674,7 +672,6 @@ chipc_get_resource_list(device_t dev, device_t child)
return (&dinfo->resources);
}
/* Allocate region records for the given port, and add the port's memory
* range to the mem_rman */
static int
@ -971,7 +968,7 @@ chipc_adjust_resource(device_t dev, device_t child, int type,
struct chipc_softc *sc;
struct chipc_region *cr;
struct rman *rm;
sc = device_get_softc(dev);
/* Handled by parent bus? */
@ -985,7 +982,7 @@ chipc_adjust_resource(device_t dev, device_t child, int type,
cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
if (cr == NULL)
return (EINVAL);
if (end <= start)
return (EINVAL);
@ -1031,7 +1028,7 @@ chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type,
cr = chipc_find_region(sc, r_start, r_end);
if (cr == NULL)
return (EINVAL);
/* Calculate subregion offset within the chipc region */
cr_offset = r_start - cr->cr_addr;
@ -1070,7 +1067,7 @@ chipc_activate_bhnd_resource(device_t dev, device_t child, int type,
int error;
sc = device_get_softc(dev);
/* Delegate non-locally managed resources to parent */
rm = chipc_get_rman(sc, type);
if (rm == NULL || !rman_is_region_manager(r->res, rm)) {
@ -1267,7 +1264,6 @@ chipc_disable_sprom(device_t dev)
break;
}
CHIPC_UNLOCK(sc);
}

1
sys/dev/bhnd/cores/chipc/chipc_cfi.c
View File

@ -78,7 +78,6 @@ static device_method_t chipc_cfi_methods[] = {
DEVMETHOD(device_probe, chipc_cfi_probe),
DEVMETHOD(device_attach, chipc_cfi_attach),
DEVMETHOD(device_detach, cfi_detach),
{0, 0}
};

10
sys/dev/bhnd/cores/chipc/chipc_gpio.c
View File

@ -75,7 +75,6 @@ static chipc_gpio_pin_mode chipc_gpio_pin_get_mode(
struct chipc_gpio_softc *sc,
uint32_t pin_num);
/* Debugging flags */
static u_long chipc_gpio_debug = 0;
TUNABLE_ULONG("hw.bhnd_chipc.gpio_debug", &chipc_gpio_debug);
@ -430,7 +429,7 @@ chipc_gpio_pin_getname(device_t dev, uint32_t pin_num, char *name)
if (ret >= GPIOMAXNAME)
return (ENOMEM);
return (0);
}
@ -440,7 +439,7 @@ chipc_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags)
struct chipc_gpio_softc *sc;
struct chipc_gpio_update upd;
int error;
sc = device_get_softc(dev);
if (!CC_GPIO_VALID_PIN(pin_num))
@ -548,7 +547,7 @@ chipc_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
struct chipc_gpio_softc *sc;
struct chipc_gpio_update upd;
int error;
sc = device_get_softc(dev);
if (!CC_GPIO_VALID_PINS(first_pin, num_pins))
@ -580,7 +579,6 @@ chipc_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
return (error);
}
/**
* Commit a single @p reg register update.
*/
@ -742,7 +740,7 @@ chipc_gpio_check_flags(struct chipc_gpio_softc *sc, uint32_t pin_num,
/* Check for unhandled flags */
if ((flags & ~(mode_flag | output_flag)) != 0)
return (EINVAL);
*mode = CC_GPIO_PIN_OUTPUT;
return (0);

3
sys/dev/bhnd/cores/chipc/chipc_subr.c
View File

@ -213,7 +213,6 @@ chipc_set_irq_resource(struct chipc_softc *sc, device_t child, int rid,
return (0);
}
/**
* Add a SYS_RES_MEMORY resource with a given resource ID, relative to the
* given port and region, to @p child's resource list.
@ -275,7 +274,6 @@ chipc_set_mem_resource(struct chipc_softc *sc, device_t child, int rid,
region_addr + start, count));
}
/*
* Print a capability structure.
*/
@ -486,7 +484,6 @@ chipc_retain_region(struct chipc_softc *sc, struct chipc_region *cr, int flags)
cr->cr_refs++;
}
/* Handle activation */
if (flags & RF_ACTIVE) {
KASSERT(cr->cr_refs > 0,

5
sys/dev/bhnd/cores/chipc/chipcreg.h
View File

@ -49,7 +49,6 @@
#define CHIPC_GET_BITS(_value, _field) \
((_value & _field ## _MASK) >> _field ## _SHIFT)
#define CHIPC_ID 0x00
#define CHIPC_CAPABILITIES 0x04
#define CHIPC_CORECTRL 0x08 /* rev >= 1 */
@ -115,7 +114,7 @@
#define CHIPC_PLL_ON_DELAY 0xB0 /* rev >= 4 */
#define CHIPC_PLL_FREFSEL_DELAY 0xB4 /* rev >= 4 */
#define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* "slowclock" (rev 6-9) */
/* "instaclock" clock control registers */
#define CHIPC_SYS_CLK_CTL 0xC0 /* "instaclock" (rev >= 10) */
#define CHIPC_SYS_CLK_ST_STRETCH 0xC4 /* state strech (?) rev >= 10 */
@ -266,7 +265,6 @@ enum {
CHIPC_CST_OTP_PWRDN = 3 /**< OTP is powered down, SPROM is present (rev <= 22 only) */
};
#define CHIPC_CST_SPROM_OTP_SEL_R22_MASK 0x00000003 /**< chipstatus OTP/SPROM SEL value (rev 22) */
#define CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 0
#define CHIPC_CST_SPROM_OTP_SEL_R23_MASK 0x000000c0 /**< chipstatus OTP/SPROM SEL value (revs 23-31)
@ -782,7 +780,6 @@ enum {
#define CHIPC_CST4312_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK
#define CHIPC_CST4312_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT
/* 4322 chip-specific ChipStatus register bits */
#define CHIPC_CST4322_XTAL_FREQ_20_40MHZ 0x00000020
#define CHIPC_CST4322_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK

5
sys/dev/bhnd/cores/chipc/chipcvar.h
View File

@ -60,7 +60,7 @@ const char *chipc_sflash_device_name(chipc_flash type);
enum {
/** No quirks */
CHIPC_QUIRK_NONE = 0,
/**
* ChipCommon-controlled SPROM/OTP is supported, along with the
* CHIPC_CAP_SPROM capability flag.
@ -78,7 +78,7 @@ enum {
* to allow reading/writing.
*/
CHIPC_QUIRK_MUX_SPROM = (1<<3),
/**
* Access to the SPROM uses pins shared with the 802.11a external PA.
*
@ -109,7 +109,6 @@ enum {
*/
CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) |
CHIPC_QUIRK_4331_EXTPA_MUX_SPROM,
/**
* SPROM pins are muxed with the FEM control lines on this 4360-family

2
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c
View File

@ -68,7 +68,6 @@ static int bhnd_pwrctl_updateclk(struct bhnd_pwrctl_softc *sc,
static struct bhnd_device_quirk pwrctl_quirks[];
/* Supported parent core device identifiers */
static const struct bhnd_device pwrctl_devices[] = {
BHND_DEVICE(BCM, CC, "ChipCommon Power Control", pwrctl_quirks),
@ -472,7 +471,6 @@ bhnd_pwrctl_request_clock(device_t dev, device_t child, bhnd_clock clock)
return (error);
}
static device_method_t bhnd_pwrctl_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, bhnd_pwrctl_probe),

2
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
View File

@ -539,7 +539,7 @@ bhnd_pwrctl_setclk(struct bhnd_pwrctl_softc *sc, bhnd_clock clock)
scc &= ~(CHIPC_SCC_FS | CHIPC_SCC_IP | CHIPC_SCC_XC);
if ((scc & CHIPC_SCC_SS_MASK) != CHIPC_SCC_SS_XTAL)
scc |= CHIPC_SCC_XC;
bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc);
/* for dynamic control, we have to release our xtal_pu

6
sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctlvar.h
View File

@ -71,8 +71,7 @@ enum {
* Dynamic clock control is not supported on these devices.
*/
PWRCTL_QUIRK_PCICLK_CTL = (1 << 1) | PWRCTL_QUIRK_FIXED_CLK,
/**
* On earliy BCM4311, BCM4321, and BCM4716 PCI(e) devices, no ALP
* clock is available, and the HT clock must be enabled.
@ -83,7 +82,7 @@ enum {
* ChipCommon revisions 6-9 use the slowclk register layout.
*/
PWRCTL_QUIRK_SLOWCLK_CTL = (1 << 3),
/**
* ChipCommon revisions 10-19 support the instaclk register layout.
*/
@ -100,7 +99,6 @@ struct bhnd_pwrctl_clkres {
STAILQ_ENTRY(bhnd_pwrctl_clkres) cr_link;
};
/**
* bhnd pwrctl driver instance state.
*/

12
sys/dev/bhnd/cores/pci/bhnd_pci.c
View File

@ -82,7 +82,6 @@ static const struct bhnd_pci_device {
BHND_PCI_DEV(PCI, "PCI-BHND bridge", BHND_DF_SOC),
BHND_PCI_DEV(PCIE, "PCIe-G1 Host-PCI bridge", BHND_DF_HOSTB),
BHND_PCI_DEV(PCIE, "PCIe-G1 PCI-BHND bridge", BHND_DF_SOC),
{ BHND_DEVICE_END, 0 }
};
@ -168,7 +167,7 @@ bhnd_pci_generic_detach(device_t dev)
return (error);
bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
BHND_PCI_LOCK_DESTROY(sc);
return (0);
@ -191,7 +190,7 @@ bhnd_pci_add_child(device_t dev, u_int order, const char *name, int unit)
{
struct bhnd_pci_devinfo *dinfo;
device_t child;
child = device_add_child_ordered(dev, order, name, unit);
if (child == NULL)
return (NULL);
@ -203,7 +202,7 @@ bhnd_pci_add_child(device_t dev, u_int order, const char *name, int unit)
}
resource_list_init(&dinfo->resources);
device_set_ivars(child, dinfo);
return (child);
}
@ -295,7 +294,6 @@ bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc)
return (ETIMEDOUT);
}
/**
* Write an MDIO IOCTL and wait for completion.
*/
@ -334,7 +332,6 @@ bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc)
device_printf(sc->dev, "failed to disable MDIO clock\n");
}
/**
* Issue a write command and wait for completion
*/
@ -380,7 +377,6 @@ bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd,
return (0);
}
int
bhnd_pcie_mdio_read(struct bhnd_pci_softc *sc, int phy, int reg)
{
@ -530,7 +526,7 @@ static device_method_t bhnd_pci_methods[] = {
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
DEVMETHOD_END
};

14
sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c
View File

@ -173,7 +173,6 @@ static const struct bhnd_device_quirk bhnd_pcie_quirks[] = {
BHND_DEVICE_QUIRK_END
};
#define BHND_PCI_SOFTC(_sc) (&((_sc)->common))
#define BHND_PCI_READ_2(_sc, _reg) \
@ -184,7 +183,7 @@ static const struct bhnd_device_quirk bhnd_pcie_quirks[] = {
#define BHND_PCI_WRITE_2(_sc, _reg, _val) \
bhnd_bus_write_2(BHND_PCI_SOFTC(_sc)->mem_res, (_reg), (_val))
#define BHND_PCI_WRITE_4(_sc, _reg, _val) \
bhnd_bus_write_4(BHND_PCI_SOFTC(_sc)->mem_res, (_reg), (_val))
@ -193,7 +192,7 @@ static const struct bhnd_device_quirk bhnd_pcie_quirks[] = {
#define BHND_PCI_PROTO_WRITE_4(_sc, _reg, _val) \
bhnd_pcie_write_proto_reg(BHND_PCI_SOFTC(_sc), (_reg), (_val))
#define BHND_PCI_MDIO_READ(_sc, _phy, _reg) \
bhnd_pcie_mdio_read(BHND_PCI_SOFTC(_sc), (_phy), (_reg))
@ -252,7 +251,7 @@ bhnd_pci_hostb_attach(device_t dev)
goto failed;
return (0);
failed:
bhnd_pci_generic_detach(dev);
return (error);
@ -406,12 +405,12 @@ bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc, bhnd_pci_war_state state)
/* Disable PCI CLKRUN# */
if (sc->quirks & BHND_PCI_QUIRK_CLKRUN_DSBL) {
uint32_t ctl;
ctl = BHND_PCI_READ_4(sc, BHND_PCI_CLKRUN_CTL);
ctl |= BHND_PCI_CLKRUN_DSBL;
BHND_PCI_WRITE_4(sc, BHND_PCI_CLKRUN_CTL, ctl);
}
/* Enable TLP unmatched address handling work-around */
if (sc->quirks & BHND_PCIE_QUIRK_UR_STATUS_FIX) {
uint32_t wrs;
@ -476,7 +475,7 @@ bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc, bhnd_pci_war_state state)
BHND_PCI_MDIO_WRITE(sc, BHND_PCIE_PHY_SDR9_PLL,
BHND_PCIE_SDR9_PLL_CTRL, pctl);
}
/* Explicitly enable PCI-PM */
if (sc->quirks & BHND_PCIE_QUIRK_PCIPM_REQEN) {
uint32_t lcreg;
@ -520,7 +519,6 @@ bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc, bhnd_pci_war_state state)
BHND_PCI_WRITE_2(sc, reg, cfg);
/* Set ASPM/ECPM (CLKREQ) flags in PCIe link control register */
cfg = pcie_read_config(sc->pci_dev, PCIER_LINK_CTL, 2);

7
sys/dev/bhnd/cores/pci/bhnd_pci_hostbvar.h
View File

@ -51,7 +51,7 @@ DECLARE_CLASS(bhnd_pci_hostb_driver);
enum {
/** No quirks */
BHND_PCI_QUIRK_NONE = 0,
/**
* SBTOPCI_PREF and SBTOPCI_BURST must be set on the
* SSB_PCICORE_SBTOPCI2 register.
@ -112,7 +112,7 @@ enum {
* explicitly set (to 114ns) to fix slow L1->L0 transition issues.
*/
BHND_PCIE_QUIRK_L1_IDLE_THRESH = (1<<8),
/**
* The ASPM L1 entry timer should be extended for better performance,
* and restored for better power savings.
@ -171,7 +171,7 @@ enum {
* If L23READY_EXIT_NOPRST is not already set in the SPROM, set it
*/
BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET = (1<<14),
/**
* The PCIe SerDes PLL must be configured to not retry the startup
* sequence upon frequency detection failure on SerDes <= rev9 devices
@ -254,5 +254,4 @@ struct bhnd_pcihb_softc {
} sdr9_quirk_polarity;
};
#endif /* _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ */

4
sys/dev/bhnd/cores/pci/bhnd_pcireg.h
View File

@ -205,7 +205,7 @@
#define BHND_PCIE_CFG_OFFSET(f, r) \
((((f) & BHND_PCIE_CFG_ADDR_FUNC_MASK) << BHND_PCIE_CFG_ADDR_FUNC_SHIFT) | \
(((r) & BHND_PCIE_CFG_ADDR_FUNC_SHIFT) << BHND_PCIE_CFG_ADDR_REG_SHIFT))
/* BHND_PCIE_MDIO_CTL control */
#define BHND_PCIE_MDIOCTL_DIVISOR_MASK 0x7f /* clock divisor mask */
#define BHND_PCIE_MDIOCTL_DIVISOR_VAL 0x2 /* default clock divisor */
@ -318,7 +318,6 @@
#define BHND_PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
#define BHND_PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
/*
* PCIe-G1 SerDes MDIO Registers (>= rev10)
*/
@ -395,7 +394,6 @@
#define BHND_PCIE_SDR9_RX_TIMER1_LKACQ_MASK 0x00FF /* phase acquisition mode time (in 1024ns units) */
#define BHND_PCIE_SDR9_RX_TIMER1_LKACQ_SHIFT 0
/* SPROM offsets */
#define BHND_PCIE_SRSH_PI_OFFSET BHND_PCI_SRSH_PI_OFFSET /**< PCI base address bits in SPROM shadow area */
#define BHND_PCIE_SRSH_PI_MASK BHND_PCI_SRSH_PI_MASK /**< bits 15:12 of the PCI core address */

2
sys/dev/bhnd/cores/pci/bhnd_pcivar.h
View File

@ -103,7 +103,6 @@ struct bhnd_pci_softc {
int mem_rid; /**< register block RID */
};
#define BHND_PCI_LOCK_INIT(sc) \
mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
"BHND PCI driver lock", MTX_DEF)
@ -169,7 +168,6 @@ struct bhnd_pci_softc {
BHND_PCI_COMMON_REG((_regf), _attr ## _SHIFT), \
_val)
/**
* Evaluates to the offset of a common PCI/PCIe register definition.
*

8
sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c
View File

@ -131,7 +131,7 @@ bhnd_pcie2_generic_detach(device_t dev)
return (error);
bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
BHND_PCIE2_LOCK_DESTROY(sc);
return (0);
@ -154,7 +154,7 @@ bhnd_pcie2_add_child(device_t dev, u_int order, const char *name, int unit)
{
struct bhnd_pcie2_devinfo *dinfo;
device_t child;
child = device_add_child_ordered(dev, order, name, unit);
if (child == NULL)
return (NULL);
@ -166,7 +166,7 @@ bhnd_pcie2_add_child(device_t dev, u_int order, const char *name, int unit)
}
resource_list_init(&dinfo->resources);
device_set_ivars(child, dinfo);
return (child);
}
@ -280,7 +280,7 @@ static device_method_t bhnd_pcie2_methods[] = {
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
DEVMETHOD_END
};

6
sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostb.c
View File

@ -75,7 +75,6 @@ __FBSDID("$FreeBSD$");
static const struct bhnd_device_quirk bhnd_pcie2_quirks[];
static int bhnd_pcie2_wars_early_once(struct bhnd_pcie2hb_softc *sc);
static int bhnd_pcie2_wars_hwup(struct bhnd_pcie2hb_softc *sc);
static int bhnd_pcie2_wars_hwdown(struct bhnd_pcie2hb_softc *sc);
@ -125,19 +124,16 @@ bhnd_pcie2_hostb_attach(device_t dev)
if ((error = bhnd_pcie2_generic_attach(dev)))
return (error);
/* Apply early single-shot work-arounds */
if ((error = bhnd_pcie2_wars_early_once(sc)))
goto failed;
/* Apply attach/resume work-arounds */
if ((error = bhnd_pcie2_wars_hwup(sc)))
goto failed;
return (0);
failed:
bhnd_pcie2_generic_detach(dev);
return (error);

3
sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostbvar.h
View File

@ -45,7 +45,6 @@
DECLARE_CLASS(bhnd_pcie2_hostb_driver);
/*
* PCIe-Gen2 endpoint-mode device quirks
*/
@ -59,7 +58,6 @@ enum {
BHND_PCIE2_QUIRK_SERDES_TXDRV_DEEMPH = (1<<0),
};
/**
* bhnd_pci_hostb driver instance state.
*/
@ -70,5 +68,4 @@ struct bhnd_pcie2hb_softc {
uint32_t quirks; /**< hostb device quirks */
};
#endif /* _BHND_CORES_PCIE2_BHND_PCI_HOSTBVAR_H_ */

2
sys/dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h
View File

@ -99,7 +99,6 @@
#define BHND_PCIE2_MDIO_WRDATA 0x12C /**< mdio data write */
#define BHND_PCIE2_MDIO_RDDATA 0x130 /**< mdio data read */
/* DMA doorbell registers (>= rev5) */
#define BHND_PCIE2_DB0_HOST2DEV0 0x140
#define BHND_PCIE2_DB0_HOST2DEV1 0x144
@ -237,5 +236,4 @@
#define BHND_PCIE2_DMA_STATUS0 0x10 /**< current descriptor, xmt state */
#define BHND_PCIE2_DMA_STATUS1 0x10 /**< active descriptor, xmt error */
#endif /* _BHND_CORES_PCIE2_BHND_PCIE2_REG_H_ */

2
sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h
View File

@ -50,7 +50,6 @@ int bhnd_pcie2_generic_detach(device_t dev);
int bhnd_pcie2_generic_suspend(device_t dev);
int bhnd_pcie2_generic_resume(device_t dev);
uint32_t bhnd_pcie2_read_proto_reg(struct bhnd_pcie2_softc *sc,
uint32_t addr);
void bhnd_pcie2_write_proto_reg(struct bhnd_pcie2_softc *sc,
@ -88,7 +87,6 @@ struct bhnd_pcie2_softc {
int mem_rid; /**< register block RID */
};
#define BHND_PCIE2_LOCK_INIT(sc) \
mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
"BHND PCIe-G2 driver lock", MTX_DEF)

15
sys/dev/bhnd/cores/pmu/bhnd_pmu.c
View File

@ -197,7 +197,7 @@ bhnd_pmu_attach(device_t dev, struct bhnd_resource *res)
SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
"cpu_freq", CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
bhnd_pmu_sysctl_cpu_freq, "IU", "CPU clock frequency");
SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
"mem_freq", CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
bhnd_pmu_sysctl_mem_freq, "IU", "Memory clock frequency");
@ -237,7 +237,7 @@ bhnd_pmu_detach(device_t dev)
bhnd_pmu_query_fini(&sc->query);
bhnd_free_core_clkctl(sc->clkctl);
bhnd_release_provider(sc->dev, sc->chipc_dev, BHND_SERVICE_CHIPC);
return (0);
}
@ -275,7 +275,7 @@ bhnd_pmu_sysctl_bus_freq(SYSCTL_HANDLER_ARGS)
{
struct bhnd_pmu_softc *sc;
uint32_t freq;
sc = arg1;
BPMU_LOCK(sc);
@ -290,7 +290,7 @@ bhnd_pmu_sysctl_cpu_freq(SYSCTL_HANDLER_ARGS)
{
struct bhnd_pmu_softc *sc;
uint32_t freq;
sc = arg1;
BPMU_LOCK(sc);
@ -305,7 +305,7 @@ bhnd_pmu_sysctl_mem_freq(SYSCTL_HANDLER_ARGS)
{
struct bhnd_pmu_softc *sc;
uint32_t freq;
sc = arg1;
BPMU_LOCK(sc);
@ -427,7 +427,7 @@ bhnd_pmu_set_voltage_raw_method(device_t dev, bhnd_pmu_regulator regulator,
case BHND_REGULATOR_PAREF_LDO:
if (value > UINT8_MAX)
return (EINVAL);
BPMU_LOCK(sc);
error = bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_PAREF,
value);
@ -488,7 +488,6 @@ bhnd_pmu_disable_regulator_method(device_t dev, bhnd_pmu_regulator regulator)
}
}
/**
* Default bhnd_pmu driver implementation of BHND_PMU_GET_CLOCK_LATENCY().
*/
@ -625,7 +624,7 @@ static device_method_t bhnd_pmu_methods[] = {
DEVMETHOD(bhnd_pmu_get_max_transition_latency, bhnd_pmu_get_max_transition_latency_method),
DEVMETHOD(bhnd_pmu_request_spuravoid, bhnd_pmu_request_spuravoid_method),
DEVMETHOD_END
};

2
sys/dev/bhnd/cores/pmu/bhnd_pmu.h
View File

@ -45,7 +45,6 @@
#include "bhnd_pmu_if.h"
#include "bhnd_pmu_types.h"
/**
* Return the current value of a PMU chipctrl register.
*
@ -251,7 +250,6 @@ bhnd_pmu_request_spuravoid(device_t dev, bhnd_pmu_spuravoid spuravoid)
return (BHND_PMU_REQUEST_SPURAVOID(dev, spuravoid));
}
/**
* Return the PMU's maximum state transition latency in microseconds.
*

2
sys/dev/bhnd/cores/pmu/bhnd_pmu_core.c
View File

@ -121,7 +121,7 @@ bhnd_pmu_core_detach(device_t dev)
int error;
sc = device_get_softc(dev);
/* Delegate to common driver implementation */
if ((error = bhnd_pmu_detach(dev)))
return (error);

2
sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h
View File

@ -70,7 +70,6 @@
#define BHND_PMU_PLL_WRITE(_sc, _reg, _val, _mask) \
BHND_PMU_IND_WRITE((_sc), PLL_CONTROL, (_reg), (_val), (_mask))
/** FVCO frequencies, in Hz */
enum {
FVCO_880 = 880 * 1000, /**< 880MHz */
@ -93,7 +92,6 @@ enum {
SET_LDO_VOLTAGE_LNLDO2_SEL = 10,
};
uint32_t bhnd_pmu_ind_read(const struct bhnd_pmu_io *io, void *io_ctx,
bus_size_t addr, bus_size_t data, uint32_t reg);
void bhnd_pmu_ind_write(const struct bhnd_pmu_io *io, void *io_ctx,

14
sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
View File

@ -765,7 +765,7 @@ bhnd_pmu_res_masks(struct bhnd_pmu_softc *sc, uint32_t *pmin, uint32_t *pmax)
case BHND_CHIPID_BCM4342:
if (sc->cid.chip_rev >= 2)
break;
/* request ALP(can skip for A1) */
min_mask = PMURES_BIT(RES4322_RF_LDO) |
PMURES_BIT(RES4322_XTAL_PU) |
@ -1012,7 +1012,7 @@ bhnd_pmu_res_init(struct bhnd_pmu_softc *sc)
KASSERT(pmu_res_updown_table != NULL, ("no updown tables"));
updt = &pmu_res_updown_table[pmu_res_updown_table_sz - i - 1];
PMU_DEBUG(sc, "Changing rsrc %d res_updn_timer to %#x\n",
updt->resnum, updt->updown);
@ -1571,7 +1571,7 @@ bhnd_pmu0_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal)
} else {
pll_data &= ~BHND_PMU0_PLL0_PC1_STOP_MOD;
}
pll_mask =
BHND_PMU0_PLL0_PC1_WILD_INT_MASK |
BHND_PMU0_PLL0_PC1_WILD_FRAC_MASK;
@ -1665,8 +1665,6 @@ bhnd_pmu0_cpuclk0(struct bhnd_pmu_query *sc)
return FVCO / (divarm + BHND_PMU0_PLL0_PC0_DIV_ARM_BASE) * 1000;
}
/* Set up PLL registers in the PMU as per the crystal speed. */
static void
bhnd_pmu1_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal)
@ -1862,7 +1860,6 @@ bhnd_pmu1_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal)
BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, plldata, pllmask);
if (sc->cid.chip_id == BHND_CHIPID_BCM4330)
bhnd_pmu_set_4330_plldivs(sc);
@ -1885,7 +1882,6 @@ bhnd_pmu1_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal)
} else {
ndiv_mode = BHND_PMU1_PLL0_PC2_NDIV_MODE_MASH;
}
BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2,
BHND_PMU_SET_BITS(xt->ndiv_int, BHND_PMU1_PLL0_PC2_NDIV_INT) |
@ -2250,7 +2246,6 @@ bhnd_pmu5_clock(struct bhnd_pmu_query *sc, u_int pll0, u_int m)
return (133 * 1000000);
}
/* Fetch p1 and p2 */
BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR,
pll0 + BHND_PMU5_PLL_P1P2_OFF);
@ -2690,7 +2685,6 @@ bhnd_pmu_init(struct bhnd_pmu_softc *sc)
BHND_PMU_REGCTRL_WRITE(sc, 2, 0x00000005, 0x00000007);
}
/* Fetch target xtalfreq, in KHz */
error = bhnd_nvram_getvar_uint32(sc->chipc_dev, BHND_NVAR_XTALFREQ,
&xtalfreq);
@ -2876,7 +2870,6 @@ bhnd_pmu_rcal(struct bhnd_pmu_softc *sc)
uint8_t rcal_code;
bool bluetooth_rcal;
bluetooth_rcal = false;
switch (sc->cid.chip_id) {
@ -3204,7 +3197,6 @@ bhnd_pmu_spuravoid_pllupdate(struct bhnd_pmu_softc *sc,
return (ENODEV);
}
pmuctrl = BHND_PMU_CTRL_NOILP_ON_WAIT |
BHND_PMU_CTRL_PLL_PLLCTL_UPD;
break;

16
sys/dev/bhnd/cores/pmu/bhnd_pmureg.h
View File

@ -366,7 +366,6 @@
#define BHND_PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
#define BHND_PMU_XTALFREQ_REG_MEASURE_SHIFT 31
/* Divider allocation in 4716/47162/5356/5357 */
#define BHND_PMU5_MAINPLL_CPU 1
#define BHND_PMU5_MAINPLL_MEM 2
@ -394,16 +393,13 @@
#define BHND_PMU7_PLL_PLLCTL8 8
#define BHND_PMU7_PLL_PLLCTL11 11
/* PLL usage in 4716/47162 */
#define BHND_PMU4716_MAINPLL_PLL0 12
/* PLL usage in 5356/5357 */
#define BHND_PMU5356_MAINPLL_PLL0 0
#define BHND_PMU5357_MAINPLL_PLL0 0
/* 4716/47162 PMU resources */
#define BHND_PMU_RES4716_PROC_PLL_ON 0x00000040
#define BHND_PMU_RES4716_PROC_HT_AVAIL 0x00000080
@ -411,7 +407,6 @@
/* 4716/4717/4718 chip-specific CHIPCTRL PMU register bits */
#define BHND_PMU_CCTRL471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared with pflash */
/* 5354 PMU resources */
#define BHND_PMU_RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */
#define BHND_PMU_RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */
@ -434,12 +429,10 @@
#define BHND_PMU_RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */
#define BHND_PMU_RES5354_BB_PLL_PU 19 /* 0x80000 */
/* 5357 chip-specific CHIPCTRL register bits */
#define BHND_PMU_CCTRL5357_EXTPA (1<<14) /* extPA in CHIPCTRL1, bit 14 */
#define BHND_PMU_CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in CHIPCTRL1, bit 15 */
/* 4328 PMU resources */
#define BHND_PMU_RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
#define BHND_PMU_RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
@ -462,7 +455,6 @@
#define BHND_PMU_RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
#define BHND_PMU_RES4328_BB_PLL_PU 19 /* 0x80000 */
/* 4325 A0/A1 PMU resources */
#define BHND_PMU_RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
#define BHND_PMU_RES4325_CBUCK_BURST 1 /* 0x00000002 */
@ -487,18 +479,15 @@
#define BHND_PMU_RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
#define BHND_PMU_RES4325_HT_AVAIL 21 /* 0x00200000 */
/* 4325 B0/C0 PMU resources */
#define BHND_PMU_RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */
#define BHND_PMU_RES4325B0_CBUCK_BURST 2 /* 0x00000004 */
#define BHND_PMU_RES4325B0_CBUCK_PWM 3 /* 0x00000008 */
#define BHND_PMU_RES4325B0_CLDO_PU 4 /* 0x00000010 */
/* 4325 C1 PMU resources */
#define BHND_PMU_RES4325C1_LNLDO2_PU 12 /* 0x00001000 */
/* 4325 PMU resources */
#define BHND_PMU_RES4329_RESERVED0 0 /* 0x00000001 */
#define BHND_PMU_RES4329_CBUCK_LPOM 1 /* 0x00000002 */
@ -523,7 +512,6 @@
#define BHND_PMU_RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */
#define BHND_PMU_RES4329_HT_AVAIL 21 /* 0x00200000 */
/* 4312 PMU resources (all PMU chips with little memory constraint) */
#define BHND_PMU_RES4312_SWITCHER_BURST 0 /* 0x00000001 */
#define BHND_PMU_RES4312_SWITCHER_PWM 1 /* 0x00000002 */
@ -541,7 +529,6 @@
#define BHND_PMU_RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */
#define BHND_PMU_RES4312_HT_AVAIL 14 /* 0x00004000 */
/* 4322 PMU resources */
#define BHND_PMU_RES4322_RF_LDO 0
#define BHND_PMU_RES4322_ILP_REQUEST 1
@ -553,13 +540,11 @@
#define BHND_PMU_RES4322_HT_PHY_AVAIL 7
#define BHND_PMU_RES4322_OTP_PU 8
/* 43224 chip-specific CHIPCTRL register bits */
#define BHND_PMU_CCTRL43224_GPIO_TOGGLE 0x8000
#define BHND_PMU_CCTRL43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
#define BHND_PMU_CCTRL43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
/* 43236 PMU resources */
#define BHND_PMU_RES43236_REGULATOR 0
#define BHND_PMU_RES43236_ILP_REQUEST 1
@ -575,7 +560,6 @@
#define BHND_PMU_CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */
#define BHND_PMU_CCTRL43236_GSIO (1<<4) /* 0 disable */
/* 4331 PMU resources */
#define BHND_PMU_RES4331_REGULATOR 0
#define BHND_PMU_RES4331_ILP_REQUEST 1

1
sys/dev/bhnd/cores/usb/bhnd_ehci.c
View File

@ -247,7 +247,6 @@ static device_method_t ehci_methods[] = {
/* Bus interface */
DEVMETHOD(bus_print_child, bus_generic_print_child),
{0, 0}
};

2
sys/dev/bhnd/cores/usb/bhnd_usb.c
View File

@ -147,7 +147,6 @@ bhnd_usb_attach(device_t dev)
bus_write_4(sc->sc_mem, OHCI_CONTROL, 0);
if ( bhnd_get_device(dev) == BHND_COREID_USB20H) {
uint32_t rev = bhnd_get_hwrev(dev);
BHND_INFO_DEV(dev, "USB HOST 2.0 setup for rev %d", rev);
if (rev == 1/* ? == 2 */) {
@ -275,7 +274,6 @@ bhnd_usb_alloc_resource(device_t bus, device_t child, int type, int *rid,
* attempt to satisfy the allocation ourselves.
*/
if (type == SYS_RES_MEMORY) {
rv = rman_reserve_resource(&sc->mem_rman, start, end, count,
flags, child);
if (rv == NULL) {

3
sys/dev/bhnd/nvram/bhnd_nvram.h
View File

@ -56,7 +56,7 @@ typedef enum {
BHND_NVRAM_SRC_FLASH, /**< External flash */
BHND_NVRAM_SRC_SPROM, /**< External serial EEPROM. */
BHND_NVRAM_SRC_UNKNOWN /**< No NVRAM source is directly
* attached.
*
@ -125,7 +125,6 @@ typedef enum {
values */
} bhnd_nvram_type;
bool bhnd_nvram_is_signed_type(bhnd_nvram_type type);
bool bhnd_nvram_is_unsigned_type(bhnd_nvram_type type);
bool bhnd_nvram_is_int_type(bhnd_nvram_type type);

4
sys/dev/bhnd/nvram/bhnd_nvram_data.c
View File

@ -30,7 +30,6 @@
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#ifdef _KERNEL
#include <sys/param.h>
@ -207,7 +206,6 @@ bhnd_nvram_data_probe_classes(struct bhnd_nvram_data **data,
prio = result;
cls = next_cls;
/* Terminate search immediately on
* BHND_NVRAM_DATA_PROBE_SPECIFIC */
if (result == BHND_NVRAM_DATA_PROBE_SPECIFIC)
@ -549,7 +547,6 @@ bhnd_nvram_data_getvar_ptr_info(struct bhnd_nvram_data *nv, void *cookiep,
/* Select a default value format implementation */
/* Fetch the reference variable name */
name = bhnd_nvram_data_getvar_name(nv, cookiep);
@ -702,7 +699,6 @@ bhnd_nvram_data_getvar_ptr(struct bhnd_nvram_data *nv, void *cookiep,
return (nv->cls->op_getvar_ptr(nv, cookiep, len, type));
}
/**
* Return the variable name associated with a given @p cookiep.
* @param nv The NVRAM data to be iterated.

6
sys/dev/bhnd/nvram/bhnd_nvram_data_bcm.c
View File

@ -439,7 +439,7 @@ bhnd_nvram_bcm_serialize(bhnd_nvram_data_class *cls, bhnd_nvram_plist *props,
hdr.cfg0 = BCM_NVRAM_SET_BITS(hdr.cfg0, BCM_NVRAM_CFG0_VER, bcm_ver);
hdr.cfg0 = BCM_NVRAM_SET_BITS(hdr.cfg0, BCM_NVRAM_CFG0_SDRAM_INIT,
htole16(sdram_init));
hdr.cfg1 = BCM_NVRAM_SET_BITS(hdr.cfg1, BCM_NVRAM_CFG1_SDRAM_CFG,
htole16(sdram_cfg));
hdr.cfg1 = BCM_NVRAM_SET_BITS(hdr.cfg1, BCM_NVRAM_CFG1_SDRAM_REFRESH,
@ -722,7 +722,7 @@ bhnd_nvram_bcm_init(struct bhnd_nvram_bcm *bcm, struct bhnd_nvram_io *src)
/* Seek to the next record */
if (++io_offset == io_size) {
char ch;
/* Hit EOF without finding a terminating NUL
* byte; we need to grow our buffer and append
* it */
@ -833,7 +833,7 @@ bhnd_nvram_bcm_next(struct bhnd_nvram_data *nv, void **cookiep)
int error;
bcm = (struct bhnd_nvram_bcm *)nv;
io_offset = sizeof(struct bhnd_nvram_bcmhdr);
io_size = bhnd_nvram_io_getsize(bcm->data) - io_offset;

2
sys/dev/bhnd/nvram/bhnd_nvram_data_bcmvar.h
View File

@ -59,7 +59,7 @@ struct bhnd_nvram_bcm_hvar {
/** variable data */
union bhnd_nvram_bcm_hvar_value value;
};
/** BCM NVRAM header */
struct bhnd_nvram_bcmhdr {
uint32_t magic;

16
sys/dev/bhnd/nvram/bhnd_nvram_data_btxt.c
View File

@ -124,7 +124,6 @@ bhnd_nvram_btxt_probe(struct bhnd_nvram_io *io)
return (BHND_NVRAM_DATA_PROBE_MAYBE);
}
/**
* Parser states for bhnd_nvram_bcm_getvar_direct_common().
*/
@ -204,7 +203,6 @@ bhnd_nvram_btxt_getvar_direct(struct bhnd_nvram_io *io, const char *name,
pstate = BTXT_PARSE_KEY;
}
break;
case BTXT_PARSE_KEY: {
@ -454,7 +452,7 @@ bhnd_nvram_btxt_init(struct bhnd_nvram_btxt *btxt, struct bhnd_nvram_io *src)
int error;
BHND_NV_ASSERT(btxt->data == NULL, ("btxt data already allocated"));
if ((btxt->data = bhnd_nvram_iobuf_copy(src)) == NULL)
return (ENOMEM);
@ -495,7 +493,7 @@ bhnd_nvram_btxt_init(struct bhnd_nvram_btxt *btxt, struct bhnd_nvram_io *src)
&line_len, &env_len);
if (error)
return (error);
/* EOF? */
if (env_len == 0) {
BHND_NV_ASSERT(io_offset == io_size,
@ -680,9 +678,9 @@ bhnd_nvram_btxt_getvar_ptr(struct bhnd_nvram_data *nv, void *cookiep,
size_t io_offset, io_size;
size_t line_len, env_len;
int error;
btxt = (struct bhnd_nvram_btxt *)nv;
io_size = bhnd_nvram_io_getsize(btxt->data);
io_offset = bhnd_nvram_btxt_cookiep_to_offset(btxt, cookiep);
@ -726,9 +724,9 @@ bhnd_nvram_btxt_getvar_name(struct bhnd_nvram_data *nv, void *cookiep)
const void *ptr;
size_t io_offset, io_size;
int error;
btxt = (struct bhnd_nvram_btxt *)nv;
io_size = bhnd_nvram_io_getsize(btxt->data);
io_offset = bhnd_nvram_btxt_cookiep_to_offset(btxt, cookiep);
@ -901,7 +899,7 @@ bhnd_nvram_btxt_seek_next(struct bhnd_nvram_io *io, size_t *offset)
/* Skip entire comment line */
if (c == '#') {
size_t line_off = *offset + (p - baseptr);
if ((error = bhnd_nvram_btxt_seek_eol(io, &line_off)))
return (error);

15
sys/dev/bhnd/nvram/bhnd_nvram_data_sprom.c
View File

@ -257,7 +257,7 @@ bhnd_nvram_sprom_ident(struct bhnd_nvram_io *io,
return (ENXIO);
}
continue;
}
@ -314,7 +314,7 @@ bhnd_nvram_sprom_getvar_direct(struct bhnd_nvram_io *io, const char *name,
/* Look up the variable definition and ID */
if ((var = bhnd_nvram_find_vardefn(name)) == NULL)
return (ENOENT);
vid = bhnd_nvram_get_vardefn_id(var);
/* Identify the SPROM image layout */
@ -332,7 +332,7 @@ bhnd_nvram_sprom_getvar_direct(struct bhnd_nvram_io *io, const char *name,
bhnd_sprom_opcode_idx_entry entry;
union bhnd_nvram_sprom_storage storage;
bhnd_nvram_val val;
/* Fetch the variable's entry state */
if ((error = bhnd_sprom_opcode_init_entry(&state, &entry)))
return (error);
@ -509,7 +509,7 @@ bhnd_nvram_sprom_write_var(bhnd_sprom_opcode_state *state,
if (enc_nelem != nelem) {
const char *type_name;
type_name = bhnd_nvram_type_name(var_base_type);
BHND_NV_LOG("invalid %s property value '%s[%zu]': "
"required %s[%zu]", var->name, type_name,
@ -526,7 +526,7 @@ bhnd_nvram_sprom_write_var(bhnd_sprom_opcode_state *state,
BHND_NV_LOG("variable seek failed: %d\n", error);
return (error);
}
ipos = 0;
while ((error = bhnd_sprom_opcode_next_binding(state)) == 0) {
bhnd_sprom_opcode_bind *binding;
@ -744,7 +744,7 @@ bhnd_nvram_sprom_serialize(bhnd_nvram_data_class *cls, bhnd_nvram_plist *props,
BHND_NV_LOG("error writing CRC value: %d\n", error);
goto finished;
}
/*
* Success!
*/
@ -752,7 +752,7 @@ bhnd_nvram_sprom_serialize(bhnd_nvram_data_class *cls, bhnd_nvram_plist *props,
finished:
bhnd_sprom_opcode_fini(&state);
if (io != NULL)
bhnd_nvram_io_free(io);
@ -1264,7 +1264,6 @@ bhnd_nvram_sprom_read_var(struct bhnd_sprom_opcode_state *state,
BHND_NVRAM_VAL_BORROW_DATA));
}
/**
* Common variable decoding; fetches and decodes variable to @p val,
* using @p storage for actual data storage.

11
sys/dev/bhnd/nvram/bhnd_nvram_data_sprom_subr.c
View File

@ -183,7 +183,6 @@ bhnd_sprom_opcode_fini(bhnd_sprom_opcode_state *state)
bhnd_nv_free(state->idx);
}
/**
* Sort function used to prepare our index for querying; sorts
* bhnd_sprom_opcode_idx_entry values by variable ID, ascending.
@ -251,7 +250,6 @@ bhnd_sprom_opcode_index_find(bhnd_sprom_opcode_state *state, const char *name)
bhnd_nvram_opcode_idx_vid_compare));
}
/**
* Iterate over all index entries in @p state.
*
@ -289,7 +287,6 @@ bhnd_sprom_opcode_index_next(bhnd_sprom_opcode_state *state,
return (&state->idx[idxpos]);
}
/**
* Initialize @p entry with the current variable's opcode state.
*
@ -544,7 +541,6 @@ bhnd_sprom_opcode_set_bind(bhnd_sprom_opcode_state *state, uint8_t count,
return (0);
}
/**
* Apply and clear the current opcode bind state, if any.
*
@ -642,7 +638,7 @@ bhnd_sprom_opcode_set_type(bhnd_sprom_opcode_state *state, bhnd_nvram_type type)
SPROM_OP_BAD(state, "unsupported type: %d\n", type);
return (EINVAL);
}
/* Update state */
state->var.base_type = base_type;
state->var.mask = mask;
@ -717,7 +713,7 @@ bhnd_sprom_opcode_set_nelem(bhnd_sprom_opcode_state *state, uint8_t nelem)
state->vid);
return (ENXIO);
}
/* Cannot exceed the variable's defined array length */
if (nelem > var->nelem) {
SPROM_OP_BAD(state, "nelem %hhu exceeds %zu length %hhu\n",
@ -975,7 +971,6 @@ bhnd_sprom_opcode_rewrite_opcode(bhnd_sprom_opcode_state *state,
}
break;
case SPROM_OPCODE_VAR_STATE_DONE:
/* Previously completed variable definition. Discard variable
* state */
@ -1203,7 +1198,7 @@ bhnd_sprom_opcode_step(bhnd_sprom_opcode_state *state, uint8_t *opcode)
error = bhnd_sprom_opcode_apply_scale(state, &val);
if (error)
return (error);
/* Adding val must not overflow our offset */
if (UINT32_MAX - state->offset < val) {
BHND_NV_LOG("offset out of range\n");

2
sys/dev/bhnd/nvram/bhnd_nvram_data_spromvar.h
View File

@ -130,7 +130,7 @@ struct bhnd_sprom_opcode_state {
/** Current SPROM revision range */
bitstr_t bit_decl(revs, SPROM_OP_REV_MAX);
const uint8_t *input; /**< opcode input position */
/* State preserved across variable definitions */

8
sys/dev/bhnd/nvram/bhnd_nvram_data_tlv.c
View File

@ -88,7 +88,6 @@ struct bhnd_nvram_tlv_env {
#define NVRAM_TLV_ENVP_DATA_MAX_LEN \
(UINT8_MAX - sizeof(uint8_t) /* flags */)
static int bhnd_nvram_tlv_parse_size(
struct bhnd_nvram_io *io,
size_t *size);
@ -314,7 +313,7 @@ bhnd_nvram_tlv_serialize(bhnd_nvram_data_class *cls, bhnd_nvram_plist *props,
if (p != NULL) {
memcpy(p, &env, sizeof(env));
p += sizeof(env);
memcpy(p, name, name_len - 1);
p[name_len - 1] = '=';
p += name_len;
@ -415,7 +414,7 @@ bhnd_nvram_tlv_init(struct bhnd_nvram_tlv *tlv, struct bhnd_nvram_io *src)
static int
bhnd_nvram_tlv_new(struct bhnd_nvram_data *nv, struct bhnd_nvram_io *io)
{
struct bhnd_nvram_tlv *tlv;
int error;
@ -447,7 +446,6 @@ bhnd_nvram_tlv_count(struct bhnd_nvram_data *nv)
return (tlv->count);
}
static bhnd_nvram_plist *
bhnd_nvram_tlv_options(struct bhnd_nvram_data *nv)
{
@ -800,7 +798,7 @@ bhnd_nvram_tlv_get_env(struct bhnd_nvram_tlv *tlv, void *cookiep)
size_t navail;
size_t io_offset, io_size;
int error;
io_size = bhnd_nvram_io_getsize(tlv->data);
io_offset = bhnd_nvram_tlv_to_offset(tlv, cookiep);

2
sys/dev/bhnd/nvram/bhnd_nvram_io.c
View File

@ -66,7 +66,6 @@ bhnd_nvram_io_read(struct bhnd_nvram_io *io, size_t offset, void *buffer,
return (io->iops->read(io, offset, buffer, nbytes));
}
/**
* Attempt to fetch a pointer to @p io's internal read buffer, if
* supported by @p io.
@ -202,4 +201,3 @@ bhnd_nvram_io_free(struct bhnd_nvram_io *io)
{
return (io->iops->free(io));
}

2
sys/dev/bhnd/nvram/bhnd_nvram_iobuf.c
View File

@ -120,7 +120,6 @@ bhnd_nvram_iobuf_empty(size_t size, size_t capacity)
else
iobuf->buf = bhnd_nv_malloc(iobuf->capacity);
if (iobuf->buf == NULL) {
bhnd_nv_free(iobuf);
return (NULL);
@ -219,7 +218,6 @@ bhnd_nvram_iobuf_copy_range(struct bhnd_nvram_io *src, size_t offset,
return (io);
}
static void
bhnd_nvram_iobuf_free(struct bhnd_nvram_io *io)
{

38
sys/dev/bhnd/nvram/bhnd_nvram_ioptr.c
View File

@ -65,7 +65,7 @@ BHND_NVRAM_IOPS_DEFN(ioptr)
/**
* Allocate and return a new I/O context, mapping @p size bytes at @p ptr.
* The caller is responsible for deallocating the returned I/O context via
* bhnd_nvram_io_free().
*
@ -90,12 +90,12 @@ bhnd_nvram_ioptr_new(const void *ptr, size_t size, size_t capacity,
/* Sanity check the capacity */
if (size > capacity)
return (NULL);
/* Allocate I/O context */
ioptr = bhnd_nv_malloc(sizeof(*ioptr));
if (ioptr == NULL)
return (NULL);
ioptr->io.iops = &bhnd_nvram_ioptr_ops;
ioptr->ptr = __DECONST(void *, ptr);
ioptr->size = size;
@ -126,11 +126,11 @@ bhnd_nvram_ioptr_setsize(struct bhnd_nvram_io *io, size_t size)
/* Must be writable */
if (!(ioptr->flags & BHND_NVRAM_IOPTR_RDWR))
return (ENODEV);
/* Can't exceed the actual capacity */
if (size > ioptr->capacity)
return (ENXIO);
ioptr->size = size;
return (0);
}
@ -141,21 +141,21 @@ bhnd_nvram_ioptr_ptr(struct bhnd_nvram_ioptr *ioptr, size_t offset, void **ptr,
size_t nbytes, size_t *navail)
{
size_t avail;
/* Verify offset+nbytes fall within the buffer range */
if (offset > ioptr->size)
return (ENXIO);
avail = ioptr->size - offset;
if (avail < nbytes)
return (ENXIO);
/* Valid I/O range, provide a pointer to the buffer and the
* total count of available bytes */
*ptr = ((uint8_t *)ioptr->ptr) + offset;
if (navail != NULL)
*navail = avail;
return (0);
}
@ -166,16 +166,16 @@ bhnd_nvram_ioptr_read_ptr(struct bhnd_nvram_io *io, size_t offset,
struct bhnd_nvram_ioptr *ioptr;
void *writep;
int error;
ioptr = (struct bhnd_nvram_ioptr *) io;
/* Return a pointer into our backing buffer */
error = bhnd_nvram_ioptr_ptr(ioptr, offset, &writep, nbytes, navail);
if (error)
return (error);
*ptr = writep;
return (0);
}
@ -184,13 +184,13 @@ bhnd_nvram_ioptr_write_ptr(struct bhnd_nvram_io *io, size_t offset,
void **ptr, size_t nbytes, size_t *navail)
{
struct bhnd_nvram_ioptr *ioptr;
ioptr = (struct bhnd_nvram_ioptr *) io;
/* Must be writable */
if (!(ioptr->flags & BHND_NVRAM_IOPTR_RDWR))
return (ENODEV);
/* Return a pointer into our backing buffer */
return (bhnd_nvram_ioptr_ptr(ioptr, offset, ptr, nbytes, navail));
}
@ -201,11 +201,11 @@ bhnd_nvram_ioptr_read(struct bhnd_nvram_io *io, size_t offset, void *buffer,
{
const void *ptr;
int error;
/* Try to fetch a direct pointer for at least nbytes */
if ((error = bhnd_nvram_io_read_ptr(io, offset, &ptr, nbytes, NULL)))
return (error);
/* Copy out the requested data */
memcpy(buffer, ptr, nbytes);
return (0);
@ -217,11 +217,11 @@ bhnd_nvram_ioptr_write(struct bhnd_nvram_io *io, size_t offset,
{
void *ptr;
int error;
/* Try to fetch a direct pointer for at least nbytes */
if ((error = bhnd_nvram_io_write_ptr(io, offset, &ptr, nbytes, NULL)))
return (error);
/* Copy in the provided data */
memcpy(ptr, buffer, nbytes);
return (0);

3
sys/dev/bhnd/nvram/bhnd_nvram_iores.c
View File

@ -102,7 +102,7 @@ bhnd_nvram_iores_new(struct bhnd_resource *r, bus_size_t offset,
(uintmax_t)offset, (uintmax_t)offset);
return (NULL);
}
if (size > BUS_SPACE_MAXSIZE || offset > BUS_SPACE_MAXSIZE)
{
BHND_NV_LOG("offset %#jx+%#jx exceeds BUS_SPACE_MAXSIZE\n",
@ -210,7 +210,6 @@ bhnd_nvram_iores_validate_req(struct bhnd_nvram_iores *iores, size_t offset,
return (0);
}
static int
bhnd_nvram_iores_read(struct bhnd_nvram_io *io, size_t offset, void *buffer,
size_t nbytes)

11
sys/dev/bhnd/nvram/bhnd_nvram_store.c
View File

@ -199,7 +199,6 @@ bhnd_nvram_store_parse_new(struct bhnd_nvram_store **store,
struct bhnd_nvram_data *data;
int error;
/* Try to parse the data */
if ((error = bhnd_nvram_data_new(cls, &data, io)))
return (error);
@ -220,7 +219,7 @@ bhnd_nvram_store_parse_new(struct bhnd_nvram_store **store,
void
bhnd_nvram_store_free(struct bhnd_nvram_store *sc)
{
/* Clean up alias hash table */
for (size_t i = 0; i < nitems(sc->aliases); i++) {
bhnd_nvstore_alias *alias, *anext;
@ -384,7 +383,6 @@ bhnd_nvstore_parse_data(struct bhnd_nvram_store *sc)
return (0);
}
/**
* Parse and register path and path alias entries for all declarations found in
* the NVRAM data backing @p nvram.
@ -434,7 +432,6 @@ bhnd_nvstore_parse_path_entries(struct bhnd_nvram_store *sc)
return (0);
}
/**
* Merge exported per-path variables (uncommitted, committed, or both) into
* the empty @p merged property list.
@ -706,7 +703,7 @@ bhnd_nvram_store_export_child(struct bhnd_nvram_store *sc,
error = ENOMEM;
goto finished;
}
prefix_len = len;
} else if (relpath_len > 0) {
int len;
@ -834,7 +831,7 @@ bhnd_nvram_store_export(struct bhnd_nvram_store *sc, const char *path,
void *cookiep;
size_t num_dpath_flags;
int error;
*props = NULL;
unordered = NULL;
num_dpath_flags = 0;
@ -961,7 +958,7 @@ bhnd_nvram_store_export(struct bhnd_nvram_store *sc, const char *path,
/* Append to ordered result */
if ((error = bhnd_nvram_plist_append(*props, prop)))
goto failed;
/* Remove from unordered list */
bhnd_nvram_plist_remove(unordered, name);
}

15
sys/dev/bhnd/nvram/bhnd_nvram_subr.c
View File

@ -1041,7 +1041,6 @@ bhnd_nvram_parse_env(const char *env, size_t env_len, char delim,
return (0);
}
/**
* Parse a field value, returning the actual pointer to the first
* non-whitespace character and the total size of the field.
@ -1057,19 +1056,19 @@ size_t
bhnd_nvram_parse_field(const char **inp, size_t ilen, char delim)
{
const char *p, *sp;
/* Skip any leading whitespace */
for (sp = *inp; (size_t)(sp-*inp) < ilen && bhnd_nv_isspace(*sp); sp++)
continue;
*inp = sp;
/* Find the last field character */
for (p = *inp; (size_t)(p - *inp) < ilen; p++) {
if (*p == delim || *p == '\0')
break;
}
return (p - *inp);
}
@ -1091,9 +1090,9 @@ bhnd_nvram_trim_field(const char **inp, size_t ilen, char delim)
{
const char *sp;
size_t plen;
plen = bhnd_nvram_parse_field(inp, ilen, delim);
/* Trim trailing whitespace */
sp = *inp;
while (plen > 0) {
@ -1102,6 +1101,6 @@ bhnd_nvram_trim_field(const char **inp, size_t ilen, char delim)
plen--;
}
return (plen);
}

20
sys/dev/bhnd/nvram/bhnd_nvram_value.c
View File

@ -67,7 +67,6 @@ static int bhnd_nvram_val_set(bhnd_nvram_val *value, const void *inp,
static int bhnd_nvram_val_set_inline(bhnd_nvram_val *value,
const void *inp, size_t ilen, bhnd_nvram_type itype);
static int bhnd_nvram_val_encode_data(const void *inp, size_t ilen,
bhnd_nvram_type itype, void *outp, size_t *olen,
bhnd_nvram_type otype);
@ -205,7 +204,7 @@ bhnd_nvram_val_default_fmt(bhnd_nvram_type type)
case BHND_NVRAM_TYPE_BOOL_ARRAY:
return (&bhnd_nvram_val_bool_array_fmt);
}
/* Quiesce gcc4.2 */
BHND_NV_PANIC("bhnd nvram type %u unknown", type);
}
@ -311,22 +310,22 @@ bhnd_nvram_val_init_common(bhnd_nvram_val *value,
return (0);
}
/* Determine size when encoded in native format */
error = bhnd_nvram_value_coerce(inp, ilen, itype, NULL, &olen, otype);
if (error)
return (error);
/* Fetch reference to (or allocate) an appropriately sized buffer */
outp = bhnd_nvram_val_alloc_bytes(value, olen, otype, flags);
if (outp == NULL)
return (ENOMEM);
/* Perform encode */
error = bhnd_nvram_value_coerce(inp, ilen, itype, outp, &olen, otype);
if (error)
return (error);
return (0);
}
@ -412,7 +411,6 @@ bhnd_nvram_val_new(bhnd_nvram_val **value, const bhnd_nvram_val_fmt *fmt,
return (error);
}
/* Common initialization support for bhnd_nvram_val_convert_init() and
* bhnd_nvram_val_convert_new() */
static int
@ -461,12 +459,12 @@ bhnd_nvram_val_convert_common(bhnd_nvram_val *value,
/* Determine size when encoded in native format */
if ((error = bhnd_nvram_val_encode(src, NULL, &olen, otype)))
return (error);
/* Fetch reference to (or allocate) an appropriately sized buffer */
outp = bhnd_nvram_val_alloc_bytes(value, olen, otype, flags);
if (outp == NULL)
return (ENOMEM);
/* Perform encode */
if ((error = bhnd_nvram_val_encode(src, outp, &olen, otype)))
return (error);
@ -594,7 +592,6 @@ bhnd_nvram_val_copy(bhnd_nvram_val *value)
break;
}
/* Compute the new value's flags based on the source value */
switch (value->data_storage) {
case BHND_NVRAM_VAL_DATA_NONE:
@ -811,7 +808,6 @@ bhnd_nvram_val_encode_data(const void *inp, size_t ilen, bhnd_nvram_type itype,
}
}
/**
* Standard string/char array/char encoding implementation.
*
@ -1276,7 +1272,7 @@ bhnd_nvram_val_encode_int(const void *inp, size_t ilen, bhnd_nvram_type itype,
case BHND_NVRAM_TYPE_STRING:
case BHND_NVRAM_TYPE_STRING_ARRAY: {
ssize_t len;
/* Attempt to write the entry + NUL */
if (otype_signed) {
len = snprintf(outp, limit, "%" PRId64, intv.i64);

4
sys/dev/bhnd/nvram/bhnd_nvram_value.h
View File

@ -32,7 +32,6 @@
#ifndef _BHND_NVRAM_BHND_NVRAM_VALUE_H_
#define _BHND_NVRAM_BHND_NVRAM_VALUE_H_
#include <sys/refcount.h>
#ifdef _KERNEL
@ -93,7 +92,6 @@ int bhnd_nvram_val_vprintf(bhnd_nvram_val *value,
const char *fmt, char *outp, size_t *olen,
va_list ap);
const void *bhnd_nvram_val_bytes(bhnd_nvram_val *value,
size_t *olen, bhnd_nvram_type *otype);
@ -161,7 +159,7 @@ typedef enum {
* to a new heap allocation.
*/
BHND_NVRAM_VAL_STORAGE_AUTO = 0,
/**
* The value structure was heap allocated and is fully managed by the
* the NVRAM value API.

6
sys/dev/bhnd/nvram/bhnd_nvram_value_fmts.c
View File

@ -80,7 +80,6 @@ static const void *bhnd_nvram_val_bcm_macaddr_string_next(
bhnd_nvram_val *value, const void *prev,
size_t *len);
static int bhnd_nvram_val_bcm_int_filter(
const bhnd_nvram_val_fmt **fmt, const void *inp,
size_t ilen, bhnd_nvram_type itype);
@ -104,7 +103,6 @@ static int bhnd_nvram_val_bcm_leddc_encode_elem(
size_t ilen, void *outp, size_t *olen,
bhnd_nvram_type otype);
static int bhnd_nvram_val_bcmstr_encode(bhnd_nvram_val *value,
void *outp, size_t *olen, bhnd_nvram_type otype);
@ -198,7 +196,6 @@ static const bhnd_nvram_val_fmt bhnd_nvram_val_bcm_string_csv_fmt = {
.op_next = bhnd_nvram_val_bcmstr_csv_next,
};
/* Built-in format definitions */
#define BHND_NVRAM_VAL_FMT_NATIVE(_n, _type) \
const bhnd_nvram_val_fmt bhnd_nvram_val_ ## _n ## _fmt = { \
@ -754,7 +751,6 @@ bhnd_nvram_val_bcm_macaddr_string_filter(const bhnd_nvram_val_fmt **fmt,
}
}
/**
* MAC address string octet encoding.
*/
@ -843,7 +839,6 @@ bhnd_nvram_val_bcm_macaddr_string_next(bhnd_nvram_val *value, const void *prev,
return (next);
}
/**
* Determine whether @p inp is in octet string format, consisting of a
* fields of two hex characters, separated with ':' or '-' delimiters.
@ -949,7 +944,6 @@ bhnd_nvram_ident_octet_string(const char *inp, size_t ilen, char *delim,
return (true);
}
/**
* Determine whether @p inp is in hexadecimal, octal, or decimal string
* format.

5
sys/dev/bhnd/nvram/bhnd_nvram_value_prf.c
View File

@ -112,7 +112,6 @@ bhnd_nvram_val_printf(bhnd_nvram_val *value, const char *fmt, char *outp,
return (error);
}
/**
* Format a string representation of the elements of @p value using @p fmt,
* writing the result to @p outp.
@ -319,7 +318,7 @@ bhnd_nvram_val_vprintf(bhnd_nvram_val *value, const char *fmt, char *outp,
stop = false;
np = p+1;
switch (*p) {
case '#':
alt_form = true;
@ -547,7 +546,7 @@ bhnd_nvram_val_vprintf(bhnd_nvram_val *value, const char *fmt, char *outp,
size_t nremain = 0;
if (limit > nbytes)
nremain = limit - nbytes;
if (nremain >= delim_len)
memcpy(outp + nbytes, delim, delim_len);

3
sys/dev/bhnd/nvram/bhnd_nvram_value_subr.c
View File

@ -165,7 +165,7 @@ bhnd_nvram_value_nelem(const void *inp, size_t ilen, bhnd_nvram_type itype,
/* Determine string length */
slen = strnlen(p, nleft);
nleft -= slen;
/* Advance input */
p += slen;
@ -365,7 +365,6 @@ bhnd_nvram_value_size(const void *inp, size_t ilen, bhnd_nvram_type itype,
BHND_NV_PANIC("bhnd nvram type %u unknown", itype);
}
/**
* Format a string representation of @p inp using @p fmt, with, writing the
* result to @p outp.

2
sys/dev/bhnd/nvram/bhnd_sprom.c
View File

@ -196,7 +196,7 @@ bhnd_sprom_detach(device_t dev)
{
struct bhnd_sprom_softc *sc;
int error;
sc = device_get_softc(dev);
if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY)))

6
sys/dev/bhnd/siba/siba.c
View File

@ -134,7 +134,7 @@ siba_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
sc = device_get_softc(dev);
dinfo = device_get_ivars(child);
cfg = &dinfo->core_id.core_info;
switch (index) {
case BHND_IVAR_VENDOR:
*result = cfg->vendor;
@ -1194,7 +1194,7 @@ siba_map_cfg_resources(device_t dev, struct siba_devinfo *dinfo)
num_cfg);
return (ENXIO);
}
/* Fetch the core register address space */
addrspace = siba_find_addrspace(dinfo, BHND_PORT_DEVICE, 0, 0);
if (addrspace == NULL) {
@ -1401,7 +1401,7 @@ static device_method_t siba_methods[] = {
DEVMETHOD(device_detach, siba_detach),
DEVMETHOD(device_resume, siba_resume),
DEVMETHOD(device_suspend, siba_suspend),
/* Bus interface */
DEVMETHOD(bus_add_child, siba_add_child),
DEVMETHOD(bus_child_deleted, siba_child_deleted),

4
sys/dev/bhnd/siba/siba_bhndb.c
View File

@ -189,7 +189,7 @@ siba_bhndb_suspend_child(device_t dev, device_t child)
/* Suspend resource references to the child's config registers */
siba_bhndb_suspend_cfgblocks(dev, dinfo);
return (0);
}
@ -291,7 +291,7 @@ DEFINE_CLASS_2(bhnd, siba_bhndb_driver, siba_bhndb_methods,
sizeof(struct siba_softc), bhnd_bhndb_driver, siba_driver);
DRIVER_MODULE(siba_bhndb, bhndb, siba_bhndb_driver, bhnd_devclass, NULL, NULL);
MODULE_VERSION(siba_bhndb, 1);
MODULE_DEPEND(siba_bhndb, siba, 1, 1, 1);
MODULE_DEPEND(siba_bhndb, bhnd, 1, 1, 1);

3
sys/dev/bhnd/siba/siba_erom.c
View File

@ -54,7 +54,6 @@ __FBSDID("$FreeBSD$");
struct siba_erom;
struct siba_erom_io;
static int siba_eio_init(struct siba_erom_io *io,
struct bhnd_erom_io *eio, u_int ncores);
@ -509,7 +508,7 @@ siba_erom_lookup_core_addr(bhnd_erom_t *erom, const struct bhnd_core_match *desc
uint32_t am;
u_int am_offset;
u_int addrspace, cfg;
int error;
sc = (struct siba_erom *)erom;

7
sys/dev/bhnd/siba/siba_subr.c
View File

@ -84,7 +84,7 @@ struct siba_devinfo *
siba_alloc_dinfo(device_t bus)
{
struct siba_devinfo *dinfo;
dinfo = malloc(sizeof(struct siba_devinfo), M_BHND, M_NOWAIT|M_ZERO);
if (dinfo == NULL)
return NULL;
@ -157,7 +157,6 @@ siba_init_dinfo(device_t dev, device_t child, struct siba_devinfo *dinfo,
return (0);
}
/**
* Register and map all interrupts for @p dinfo.
*
@ -458,7 +457,7 @@ siba_addrspace_index(struct siba_core_id *core_id, bhnd_port_type port_type,
/* Port must be valid */
if (!siba_is_port_valid(core_id, port_type, port))
return (ENOENT);
if (port == 0)
idx = region;
else if (port == 1)
@ -629,7 +628,7 @@ int
siba_parse_admatch(uint32_t am, struct siba_admatch *admatch)
{
u_int am_type;
/* Extract the base address and size */
am_type = SIBA_REG_GET(am, AM_TYPE);
switch (am_type) {

1
sys/dev/bhnd/siba/sibareg.h
View File

@ -44,7 +44,6 @@
((_entry & SIBA_ ## _attr ## _MASK) \
>> SIBA_ ## _attr ## _SHIFT)
#define SIBA_ENUM_ADDR BHND_DEFAULT_CHIPC_ADDR /**< enumeration space */
#define SIBA_ENUM_SIZE 0x00100000 /**< size of the enumeration space */
#define SIBA_CORE_SIZE BHND_DEFAULT_CORE_SIZE /**< per-core register block size */

1
sys/dev/bhnd/siba/sibavar.h
View File

@ -227,7 +227,6 @@ struct siba_softc {
struct mtx mtx; /**< state mutex */
};
#define SIBA_LOCK_INIT(sc) \
mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF)
#define SIBA_LOCK(sc) mtx_lock(&(sc)->mtx)