Fix copy/paste typo in last revision. PMC0 control should be shifted 8
bits, not 6, on the PPC 970.
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@ -336,7 +336,7 @@
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#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */
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#define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */
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#define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */
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#define SPR_970MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector (970) */
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#define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */
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#define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */
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#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */
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#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */
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