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MFC r267062:

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Disable existing uncore hwpmc code for Nehalem and Westmere EX.
This commit is contained in:
kib 2014-06-18 05:35:09 +00:00
parent 13424f9f51
commit adb3a0aab0
4 changed files with 64 additions and 3 deletions
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46
lib/libpmc/libpmc.c
View File

@ -190,6 +190,11 @@ static const struct pmc_event_descr corei7_event_table[] =
__PMC_EV_ALIAS_COREI7() __PMC_EV_ALIAS_COREI7()
}; };
static const struct pmc_event_descr nehalem_ex_event_table[] =
{
__PMC_EV_ALIAS_COREI7()
};
static const struct pmc_event_descr haswell_event_table[] = static const struct pmc_event_descr haswell_event_table[] =
{ {
__PMC_EV_ALIAS_HASWELL() __PMC_EV_ALIAS_HASWELL()
@ -220,6 +225,11 @@ static const struct pmc_event_descr westmere_event_table[] =
__PMC_EV_ALIAS_WESTMERE() __PMC_EV_ALIAS_WESTMERE()
}; };
static const struct pmc_event_descr westmere_ex_event_table[] =
{
__PMC_EV_ALIAS_WESTMERE()
};
static const struct pmc_event_descr corei7uc_event_table[] = static const struct pmc_event_descr corei7uc_event_table[] =
{ {
__PMC_EV_ALIAS_COREI7UC() __PMC_EV_ALIAS_COREI7UC()
@ -255,12 +265,14 @@ PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TS
PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC);
@ -298,12 +310,14 @@ PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap);
PMC_CLASS_TABLE_DESC(core, IAP, core, iap); PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap);
PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap); PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap);
PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap);
PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap);
PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp); PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp);
@ -608,6 +622,8 @@ static struct pmc_event_alias core2_aliases_without_iaf[] = {
#define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf #define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf
#define corei7_aliases core2_aliases #define corei7_aliases core2_aliases
#define corei7_aliases_without_iaf core2_aliases_without_iaf #define corei7_aliases_without_iaf core2_aliases_without_iaf
#define nehalem_ex_aliases core2_aliases
#define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf
#define haswell_aliases core2_aliases #define haswell_aliases core2_aliases
#define haswell_aliases_without_iaf core2_aliases_without_iaf #define haswell_aliases_without_iaf core2_aliases_without_iaf
#define ivybridge_aliases core2_aliases #define ivybridge_aliases core2_aliases
@ -620,6 +636,8 @@ static struct pmc_event_alias core2_aliases_without_iaf[] = {
#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf #define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf
#define westmere_aliases core2_aliases #define westmere_aliases core2_aliases
#define westmere_aliases_without_iaf core2_aliases_without_iaf #define westmere_aliases_without_iaf core2_aliases_without_iaf
#define westmere_ex_aliases core2_aliases
#define westmere_ex_aliases_without_iaf core2_aliases_without_iaf
#define IAF_KW_OS "os" #define IAF_KW_OS "os"
#define IAF_KW_USR "usr" #define IAF_KW_USR "usr"
@ -863,7 +881,9 @@ iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
} else } else
return (-1); return (-1);
} else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) { cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE ||
cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX ||
cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) {
if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp);
} else } else
@ -2760,6 +2780,10 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
ev = corei7_event_table; ev = corei7_event_table;
count = PMC_EVENT_TABLE_SIZE(corei7); count = PMC_EVENT_TABLE_SIZE(corei7);
break; break;
case PMC_CPU_INTEL_NEHALEM_EX:
ev = nehalem_ex_event_table;
count = PMC_EVENT_TABLE_SIZE(nehalem_ex);
break;
case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_HASWELL:
ev = haswell_event_table; ev = haswell_event_table;
count = PMC_EVENT_TABLE_SIZE(haswell); count = PMC_EVENT_TABLE_SIZE(haswell);
@ -2784,6 +2808,10 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
ev = westmere_event_table; ev = westmere_event_table;
count = PMC_EVENT_TABLE_SIZE(westmere); count = PMC_EVENT_TABLE_SIZE(westmere);
break; break;
case PMC_CPU_INTEL_WESTMERE_EX:
ev = westmere_ex_event_table;
count = PMC_EVENT_TABLE_SIZE(westmere_ex);
break;
} }
break; break;
case PMC_CLASS_UCF: case PMC_CLASS_UCF:
@ -3079,6 +3107,9 @@ pmc_init(void)
pmc_class_table[n++] = &corei7uc_class_table_descr; pmc_class_table[n++] = &corei7uc_class_table_descr;
PMC_MDEP_INIT_INTEL_V2(corei7); PMC_MDEP_INIT_INTEL_V2(corei7);
break; break;
case PMC_CPU_INTEL_NEHALEM_EX:
PMC_MDEP_INIT_INTEL_V2(nehalem_ex);
break;
case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_HASWELL:
pmc_class_table[n++] = &ucf_class_table_descr; pmc_class_table[n++] = &ucf_class_table_descr;
pmc_class_table[n++] = &haswelluc_class_table_descr; pmc_class_table[n++] = &haswelluc_class_table_descr;
@ -3103,6 +3134,9 @@ pmc_init(void)
pmc_class_table[n++] = &westmereuc_class_table_descr; pmc_class_table[n++] = &westmereuc_class_table_descr;
PMC_MDEP_INIT_INTEL_V2(westmere); PMC_MDEP_INIT_INTEL_V2(westmere);
break; break;
case PMC_CPU_INTEL_WESTMERE_EX:
PMC_MDEP_INIT_INTEL_V2(westmere_ex);
break;
case PMC_CPU_INTEL_PIV: case PMC_CPU_INTEL_PIV:
PMC_MDEP_INIT(p4); PMC_MDEP_INIT(p4);
pmc_class_table[n] = &p4_class_table_descr; pmc_class_table[n] = &p4_class_table_descr;
@ -3237,6 +3271,11 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
ev = corei7_event_table; ev = corei7_event_table;
evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
break; break;
case PMC_CPU_INTEL_NEHALEM_EX:
ev = nehalem_ex_event_table;
evfence = nehalem_ex_event_table +
PMC_EVENT_TABLE_SIZE(nehalem_ex);
break;
case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_HASWELL:
ev = haswell_event_table; ev = haswell_event_table;
evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell); evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell);
@ -3261,6 +3300,11 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
ev = westmere_event_table; ev = westmere_event_table;
evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
break; break;
case PMC_CPU_INTEL_WESTMERE_EX:
ev = westmere_ex_event_table;
evfence = westmere_ex_event_table +
PMC_EVENT_TABLE_SIZE(westmere_ex);
break;
default: /* Unknown CPU type. */ default: /* Unknown CPU type. */
break; break;
} }

6
sys/dev/hwpmc/hwpmc_core.c
View File

@ -2021,6 +2021,7 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
switch (core_cputype) { switch (core_cputype) {
case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_COREI7:
case PMC_CPU_INTEL_NEHALEM_EX:
if (iap_event_corei7_ok_on_counter(ev, ri) == 0) if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
return (EINVAL); return (EINVAL);
break; break;
@ -2033,6 +2034,7 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
return (EINVAL); return (EINVAL);
break; break;
case PMC_CPU_INTEL_WESTMERE: case PMC_CPU_INTEL_WESTMERE:
case PMC_CPU_INTEL_WESTMERE_EX:
if (iap_event_westmere_ok_on_counter(ev, ri) == 0) if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
return (EINVAL); return (EINVAL);
break; break;
@ -2186,7 +2188,9 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
ev == PMC_EV_IAP_EVENT_BBH_01H) ev == PMC_EV_IAP_EVENT_BBH_01H)
return (EINVAL); return (EINVAL);
if ((core_cputype == PMC_CPU_INTEL_COREI7 || if ((core_cputype == PMC_CPU_INTEL_COREI7 ||
core_cputype == PMC_CPU_INTEL_WESTMERE) && core_cputype == PMC_CPU_INTEL_WESTMERE ||
core_cputype == PMC_CPU_INTEL_NEHALEM_EX ||
core_cputype == PMC_CPU_INTEL_WESTMERE_EX) &&
a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM)
return (EINVAL); return (EINVAL);
else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||

13
sys/dev/hwpmc/hwpmc_intel.c
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@ -139,15 +139,22 @@ pmc_intel_initialize(void)
* Per Intel document 253669-032 9/2009, * Per Intel document 253669-032 9/2009,
* pages A-2 and A-57 * pages A-2 and A-57
*/ */
case 0x2E:
cputype = PMC_CPU_INTEL_COREI7; cputype = PMC_CPU_INTEL_COREI7;
nclasses = 5; nclasses = 5;
break; break;
case 0x2E:
cputype = PMC_CPU_INTEL_NEHALEM_EX;
nclasses = 3;
break;
case 0x25: /* Per Intel document 253669-033US 12/2009. */ case 0x25: /* Per Intel document 253669-033US 12/2009. */
case 0x2C: /* Per Intel document 253669-033US 12/2009. */ case 0x2C: /* Per Intel document 253669-033US 12/2009. */
cputype = PMC_CPU_INTEL_WESTMERE; cputype = PMC_CPU_INTEL_WESTMERE;
nclasses = 5; nclasses = 5;
break; break;
case 0x2F: /* Westmere-EX, seen in wild */
cputype = PMC_CPU_INTEL_WESTMERE_EX;
nclasses = 3;
break;
case 0x2A: /* Per Intel document 253669-039US 05/2011. */ case 0x2A: /* Per Intel document 253669-039US 05/2011. */
cputype = PMC_CPU_INTEL_SANDYBRIDGE; cputype = PMC_CPU_INTEL_SANDYBRIDGE;
nclasses = 5; nclasses = 5;
@ -209,9 +216,11 @@ pmc_intel_initialize(void)
case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2:
case PMC_CPU_INTEL_CORE2EXTREME: case PMC_CPU_INTEL_CORE2EXTREME:
case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_COREI7:
case PMC_CPU_INTEL_NEHALEM_EX:
case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_IVYBRIDGE:
case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE:
case PMC_CPU_INTEL_WESTMERE: case PMC_CPU_INTEL_WESTMERE:
case PMC_CPU_INTEL_WESTMERE_EX:
case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
case PMC_CPU_INTEL_IVYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE_XEON:
case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_HASWELL:
@ -298,10 +307,12 @@ pmc_intel_finalize(struct pmc_mdep *md)
case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2:
case PMC_CPU_INTEL_CORE2EXTREME: case PMC_CPU_INTEL_CORE2EXTREME:
case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_COREI7:
case PMC_CPU_INTEL_NEHALEM_EX:
case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_HASWELL:
case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_IVYBRIDGE:
case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE:
case PMC_CPU_INTEL_WESTMERE: case PMC_CPU_INTEL_WESTMERE:
case PMC_CPU_INTEL_WESTMERE_EX:
case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
case PMC_CPU_INTEL_IVYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE_XEON:
pmc_core_finalize(md); pmc_core_finalize(md);

2
sys/sys/pmc.h
View File

@ -92,6 +92,8 @@
__PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \
__PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \
__PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \
__PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \
__PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \
__PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
__PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \
__PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \